drivers/clk/renesas/renesas-cpg-mssr.c

   1 /*
   2  * Renesas Clock Pulse Generator / Module Standby and Software Reset
   3  *
   4  * Copyright (C) 2015 Glider bvba
   5  *
   6  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
   7  *
   8  * Copyright (C) 2013 Ideas On Board SPRL
   9  * Copyright (C) 2015 Renesas Electronics Corp.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; version 2 of the License.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/clk/renesas.h>
  19 #include <linux/delay.h>
  20 #include <linux/device.h>
  21 #include <linux/init.h>
  22 #include <linux/mod_devicetable.h>
  23 #include <linux/module.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_clock.h>
  28 #include <linux/pm_domain.h>
  29 #include <linux/psci.h>
  30 #include <linux/reset-controller.h>
  31 #include <linux/slab.h>
  32
  33 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  34
  35 #include "renesas-cpg-mssr.h"
  36 #include "clk-div6.h"
  37
  38 #ifdef DEBUG
  39 #define WARN_DEBUG(x)   WARN_ON(x)
  40 #else
  41 #define WARN_DEBUG(x)   do { } while (0)
  42 #endif
  43
  44
  45 /*
  46  * Module Standby and Software Reset register offets.
  47  *
  48  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  49  * R-Car Gen2, R-Car Gen3, and RZ/G1.
  50  * These are NOT valid for R-Car Gen1 and RZ/A1!
  51  */
  52
  53 /*
  54  * Module Stop Status Register offsets
  55  */
  56
  57 static const u16 mstpsr[] = {
  58         0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  59         0x9A0, 0x9A4, 0x9A8, 0x9AC,
  60 };
  61
  62 #define MSTPSR(i)       mstpsr[i]
  63
  64
  65 /*
  66  * System Module Stop Control Register offsets
  67  */
  68
  69 static const u16 smstpcr[] = {
  70         0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  71         0x990, 0x994, 0x998, 0x99C,
  72 };
  73
  74 #define SMSTPCR(i)      smstpcr[i]
  75
  76
  77 /*
  78  * Software Reset Register offsets
  79  */
  80
  81 static const u16 srcr[] = {
  82         0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  83         0x920, 0x924, 0x928, 0x92C,
  84 };
  85
  86 #define SRCR(i)         srcr[i]
  87
  88
  89 /* Realtime Module Stop Control Register offsets */
  90 #define RMSTPCR(i)      (smstpcr[i] - 0x20)
  91
  92 /* Modem Module Stop Control Register offsets (r8a73a4) */
  93 #define MMSTPCR(i)      (smstpcr[i] + 0x20)
  94
  95 /* Software Reset Clearing Register offsets */
  96 #define SRSTCLR(i)      (0x940 + (i) * 4)
  97
  98
  99 /**
 100  * Clock Pulse Generator / Module Standby and Software Reset Private Data
 101  *
 102  * @rcdev: Optional reset controller entity
 103  * @dev: CPG/MSSR device
 104  * @base: CPG/MSSR register block base address
 105  * @rmw_lock: protects RMW register accesses
 106  * @clks: Array containing all Core and Module Clocks
 107  * @num_core_clks: Number of Core Clocks in clks[]
 108  * @num_mod_clks: Number of Module Clocks in clks[]
 109  * @last_dt_core_clk: ID of the last Core Clock exported to DT
 110  * @notifiers: Notifier chain to save/restore clock state for system resume
 111  * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
 112  * @smstpcr_saved[].val: Saved values of SMSTPCR[]
 113  */
 114 struct cpg_mssr_priv {
 115 #ifdef CONFIG_RESET_CONTROLLER
 116         struct reset_controller_dev rcdev;
 117 #endif
 118         struct device *dev;
 119         void __iomem *base;
 120         spinlock_t rmw_lock;
 121
 122         struct clk **clks;
 123         unsigned int num_core_clks;
 124         unsigned int num_mod_clks;
 125         unsigned int last_dt_core_clk;
 126
 127         struct raw_notifier_head notifiers;
 128         struct {
 129                 u32 mask;
 130                 u32 val;
 131         } smstpcr_saved[ARRAY_SIZE(smstpcr)];
 132 };
 133
 134
 135 /**
 136  * struct mstp_clock - MSTP gating clock
 137  * @hw: handle between common and hardware-specific interfaces
 138  * @index: MSTP clock number
 139  * @priv: CPG/MSSR private data
 140  */
 141 struct mstp_clock {
 142         struct clk_hw hw;
 143         u32 index;
 144         struct cpg_mssr_priv *priv;
 145 };
 146
 147 #define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
 148
 149 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
 150 {
 151         struct mstp_clock *clock = to_mstp_clock(hw);
 152         struct cpg_mssr_priv *priv = clock->priv;
 153         unsigned int reg = clock->index / 32;
 154         unsigned int bit = clock->index % 32;
 155         struct device *dev = priv->dev;
 156         u32 bitmask = BIT(bit);
 157         unsigned long flags;
 158         unsigned int i;
 159         u32 value;
 160
 161         dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
 162                 enable ? "ON" : "OFF");
 163         spin_lock_irqsave(&priv->rmw_lock, flags);
 164
 165         value = readl(priv->base + SMSTPCR(reg));
 166         if (enable)
 167                 value &= ~bitmask;
 168         else
 169                 value |= bitmask;
 170         writel(value, priv->base + SMSTPCR(reg));
 171
 172         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 173
 174         if (!enable)
 175                 return 0;
 176
 177         for (i = 1000; i > 0; --i) {
 178                 if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
 179                         break;
 180                 cpu_relax();
 181         }
 182
 183         if (!i) {
 184                 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
 185                         priv->base + SMSTPCR(reg), bit);
 186                 return -ETIMEDOUT;
 187         }
 188
 189         return 0;
 190 }
 191
 192 static int cpg_mstp_clock_enable(struct clk_hw *hw)
 193 {
 194         return cpg_mstp_clock_endisable(hw, true);
 195 }
 196
 197 static void cpg_mstp_clock_disable(struct clk_hw *hw)
 198 {
 199         cpg_mstp_clock_endisable(hw, false);
 200 }
 201
 202 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
 203 {
 204         struct mstp_clock *clock = to_mstp_clock(hw);
 205         struct cpg_mssr_priv *priv = clock->priv;
 206         u32 value;
 207
 208         value = readl(priv->base + MSTPSR(clock->index / 32));
 209
 210         return !(value & BIT(clock->index % 32));
 211 }
 212
 213 static const struct clk_ops cpg_mstp_clock_ops = {
 214         .enable = cpg_mstp_clock_enable,
 215         .disable = cpg_mstp_clock_disable,
 216         .is_enabled = cpg_mstp_clock_is_enabled,
 217 };
 218
 219 static
 220 struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
 221                                          void *data)
 222 {
 223         unsigned int clkidx = clkspec->args[1];
 224         struct cpg_mssr_priv *priv = data;
 225         struct device *dev = priv->dev;
 226         unsigned int idx;
 227         const char *type;
 228         struct clk *clk;
 229
 230         switch (clkspec->args[0]) {
 231         case CPG_CORE:
 232                 type = "core";
 233                 if (clkidx > priv->last_dt_core_clk) {
 234                         dev_err(dev, "Invalid %s clock index %u\n", type,
 235                                clkidx);
 236                         return ERR_PTR(-EINVAL);
 237                 }
 238                 clk = priv->clks[clkidx];
 239                 break;
 240
 241         case CPG_MOD:
 242                 type = "module";
 243                 idx = MOD_CLK_PACK(clkidx);
 244                 if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
 245                         dev_err(dev, "Invalid %s clock index %u\n", type,
 246                                 clkidx);
 247                         return ERR_PTR(-EINVAL);
 248                 }
 249                 clk = priv->clks[priv->num_core_clks + idx];
 250                 break;
 251
 252         default:
 253                 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
 254                 return ERR_PTR(-EINVAL);
 255         }
 256
 257         if (IS_ERR(clk))
 258                 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
 259                        PTR_ERR(clk));
 260         else
 261                 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
 262                         clkspec->args[0], clkspec->args[1], clk,
 263                         clk_get_rate(clk));
 264         return clk;
 265 }
 266
 267 static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
 268                                               const struct cpg_mssr_info *info,
 269                                               struct cpg_mssr_priv *priv)
 270 {
 271         struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;
 272         struct device *dev = priv->dev;
 273         unsigned int id = core->id, div = core->div;
 274         const char *parent_name;
 275
 276         WARN_DEBUG(id >= priv->num_core_clks);
 277         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 278
 279         if (!core->name) {
 280                 /* Skip NULLified clock */
 281                 return;
 282         }
 283
 284         switch (core->type) {
 285         case CLK_TYPE_IN:
 286                 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
 287                 break;
 288
 289         case CLK_TYPE_FF:
 290         case CLK_TYPE_DIV6P1:
 291         case CLK_TYPE_DIV6_RO:
 292                 WARN_DEBUG(core->parent >= priv->num_core_clks);
 293                 parent = priv->clks[core->parent];
 294                 if (IS_ERR(parent)) {
 295                         clk = parent;
 296                         goto fail;
 297                 }
 298
 299                 parent_name = __clk_get_name(parent);
 300
 301                 if (core->type == CLK_TYPE_DIV6_RO)
 302                         /* Multiply with the DIV6 register value */
 303                         div *= (readl(priv->base + core->offset) & 0x3f) + 1;
 304
 305                 if (core->type == CLK_TYPE_DIV6P1) {
 306                         clk = cpg_div6_register(core->name, 1, &parent_name,
 307                                                 priv->base + core->offset,
 308                                                 &priv->notifiers);
 309                 } else {
 310                         clk = clk_register_fixed_factor(NULL, core->name,
 311                                                         parent_name, 0,
 312                                                         core->mult, div);
 313                 }
 314                 break;
 315
 316         default:
 317                 if (info->cpg_clk_register)
 318                         clk = info->cpg_clk_register(dev, core, info,
 319                                                      priv->clks, priv->base,
 320                                                      &priv->notifiers);
 321                 else
 322                         dev_err(dev, "%s has unsupported core clock type %u\n",
 323                                 core->name, core->type);
 324                 break;
 325         }
 326
 327         if (IS_ERR_OR_NULL(clk))
 328                 goto fail;
 329
 330         dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 331         priv->clks[id] = clk;
 332         return;
 333
 334 fail:
 335         dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
 336                 core->name, PTR_ERR(clk));
 337 }
 338
 339 static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
 340                                              const struct cpg_mssr_info *info,
 341                                              struct cpg_mssr_priv *priv)
 342 {
 343         struct mstp_clock *clock = NULL;
 344         struct device *dev = priv->dev;
 345         unsigned int id = mod->id;
 346         struct clk_init_data init;
 347         struct clk *parent, *clk;
 348         const char *parent_name;
 349         unsigned int i;
 350
 351         WARN_DEBUG(id < priv->num_core_clks);
 352         WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
 353         WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
 354         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 355
 356         if (!mod->name) {
 357                 /* Skip NULLified clock */
 358                 return;
 359         }
 360
 361         parent = priv->clks[mod->parent];
 362         if (IS_ERR(parent)) {
 363                 clk = parent;
 364                 goto fail;
 365         }
 366
 367         clock = kzalloc(sizeof(*clock), GFP_KERNEL);
 368         if (!clock) {
 369                 clk = ERR_PTR(-ENOMEM);
 370                 goto fail;
 371         }
 372
 373         init.name = mod->name;
 374         init.ops = &cpg_mstp_clock_ops;
 375         init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
 376         for (i = 0; i < info->num_crit_mod_clks; i++)
 377                 if (id == info->crit_mod_clks[i]) {
 378                         dev_dbg(dev, "MSTP %s setting CLK_IS_CRITICAL\n",
 379                                 mod->name);
 380                         init.flags |= CLK_IS_CRITICAL;
 381                         break;
 382                 }
 383
 384         parent_name = __clk_get_name(parent);
 385         init.parent_names = &parent_name;
 386         init.num_parents = 1;
 387
 388         clock->index = id - priv->num_core_clks;
 389         clock->priv = priv;
 390         clock->hw.init = &init;
 391
 392         clk = clk_register(NULL, &clock->hw);
 393         if (IS_ERR(clk))
 394                 goto fail;
 395
 396         dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 397         priv->clks[id] = clk;
 398         priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
 399         return;
 400
 401 fail:
 402         dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
 403                 mod->name, PTR_ERR(clk));
 404         kfree(clock);
 405 }
 406
 407 struct cpg_mssr_clk_domain {
 408         struct generic_pm_domain genpd;
 409         struct device_node *np;
 410         unsigned int num_core_pm_clks;
 411         unsigned int core_pm_clks[0];
 412 };
 413
 414 static struct cpg_mssr_clk_domain *cpg_mssr_clk_domain;
 415
 416 static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
 417                                struct cpg_mssr_clk_domain *pd)
 418 {
 419         unsigned int i;
 420
 421         if (clkspec->np != pd->np || clkspec->args_count != 2)
 422                 return false;
 423
 424         switch (clkspec->args[0]) {
 425         case CPG_CORE:
 426                 for (i = 0; i < pd->num_core_pm_clks; i++)
 427                         if (clkspec->args[1] == pd->core_pm_clks[i])
 428                                 return true;
 429                 return false;
 430
 431         case CPG_MOD:
 432                 return true;
 433
 434         default:
 435                 return false;
 436         }
 437 }
 438
 439 int cpg_mssr_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 440 {
 441         struct cpg_mssr_clk_domain *pd = cpg_mssr_clk_domain;
 442         struct device_node *np = dev->of_node;
 443         struct of_phandle_args clkspec;
 444         struct clk *clk;
 445         int i = 0;
 446         int error;
 447
 448         if (!pd) {
 449                 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
 450                 return -EPROBE_DEFER;
 451         }
 452
 453         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 454                                            &clkspec)) {
 455                 if (cpg_mssr_is_pm_clk(&clkspec, pd))
 456                         goto found;
 457
 458                 of_node_put(clkspec.np);
 459                 i++;
 460         }
 461
 462         return 0;
 463
 464 found:
 465         clk = of_clk_get_from_provider(&clkspec);
 466         of_node_put(clkspec.np);
 467
 468         if (IS_ERR(clk))
 469                 return PTR_ERR(clk);
 470
 471         error = pm_clk_create(dev);
 472         if (error) {
 473                 dev_err(dev, "pm_clk_create failed %d\n", error);
 474                 goto fail_put;
 475         }
 476
 477         error = pm_clk_add_clk(dev, clk);
 478         if (error) {
 479                 dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
 480                 goto fail_destroy;
 481         }
 482
 483         return 0;
 484
 485 fail_destroy:
 486         pm_clk_destroy(dev);
 487 fail_put:
 488         clk_put(clk);
 489         return error;
 490 }
 491
 492 void cpg_mssr_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 493 {
 494         if (!pm_clk_no_clocks(dev))
 495                 pm_clk_destroy(dev);
 496 }
 497
 498 static int __init cpg_mssr_add_clk_domain(struct device *dev,
 499                                           const unsigned int *core_pm_clks,
 500                                           unsigned int num_core_pm_clks)
 501 {
 502         struct device_node *np = dev->of_node;
 503         struct generic_pm_domain *genpd;
 504         struct cpg_mssr_clk_domain *pd;
 505         size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
 506
 507         pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
 508         if (!pd)
 509                 return -ENOMEM;
 510
 511         pd->np = np;
 512         pd->num_core_pm_clks = num_core_pm_clks;
 513         memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
 514
 515         genpd = &pd->genpd;
 516         genpd->name = np->name;
 517         genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
 518                        GENPD_FLAG_ACTIVE_WAKEUP;
 519         genpd->attach_dev = cpg_mssr_attach_dev;
 520         genpd->detach_dev = cpg_mssr_detach_dev;
 521         pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
 522         cpg_mssr_clk_domain = pd;
 523
 524         of_genpd_add_provider_simple(np, genpd);
 525         return 0;
 526 }
 527
 528 #ifdef CONFIG_RESET_CONTROLLER
 529
 530 #define rcdev_to_priv(x)        container_of(x, struct cpg_mssr_priv, rcdev)
 531
 532 static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
 533                           unsigned long id)
 534 {
 535         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 536         unsigned int reg = id / 32;
 537         unsigned int bit = id % 32;
 538         u32 bitmask = BIT(bit);
 539
 540         dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
 541
 542         /* Reset module */
 543         writel(bitmask, priv->base + SRCR(reg));
 544
 545         /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
 546         udelay(35);
 547
 548         /* Release module from reset state */
 549         writel(bitmask, priv->base + SRSTCLR(reg));
 550
 551         return 0;
 552 }
 553
 554 static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
 555 {
 556         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 557         unsigned int reg = id / 32;
 558         unsigned int bit = id % 32;
 559         u32 bitmask = BIT(bit);
 560
 561         dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
 562
 563         writel(bitmask, priv->base + SRCR(reg));
 564         return 0;
 565 }
 566
 567 static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
 568                              unsigned long id)
 569 {
 570         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 571         unsigned int reg = id / 32;
 572         unsigned int bit = id % 32;
 573         u32 bitmask = BIT(bit);
 574
 575         dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
 576
 577         writel(bitmask, priv->base + SRSTCLR(reg));
 578         return 0;
 579 }
 580
 581 static int cpg_mssr_status(struct reset_controller_dev *rcdev,
 582                            unsigned long id)
 583 {
 584         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 585         unsigned int reg = id / 32;
 586         unsigned int bit = id % 32;
 587         u32 bitmask = BIT(bit);
 588
 589         return !!(readl(priv->base + SRCR(reg)) & bitmask);
 590 }
 591
 592 static const struct reset_control_ops cpg_mssr_reset_ops = {
 593         .reset = cpg_mssr_reset,
 594         .assert = cpg_mssr_assert,
 595         .deassert = cpg_mssr_deassert,
 596         .status = cpg_mssr_status,
 597 };
 598
 599 static int cpg_mssr_reset_xlate(struct reset_controller_dev *rcdev,
 600                                 const struct of_phandle_args *reset_spec)
 601 {
 602         struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
 603         unsigned int unpacked = reset_spec->args[0];
 604         unsigned int idx = MOD_CLK_PACK(unpacked);
 605
 606         if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {
 607                 dev_err(priv->dev, "Invalid reset index %u\n", unpacked);
 608                 return -EINVAL;
 609         }
 610
 611         return idx;
 612 }
 613
 614 static int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 615 {
 616         priv->rcdev.ops = &cpg_mssr_reset_ops;
 617         priv->rcdev.of_node = priv->dev->of_node;
 618         priv->rcdev.of_reset_n_cells = 1;
 619         priv->rcdev.of_xlate = cpg_mssr_reset_xlate;
 620         priv->rcdev.nr_resets = priv->num_mod_clks;
 621         return devm_reset_controller_register(priv->dev, &priv->rcdev);
 622 }
 623
 624 #else /* !CONFIG_RESET_CONTROLLER */
 625 static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
 626 {
 627         return 0;
 628 }
 629 #endif /* !CONFIG_RESET_CONTROLLER */
 630
 631
 632 static const struct of_device_id cpg_mssr_match[] = {
 633 #ifdef CONFIG_CLK_R8A7743
 634         {
 635                 .compatible = "renesas,r8a7743-cpg-mssr",
 636                 .data = &r8a7743_cpg_mssr_info,
 637         },
 638 #endif
 639 #ifdef CONFIG_CLK_R8A7745
 640         {
 641                 .compatible = "renesas,r8a7745-cpg-mssr",
 642                 .data = &r8a7745_cpg_mssr_info,
 643         },
 644 #endif
 645 #ifdef CONFIG_CLK_R8A77470
 646         {
 647                 .compatible = "renesas,r8a77470-cpg-mssr",
 648                 .data = &r8a77470_cpg_mssr_info,
 649         },
 650 #endif
 651 #ifdef CONFIG_CLK_R8A7790
 652         {
 653                 .compatible = "renesas,r8a7790-cpg-mssr",
 654                 .data = &r8a7790_cpg_mssr_info,
 655         },
 656 #endif
 657 #ifdef CONFIG_CLK_R8A7791
 658         {
 659                 .compatible = "renesas,r8a7791-cpg-mssr",
 660                 .data = &r8a7791_cpg_mssr_info,
 661         },
 662         /* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
 663         {
 664                 .compatible = "renesas,r8a7793-cpg-mssr",
 665                 .data = &r8a7791_cpg_mssr_info,
 666         },
 667 #endif
 668 #ifdef CONFIG_CLK_R8A7792
 669         {
 670                 .compatible = "renesas,r8a7792-cpg-mssr",
 671                 .data = &r8a7792_cpg_mssr_info,
 672         },
 673 #endif
 674 #ifdef CONFIG_CLK_R8A7794
 675         {
 676                 .compatible = "renesas,r8a7794-cpg-mssr",
 677                 .data = &r8a7794_cpg_mssr_info,
 678         },
 679 #endif
 680 #ifdef CONFIG_CLK_R8A7795
 681         {
 682                 .compatible = "renesas,r8a7795-cpg-mssr",
 683                 .data = &r8a7795_cpg_mssr_info,
 684         },
 685 #endif
 686 #ifdef CONFIG_CLK_R8A7796
 687         {
 688                 .compatible = "renesas,r8a7796-cpg-mssr",
 689                 .data = &r8a7796_cpg_mssr_info,
 690         },
 691 #endif
 692 #ifdef CONFIG_CLK_R8A77965
 693         {
 694                 .compatible = "renesas,r8a77965-cpg-mssr",
 695                 .data = &r8a77965_cpg_mssr_info,
 696         },
 697 #endif
 698 #ifdef CONFIG_CLK_R8A77970
 699         {
 700                 .compatible = "renesas,r8a77970-cpg-mssr",
 701                 .data = &r8a77970_cpg_mssr_info,
 702         },
 703 #endif
 704 #ifdef CONFIG_CLK_R8A77980
 705         {
 706                 .compatible = "renesas,r8a77980-cpg-mssr",
 707                 .data = &r8a77980_cpg_mssr_info,
 708         },
 709 #endif
 710 #ifdef CONFIG_CLK_R8A77990
 711         {
 712                 .compatible = "renesas,r8a77990-cpg-mssr",
 713                 .data = &r8a77990_cpg_mssr_info,
 714         },
 715 #endif
 716 #ifdef CONFIG_CLK_R8A77995
 717         {
 718                 .compatible = "renesas,r8a77995-cpg-mssr",
 719                 .data = &r8a77995_cpg_mssr_info,
 720         },
 721 #endif
 722         { /* sentinel */ }
 723 };
 724
 725 static void cpg_mssr_del_clk_provider(void *data)
 726 {
 727         of_clk_del_provider(data);
 728 }
 729
 730 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
 731 static int cpg_mssr_suspend_noirq(struct device *dev)
 732 {
 733         struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
 734         unsigned int reg;
 735
 736         /* This is the best we can do to check for the presence of PSCI */
 737         if (!psci_ops.cpu_suspend)
 738                 return 0;
 739
 740         /* Save module registers with bits under our control */
 741         for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
 742                 if (priv->smstpcr_saved[reg].mask)
 743                         priv->smstpcr_saved[reg].val =
 744                                 readl(priv->base + SMSTPCR(reg));
 745         }
 746
 747         /* Save core clocks */
 748         raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
 749
 750         return 0;
 751 }
 752
 753 static int cpg_mssr_resume_noirq(struct device *dev)
 754 {
 755         struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
 756         unsigned int reg, i;
 757         u32 mask, oldval, newval;
 758
 759         /* This is the best we can do to check for the presence of PSCI */
 760         if (!psci_ops.cpu_suspend)
 761                 return 0;
 762
 763         /* Restore core clocks */
 764         raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
 765
 766         /* Restore module clocks */
 767         for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
 768                 mask = priv->smstpcr_saved[reg].mask;
 769                 if (!mask)
 770                         continue;
 771
 772                 oldval = readl(priv->base + SMSTPCR(reg));
 773                 newval = oldval & ~mask;
 774                 newval |= priv->smstpcr_saved[reg].val & mask;
 775                 if (newval == oldval)
 776                         continue;
 777
 778                 writel(newval, priv->base + SMSTPCR(reg));
 779
 780                 /* Wait until enabled clocks are really enabled */
 781                 mask &= ~priv->smstpcr_saved[reg].val;
 782                 if (!mask)
 783                         continue;
 784
 785                 for (i = 1000; i > 0; --i) {
 786                         oldval = readl(priv->base + MSTPSR(reg));
 787                         if (!(oldval & mask))
 788                                 break;
 789                         cpu_relax();
 790                 }
 791
 792                 if (!i)
 793                         dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
 794                                  priv->base + SMSTPCR(reg), oldval & mask);
 795         }
 796
 797         return 0;
 798 }
 799
 800 static const struct dev_pm_ops cpg_mssr_pm = {
 801         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
 802                                       cpg_mssr_resume_noirq)
 803 };
 804 #define DEV_PM_OPS      &cpg_mssr_pm
 805 #else
 806 #define DEV_PM_OPS      NULL
 807 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
 808
 809 static int __init cpg_mssr_probe(struct platform_device *pdev)
 810 {
 811         struct device *dev = &pdev->dev;
 812         struct device_node *np = dev->of_node;
 813         const struct cpg_mssr_info *info;
 814         struct cpg_mssr_priv *priv;
 815         unsigned int nclks, i;
 816         struct resource *res;
 817         struct clk **clks;
 818         int error;
 819
 820         info = of_device_get_match_data(dev);
 821         if (info->init) {
 822                 error = info->init(dev);
 823                 if (error)
 824                         return error;
 825         }
 826
 827         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 828         if (!priv)
 829                 return -ENOMEM;
 830
 831         priv->dev = dev;
 832         spin_lock_init(&priv->rmw_lock);
 833
 834         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 835         priv->base = devm_ioremap_resource(dev, res);
 836         if (IS_ERR(priv->base))
 837                 return PTR_ERR(priv->base);
 838
 839         nclks = info->num_total_core_clks + info->num_hw_mod_clks;
 840         clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
 841         if (!clks)
 842                 return -ENOMEM;
 843
 844         dev_set_drvdata(dev, priv);
 845         priv->clks = clks;
 846         priv->num_core_clks = info->num_total_core_clks;
 847         priv->num_mod_clks = info->num_hw_mod_clks;
 848         priv->last_dt_core_clk = info->last_dt_core_clk;
 849         RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
 850
 851         for (i = 0; i < nclks; i++)
 852                 clks[i] = ERR_PTR(-ENOENT);
 853
 854         for (i = 0; i < info->num_core_clks; i++)
 855                 cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
 856
 857         for (i = 0; i < info->num_mod_clks; i++)
 858                 cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
 859
 860         error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
 861         if (error)
 862                 return error;
 863
 864         error = devm_add_action_or_reset(dev,
 865                                          cpg_mssr_del_clk_provider,
 866                                          np);
 867         if (error)
 868                 return error;
 869
 870         error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
 871                                         info->num_core_pm_clks);
 872         if (error)
 873                 return error;
 874
 875         error = cpg_mssr_reset_controller_register(priv);
 876         if (error)
 877                 return error;
 878
 879         return 0;
 880 }
 881
 882 static struct platform_driver cpg_mssr_driver = {
 883         .driver         = {
 884                 .name   = "renesas-cpg-mssr",
 885                 .of_match_table = cpg_mssr_match,
 886                 .pm = DEV_PM_OPS,
 887         },
 888 };
 889
 890 static int __init cpg_mssr_init(void)
 891 {
 892         return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
 893 }
 894
 895 subsys_initcall(cpg_mssr_init);
 896
 897 void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
 898                                    unsigned int num_core_clks,
 899                                    unsigned int first_clk,
 900                                    unsigned int last_clk)
 901 {
 902         unsigned int i;
 903
 904         for (i = 0; i < num_core_clks; i++)
 905                 if (core_clks[i].id >= first_clk &&
 906                     core_clks[i].id <= last_clk)
 907                         core_clks[i].name = NULL;
 908 }
 909
 910 void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
 911                              unsigned int num_mod_clks,
 912                              const unsigned int *clks, unsigned int n)
 913 {
 914         unsigned int i, j;
 915
 916         for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
 917                 if (mod_clks[i].id == clks[j]) {
 918                         mod_clks[i].name = NULL;
 919                         j++;
 920                 }
 921 }
 922
 923 void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
 924                               unsigned int num_mod_clks,
 925                               const struct mssr_mod_reparent *clks,
 926                               unsigned int n)
 927 {
 928         unsigned int i, j;
 929
 930         for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
 931                 if (mod_clks[i].id == clks[j].clk) {
 932                         mod_clks[i].parent = clks[j].parent;
 933                         j++;
 934                 }
 935 }
 936
 937 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
 938 MODULE_LICENSE("GPL v2");