drivers/clk/samsung/clk-s3c2443.c

   1 /*
   2  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Common Clock Framework support for S3C2443 and following SoCs.
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/syscore_ops.h>
  15 #include <linux/reboot.h>
  16
  17 #include <dt-bindings/clock/s3c2443.h>
  18
  19 #include "clk.h"
  20 #include "clk-pll.h"
  21
  22 /* S3C2416 clock controller register offsets */
  23 #define LOCKCON0        0x00
  24 #define LOCKCON1        0x04
  25 #define MPLLCON         0x10
  26 #define EPLLCON         0x18
  27 #define EPLLCON_K       0x1C
  28 #define CLKSRC          0x20
  29 #define CLKDIV0         0x24
  30 #define CLKDIV1         0x28
  31 #define CLKDIV2         0x2C
  32 #define HCLKCON         0x30
  33 #define PCLKCON         0x34
  34 #define SCLKCON         0x38
  35 #define SWRST           0x44
  36
  37 /* the soc types */
  38 enum supported_socs {
  39         S3C2416,
  40         S3C2443,
  41         S3C2450,
  42 };
  43
  44 static void __iomem *reg_base;
  45
  46 #ifdef CONFIG_PM_SLEEP
  47 static struct samsung_clk_reg_dump *s3c2443_save;
  48
  49 /*
  50  * list of controller registers to be saved and restored during a
  51  * suspend/resume cycle.
  52  */
  53 static unsigned long s3c2443_clk_regs[] __initdata = {
  54         LOCKCON0,
  55         LOCKCON1,
  56         MPLLCON,
  57         EPLLCON,
  58         EPLLCON_K,
  59         CLKSRC,
  60         CLKDIV0,
  61         CLKDIV1,
  62         CLKDIV2,
  63         PCLKCON,
  64         HCLKCON,
  65         SCLKCON,
  66 };
  67
  68 static int s3c2443_clk_suspend(void)
  69 {
  70         samsung_clk_save(reg_base, s3c2443_save,
  71                                 ARRAY_SIZE(s3c2443_clk_regs));
  72
  73         return 0;
  74 }
  75
  76 static void s3c2443_clk_resume(void)
  77 {
  78         samsung_clk_restore(reg_base, s3c2443_save,
  79                                 ARRAY_SIZE(s3c2443_clk_regs));
  80 }
  81
  82 static struct syscore_ops s3c2443_clk_syscore_ops = {
  83         .suspend = s3c2443_clk_suspend,
  84         .resume = s3c2443_clk_resume,
  85 };
  86
  87 static void __init s3c2443_clk_sleep_init(void)
  88 {
  89         s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs,
  90                                                 ARRAY_SIZE(s3c2443_clk_regs));
  91         if (!s3c2443_save) {
  92                 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
  93                         __func__);
  94                 return;
  95         }
  96
  97         register_syscore_ops(&s3c2443_clk_syscore_ops);
  98         return;
  99 }
 100 #else
 101 static void __init s3c2443_clk_sleep_init(void) {}
 102 #endif
 103
 104 PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
 105 PNAME(esysclk_p) = { "epllref", "epll" };
 106 PNAME(mpllref_p) = { "xti", "mdivclk" };
 107 PNAME(msysclk_p) = { "mpllref", "mpll" };
 108 PNAME(armclk_p) = { "armdiv" , "hclk" };
 109 PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
 110
 111 static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
 112         MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
 113         MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
 114         MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
 115         MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
 116         MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
 117         MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
 118 };
 119
 120 static struct clk_div_table hclk_d[] = {
 121         { .val = 0, .div = 1 },
 122         { .val = 1, .div = 2 },
 123         { .val = 3, .div = 4 },
 124         { /* sentinel */ },
 125 };
 126
 127 static struct clk_div_table mdivclk_d[] = {
 128         { .val = 0, .div = 1 },
 129         { .val = 1, .div = 3 },
 130         { .val = 2, .div = 5 },
 131         { .val = 3, .div = 7 },
 132         { .val = 4, .div = 9 },
 133         { .val = 5, .div = 11 },
 134         { .val = 6, .div = 13 },
 135         { .val = 7, .div = 15 },
 136         { /* sentinel */ },
 137 };
 138
 139 static struct samsung_div_clock s3c2443_common_dividers[] __initdata = {
 140         DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d),
 141         DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2),
 142         DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
 143         DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
 144         DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2),
 145         DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8),
 146         DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4),
 147         DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4),
 148         DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2),
 149         DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2),
 150 };
 151
 152 static struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
 153         GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
 154         GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
 155         GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
 156         GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
 157         GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
 158         GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
 159         GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
 160         GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
 161         GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
 162         GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
 163         GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
 164         GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
 165         GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
 166         GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
 167         GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
 168         GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
 169         GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
 170         GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
 171         GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
 172         GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
 173         GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
 174         GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
 175         GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
 176         GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
 177         GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
 178         GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
 179         GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
 180         GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
 181         GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
 182         GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
 183         GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
 184 };
 185
 186 static struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
 187         ALIAS(MSYSCLK, NULL, "msysclk"),
 188         ALIAS(ARMCLK, NULL, "armclk"),
 189         ALIAS(MPLL, NULL, "mpll"),
 190         ALIAS(EPLL, NULL, "epll"),
 191         ALIAS(HCLK, NULL, "hclk"),
 192         ALIAS(HCLK_SSMC, NULL, "nand"),
 193         ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
 194         ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
 195         ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
 196         ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"),
 197         ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
 198         ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
 199         ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
 200         ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"),
 201         ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
 202         ALIAS(PCLK_PWM, NULL, "timers"),
 203         ALIAS(PCLK_RTC, NULL, "rtc"),
 204         ALIAS(PCLK_WDT, NULL, "watchdog"),
 205         ALIAS(PCLK_ADC, NULL, "adc"),
 206         ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"),
 207         ALIAS(HCLK_USBD, NULL, "usb-device"),
 208         ALIAS(HCLK_USBH, NULL, "usb-host"),
 209         ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
 210         ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"),
 211         ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"),
 212         ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
 213         ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
 214         ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"),
 215         ALIAS(SCLK_I2S0, NULL, "i2s-if"),
 216         ALIAS(HCLK_LCD, NULL, "lcd"),
 217         ALIAS(SCLK_FIMD, NULL, "sclk_fimd"),
 218 };
 219
 220 /* S3C2416 specific clocks */
 221
 222 static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
 223         PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
 224         PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
 225 };
 226
 227 PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
 228 PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
 229 PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
 230
 231 static struct clk_div_table armdiv_s3c2416_d[] = {
 232         { .val = 0, .div = 1 },
 233         { .val = 1, .div = 2 },
 234         { .val = 2, .div = 3 },
 235         { .val = 3, .div = 4 },
 236         { .val = 5, .div = 6 },
 237         { .val = 7, .div = 8 },
 238         { /* sentinel */ },
 239 };
 240
 241 static struct samsung_div_clock s3c2416_dividers[] __initdata = {
 242         DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d),
 243         DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4),
 244         DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2),
 245 };
 246
 247 static struct samsung_mux_clock s3c2416_muxes[] __initdata = {
 248         MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
 249         MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
 250         MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
 251 };
 252
 253 static struct samsung_gate_clock s3c2416_gates[] __initdata = {
 254         GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
 255         GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
 256         GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
 257         GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
 258         GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
 259         GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
 260         GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
 261 };
 262
 263 static struct samsung_clock_alias s3c2416_aliases[] __initdata = {
 264         ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
 265         ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
 266         ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"),
 267         ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
 268         ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
 269         ALIAS(ARMDIV, NULL, "armdiv"),
 270 };
 271
 272 /* S3C2443 specific clocks */
 273
 274 static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
 275         PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
 276         PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
 277 };
 278
 279 static struct clk_div_table armdiv_s3c2443_d[] = {
 280         { .val = 0, .div = 1 },
 281         { .val = 8, .div = 2 },
 282         { .val = 2, .div = 3 },
 283         { .val = 9, .div = 4 },
 284         { .val = 10, .div = 6 },
 285         { .val = 11, .div = 8 },
 286         { .val = 13, .div = 12 },
 287         { .val = 15, .div = 16 },
 288         { /* sentinel */ },
 289 };
 290
 291 static struct samsung_div_clock s3c2443_dividers[] __initdata = {
 292         DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d),
 293         DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
 294 };
 295
 296 static struct samsung_gate_clock s3c2443_gates[] __initdata = {
 297         GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
 298         GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
 299         GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
 300         GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
 301         GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
 302         GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
 303 };
 304
 305 static struct samsung_clock_alias s3c2443_aliases[] __initdata = {
 306         ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
 307         ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
 308         ALIAS(SCLK_CAM, NULL, "camif-upll"),
 309         ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"),
 310         ALIAS(PCLK_SDI, NULL, "sdi"),
 311         ALIAS(HCLK_CFC, NULL, "cfc"),
 312         ALIAS(ARMDIV, NULL, "armdiv"),
 313 };
 314
 315 /* S3C2450 specific clocks */
 316
 317 PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
 318 PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" };
 319 PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
 320
 321 static struct samsung_div_clock s3c2450_dividers[] __initdata = {
 322         DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
 323         DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2),
 324         DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4),
 325         DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4),
 326 };
 327
 328 static struct samsung_mux_clock s3c2450_muxes[] __initdata = {
 329         MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
 330         MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1),
 331         MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2),
 332 };
 333
 334 static struct samsung_gate_clock s3c2450_gates[] __initdata = {
 335         GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
 336         GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
 337         GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
 338         GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
 339         GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
 340         GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
 341         GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
 342         GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),
 343 };
 344
 345 static struct samsung_clock_alias s3c2450_aliases[] __initdata = {
 346         ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"),
 347         ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"),
 348         ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"),
 349         ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"),
 350 };
 351
 352 static int s3c2443_restart(struct notifier_block *this,
 353                            unsigned long mode, void *cmd)
 354 {
 355         __raw_writel(0x533c2443, reg_base + SWRST);
 356         return NOTIFY_DONE;
 357 }
 358
 359 static struct notifier_block s3c2443_restart_handler = {
 360         .notifier_call = s3c2443_restart,
 361         .priority = 129,
 362 };
 363
 364 /*
 365  * fixed rate clocks generated outside the soc
 366  * Only necessary until the devicetree-move is complete
 367  */
 368 static struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
 369         FRATE(0, "xti", NULL, 0, 0),
 370         FRATE(0, "ext", NULL, 0, 0),
 371         FRATE(0, "ext_i2s", NULL, 0, 0),
 372         FRATE(0, "ext_uart", NULL, 0, 0),
 373 };
 374
 375 static void __init s3c2443_common_clk_register_fixed_ext(
 376                 struct samsung_clk_provider *ctx, unsigned long xti_f)
 377 {
 378         s3c2443_common_frate_clks[0].fixed_rate = xti_f;
 379         samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
 380                                 ARRAY_SIZE(s3c2443_common_frate_clks));
 381 }
 382
 383 void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
 384                                     int current_soc,
 385                                     void __iomem *base)
 386 {
 387         struct samsung_clk_provider *ctx;
 388         int ret;
 389         reg_base = base;
 390
 391         if (np) {
 392                 reg_base = of_iomap(np, 0);
 393                 if (!reg_base)
 394                         panic("%s: failed to map registers\n", __func__);
 395         }
 396
 397         ctx = samsung_clk_init(np, reg_base, NR_CLKS);
 398
 399         /* Register external clocks only in non-dt cases */
 400         if (!np)
 401                 s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
 402
 403         /* Register PLLs. */
 404         if (current_soc == S3C2416 || current_soc == S3C2450)
 405                 samsung_clk_register_pll(ctx, s3c2416_pll_clks,
 406                                 ARRAY_SIZE(s3c2416_pll_clks), reg_base);
 407         else
 408                 samsung_clk_register_pll(ctx, s3c2443_pll_clks,
 409                                 ARRAY_SIZE(s3c2443_pll_clks), reg_base);
 410
 411         /* Register common internal clocks. */
 412         samsung_clk_register_mux(ctx, s3c2443_common_muxes,
 413                         ARRAY_SIZE(s3c2443_common_muxes));
 414         samsung_clk_register_div(ctx, s3c2443_common_dividers,
 415                         ARRAY_SIZE(s3c2443_common_dividers));
 416         samsung_clk_register_gate(ctx, s3c2443_common_gates,
 417                 ARRAY_SIZE(s3c2443_common_gates));
 418         samsung_clk_register_alias(ctx, s3c2443_common_aliases,
 419                 ARRAY_SIZE(s3c2443_common_aliases));
 420
 421         /* Register SoC-specific clocks. */
 422         switch (current_soc) {
 423         case S3C2450:
 424                 samsung_clk_register_div(ctx, s3c2450_dividers,
 425                                 ARRAY_SIZE(s3c2450_dividers));
 426                 samsung_clk_register_mux(ctx, s3c2450_muxes,
 427                                 ARRAY_SIZE(s3c2450_muxes));
 428                 samsung_clk_register_gate(ctx, s3c2450_gates,
 429                                 ARRAY_SIZE(s3c2450_gates));
 430                 samsung_clk_register_alias(ctx, s3c2450_aliases,
 431                                 ARRAY_SIZE(s3c2450_aliases));
 432                 /* fall through, as s3c2450 extends the s3c2416 clocks */
 433         case S3C2416:
 434                 samsung_clk_register_div(ctx, s3c2416_dividers,
 435                                 ARRAY_SIZE(s3c2416_dividers));
 436                 samsung_clk_register_mux(ctx, s3c2416_muxes,
 437                                 ARRAY_SIZE(s3c2416_muxes));
 438                 samsung_clk_register_gate(ctx, s3c2416_gates,
 439                                 ARRAY_SIZE(s3c2416_gates));
 440                 samsung_clk_register_alias(ctx, s3c2416_aliases,
 441                                 ARRAY_SIZE(s3c2416_aliases));
 442                 break;
 443         case S3C2443:
 444                 samsung_clk_register_div(ctx, s3c2443_dividers,
 445                                 ARRAY_SIZE(s3c2443_dividers));
 446                 samsung_clk_register_gate(ctx, s3c2443_gates,
 447                                 ARRAY_SIZE(s3c2443_gates));
 448                 samsung_clk_register_alias(ctx, s3c2443_aliases,
 449                                 ARRAY_SIZE(s3c2443_aliases));
 450                 break;
 451         }
 452
 453         s3c2443_clk_sleep_init();
 454
 455         samsung_clk_of_add_provider(np, ctx);
 456
 457         ret = register_restart_handler(&s3c2443_restart_handler);
 458         if (ret)
 459                 pr_warn("cannot register restart handler, %d\n", ret);
 460 }
 461
 462 static void __init s3c2416_clk_init(struct device_node *np)
 463 {
 464         s3c2443_common_clk_init(np, 0, S3C2416, NULL);
 465 }
 466 CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init);
 467
 468 static void __init s3c2443_clk_init(struct device_node *np)
 469 {
 470         s3c2443_common_clk_init(np, 0, S3C2443, NULL);
 471 }
 472 CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init);
 473
 474 static void __init s3c2450_clk_init(struct device_node *np)
 475 {
 476         s3c2443_common_clk_init(np, 0, S3C2450, NULL);
 477 }
 478 CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init);