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Linux 4.19.133
[linux/fpc-iii.git] / drivers / clk / sunxi-ng / ccu-sun4i-a10.c
blob129ebd2588fdcffe0ddcaf8cae447780b20969f9
1 /*
2 * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
3 * Copyright (c) 2017 Maxime Ripard.
4 * Copyright (c) 2017 Jonathan Liu.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/clk-provider.h>
17 #include <linux/of_address.h>
18
19 #include "ccu_common.h"
20 #include "ccu_reset.h"
21
22 #include "ccu_div.h"
23 #include "ccu_gate.h"
24 #include "ccu_mp.h"
25 #include "ccu_mult.h"
26 #include "ccu_nk.h"
27 #include "ccu_nkm.h"
28 #include "ccu_nkmp.h"
29 #include "ccu_nm.h"
30 #include "ccu_phase.h"
31 #include "ccu_sdm.h"
32
33 #include "ccu-sun4i-a10.h"
34
35 static struct ccu_nkmp pll_core_clk = {
36 .enable = BIT(31),
37 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
38 .k = _SUNXI_CCU_MULT(4, 2),
39 .m = _SUNXI_CCU_DIV(0, 2),
40 .p = _SUNXI_CCU_DIV(16, 2),
41 .common = {
42 .reg = 0x000,
43 .hw.init = CLK_HW_INIT("pll-core",
44 "hosc",
45 &ccu_nkmp_ops,
46 0),
47 },
48 };
49
50 /*
51 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
52 * the base (2x, 4x and 8x), and one variable divider (the one true
53 * pll audio).
54 *
55 * With sigma-delta modulation for fractional-N on the audio PLL,
56 * we have to use specific dividers. This means the variable divider
57 * can no longer be used, as the audio codec requests the exact clock
58 * rates we support through this mechanism. So we now hard code the
59 * variable divider to 1. This means the clock rates will no longer
60 * match the clock names.
61 */
62 #define SUN4I_PLL_AUDIO_REG 0x008
63
64 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
65 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
66 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
67 };
68
69 static struct ccu_nm pll_audio_base_clk = {
70 .enable = BIT(31),
71 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
72 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
73 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
74 0x00c, BIT(31)),
75 .common = {
76 .reg = 0x008,
77 .features = CCU_FEATURE_SIGMA_DELTA_MOD,
78 .hw.init = CLK_HW_INIT("pll-audio-base",
79 "hosc",
80 &ccu_nm_ops,
81 0),
82 },
83
84 };
85
86 static struct ccu_mult pll_video0_clk = {
87 .enable = BIT(31),
88 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
89 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
90 270000000, 297000000),
91 .common = {
92 .reg = 0x010,
93 .features = (CCU_FEATURE_FRACTIONAL |
94 CCU_FEATURE_ALL_PREDIV),
95 .prediv = 8,
96 .hw.init = CLK_HW_INIT("pll-video0",
97 "hosc",
98 &ccu_mult_ops,
99 0),
100 },
101 };
102
103 static struct ccu_nkmp pll_ve_sun4i_clk = {
104 .enable = BIT(31),
105 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
106 .k = _SUNXI_CCU_MULT(4, 2),
107 .m = _SUNXI_CCU_DIV(0, 2),
108 .p = _SUNXI_CCU_DIV(16, 2),
109 .common = {
110 .reg = 0x018,
111 .hw.init = CLK_HW_INIT("pll-ve",
112 "hosc",
113 &ccu_nkmp_ops,
114 0),
115 },
116 };
117
118 static struct ccu_nk pll_ve_sun7i_clk = {
119 .enable = BIT(31),
120 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
121 .k = _SUNXI_CCU_MULT(4, 2),
122 .common = {
123 .reg = 0x018,
124 .hw.init = CLK_HW_INIT("pll-ve",
125 "hosc",
126 &ccu_nk_ops,
127 0),
128 },
129 };
130
131 static struct ccu_nk pll_ddr_base_clk = {
132 .enable = BIT(31),
133 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
134 .k = _SUNXI_CCU_MULT(4, 2),
135 .common = {
136 .reg = 0x020,
137 .hw.init = CLK_HW_INIT("pll-ddr-base",
138 "hosc",
139 &ccu_nk_ops,
140 0),
141 },
142 };
143
144 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
145 CLK_IS_CRITICAL);
146
147 static struct ccu_div pll_ddr_other_clk = {
148 .div = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
149 .common = {
150 .reg = 0x020,
151 .hw.init = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
152 &ccu_div_ops,
153 0),
154 },
155 };
156
157 static struct ccu_nk pll_periph_base_clk = {
158 .enable = BIT(31),
159 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
160 .k = _SUNXI_CCU_MULT(4, 2),
161 .common = {
162 .reg = 0x028,
163 .hw.init = CLK_HW_INIT("pll-periph-base",
164 "hosc",
165 &ccu_nk_ops,
166 0),
167 },
168 };
169
170 static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
171 2, 1, CLK_SET_RATE_PARENT);
172
173 /* Not documented on A10 */
174 static struct ccu_div pll_periph_sata_clk = {
175 .enable = BIT(14),
176 .div = _SUNXI_CCU_DIV(0, 2),
177 .fixed_post_div = 6,
178 .common = {
179 .reg = 0x028,
180 .features = CCU_FEATURE_FIXED_POSTDIV,
181 .hw.init = CLK_HW_INIT("pll-periph-sata",
182 "pll-periph-base",
183 &ccu_div_ops, 0),
184 },
185 };
186
187 static struct ccu_mult pll_video1_clk = {
188 .enable = BIT(31),
189 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
190 .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
191 270000000, 297000000),
192 .common = {
193 .reg = 0x030,
194 .features = (CCU_FEATURE_FRACTIONAL |
195 CCU_FEATURE_ALL_PREDIV),
196 .prediv = 8,
197 .hw.init = CLK_HW_INIT("pll-video1",
198 "hosc",
199 &ccu_mult_ops,
200 0),
201 },
202 };
203
204 /* Not present on A10 */
205 static struct ccu_nk pll_gpu_clk = {
206 .enable = BIT(31),
207 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
208 .k = _SUNXI_CCU_MULT(4, 2),
209 .common = {
210 .reg = 0x040,
211 .hw.init = CLK_HW_INIT("pll-gpu",
212 "hosc",
213 &ccu_nk_ops,
214 0),
215 },
216 };
217
218 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
219
220 static const char *const cpu_parents[] = { "osc32k", "hosc",
221 "pll-core", "pll-periph" };
222 static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
223 { .index = 3, .div = 3, },
224 };
225
226 #define SUN4I_AHB_REG 0x054
227 static struct ccu_mux cpu_clk = {
228 .mux = {
229 .shift = 16,
230 .width = 2,
231 .fixed_predivs = cpu_predivs,
232 .n_predivs = ARRAY_SIZE(cpu_predivs),
233 },
234 .common = {
235 .reg = 0x054,
236 .features = CCU_FEATURE_FIXED_PREDIV,
237 .hw.init = CLK_HW_INIT_PARENTS("cpu",
238 cpu_parents,
239 &ccu_mux_ops,
240 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
241 }
242 };
243
244 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
245
246 static struct ccu_div ahb_sun4i_clk = {
247 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
248 .common = {
249 .reg = 0x054,
250 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
251 },
252 };
253
254 static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
255 "pll-periph" };
256 static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
257 { .index = 1, .div = 2, },
258 { /* Sentinel */ },
259 };
260 static struct ccu_div ahb_sun7i_clk = {
261 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
262 .mux = {
263 .shift = 6,
264 .width = 2,
265 .fixed_predivs = ahb_sun7i_predivs,
266 .n_predivs = ARRAY_SIZE(ahb_sun7i_predivs),
267 },
268
269 .common = {
270 .reg = 0x054,
271 .hw.init = CLK_HW_INIT_PARENTS("ahb",
272 ahb_sun7i_parents,
273 &ccu_div_ops,
274 0),
275 },
276 };
277
278 static struct clk_div_table apb0_div_table[] = {
279 { .val = 0, .div = 2 },
280 { .val = 1, .div = 2 },
281 { .val = 2, .div = 4 },
282 { .val = 3, .div = 8 },
283 { /* Sentinel */ },
284 };
285 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
286 0x054, 8, 2, apb0_div_table, 0);
287
288 static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
289 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
290 0, 5, /* M */
291 16, 2, /* P */
292 24, 2, /* mux */
293 0);
294
295 /* Not present on A20 */
296 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
297 0x05c, BIT(31), 0);
298
299 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
300 0x060, BIT(0), 0);
301 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
302 0x060, BIT(1), 0);
303 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
304 0x060, BIT(2), 0);
305 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
306 0x060, BIT(3), 0);
307 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
308 0x060, BIT(4), 0);
309 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
310 0x060, BIT(5), 0);
311 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
312 0x060, BIT(6), 0);
313 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
314 0x060, BIT(7), 0);
315 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
316 0x060, BIT(8), 0);
317 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
318 0x060, BIT(9), 0);
319 static SUNXI_CCU_GATE(ahb_mmc2_clk, "ahb-mmc2", "ahb",
320 0x060, BIT(10), 0);
321 static SUNXI_CCU_GATE(ahb_mmc3_clk, "ahb-mmc3", "ahb",
322 0x060, BIT(11), 0);
323 static SUNXI_CCU_GATE(ahb_ms_clk, "ahb-ms", "ahb",
324 0x060, BIT(12), 0);
325 static SUNXI_CCU_GATE(ahb_nand_clk, "ahb-nand", "ahb",
326 0x060, BIT(13), 0);
327 static SUNXI_CCU_GATE(ahb_sdram_clk, "ahb-sdram", "ahb",
328 0x060, BIT(14), CLK_IS_CRITICAL);
329
330 static SUNXI_CCU_GATE(ahb_ace_clk, "ahb-ace", "ahb",
331 0x060, BIT(16), 0);
332 static SUNXI_CCU_GATE(ahb_emac_clk, "ahb-emac", "ahb",
333 0x060, BIT(17), 0);
334 static SUNXI_CCU_GATE(ahb_ts_clk, "ahb-ts", "ahb",
335 0x060, BIT(18), 0);
336 static SUNXI_CCU_GATE(ahb_spi0_clk, "ahb-spi0", "ahb",
337 0x060, BIT(20), 0);
338 static SUNXI_CCU_GATE(ahb_spi1_clk, "ahb-spi1", "ahb",
339 0x060, BIT(21), 0);
340 static SUNXI_CCU_GATE(ahb_spi2_clk, "ahb-spi2", "ahb",
341 0x060, BIT(22), 0);
342 static SUNXI_CCU_GATE(ahb_spi3_clk, "ahb-spi3", "ahb",
343 0x060, BIT(23), 0);
344 static SUNXI_CCU_GATE(ahb_pata_clk, "ahb-pata", "ahb",
345 0x060, BIT(24), 0);
346 /* Not documented on A20 */
347 static SUNXI_CCU_GATE(ahb_sata_clk, "ahb-sata", "ahb",
348 0x060, BIT(25), 0);
349 /* Not present on A20 */
350 static SUNXI_CCU_GATE(ahb_gps_clk, "ahb-gps", "ahb",
351 0x060, BIT(26), 0);
352 /* Not present on A10 */
353 static SUNXI_CCU_GATE(ahb_hstimer_clk, "ahb-hstimer", "ahb",
354 0x060, BIT(28), 0);
355
356 static SUNXI_CCU_GATE(ahb_ve_clk, "ahb-ve", "ahb",
357 0x064, BIT(0), 0);
358 static SUNXI_CCU_GATE(ahb_tvd_clk, "ahb-tvd", "ahb",
359 0x064, BIT(1), 0);
360 static SUNXI_CCU_GATE(ahb_tve0_clk, "ahb-tve0", "ahb",
361 0x064, BIT(2), 0);
362 static SUNXI_CCU_GATE(ahb_tve1_clk, "ahb-tve1", "ahb",
363 0x064, BIT(3), 0);
364 static SUNXI_CCU_GATE(ahb_lcd0_clk, "ahb-lcd0", "ahb",
365 0x064, BIT(4), 0);
366 static SUNXI_CCU_GATE(ahb_lcd1_clk, "ahb-lcd1", "ahb",
367 0x064, BIT(5), 0);
368 static SUNXI_CCU_GATE(ahb_csi0_clk, "ahb-csi0", "ahb",
369 0x064, BIT(8), 0);
370 static SUNXI_CCU_GATE(ahb_csi1_clk, "ahb-csi1", "ahb",
371 0x064, BIT(9), 0);
372 /* Not present on A10 */
373 static SUNXI_CCU_GATE(ahb_hdmi1_clk, "ahb-hdmi1", "ahb",
374 0x064, BIT(10), 0);
375 static SUNXI_CCU_GATE(ahb_hdmi0_clk, "ahb-hdmi0", "ahb",
376 0x064, BIT(11), 0);
377 static SUNXI_CCU_GATE(ahb_de_be0_clk, "ahb-de-be0", "ahb",
378 0x064, BIT(12), 0);
379 static SUNXI_CCU_GATE(ahb_de_be1_clk, "ahb-de-be1", "ahb",
380 0x064, BIT(13), 0);
381 static SUNXI_CCU_GATE(ahb_de_fe0_clk, "ahb-de-fe0", "ahb",
382 0x064, BIT(14), 0);
383 static SUNXI_CCU_GATE(ahb_de_fe1_clk, "ahb-de-fe1", "ahb",
384 0x064, BIT(15), 0);
385 /* Not present on A10 */
386 static SUNXI_CCU_GATE(ahb_gmac_clk, "ahb-gmac", "ahb",
387 0x064, BIT(17), 0);
388 static SUNXI_CCU_GATE(ahb_mp_clk, "ahb-mp", "ahb",
389 0x064, BIT(18), 0);
390 static SUNXI_CCU_GATE(ahb_gpu_clk, "ahb-gpu", "ahb",
391 0x064, BIT(20), 0);
392
393 static SUNXI_CCU_GATE(apb0_codec_clk, "apb0-codec", "apb0",
394 0x068, BIT(0), 0);
395 static SUNXI_CCU_GATE(apb0_spdif_clk, "apb0-spdif", "apb0",
396 0x068, BIT(1), 0);
397 static SUNXI_CCU_GATE(apb0_ac97_clk, "apb0-ac97", "apb0",
398 0x068, BIT(2), 0);
399 static SUNXI_CCU_GATE(apb0_i2s0_clk, "apb0-i2s0", "apb0",
400 0x068, BIT(3), 0);
401 /* Not present on A10 */
402 static SUNXI_CCU_GATE(apb0_i2s1_clk, "apb0-i2s1", "apb0",
403 0x068, BIT(4), 0);
404 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
405 0x068, BIT(5), 0);
406 static SUNXI_CCU_GATE(apb0_ir0_clk, "apb0-ir0", "apb0",
407 0x068, BIT(6), 0);
408 static SUNXI_CCU_GATE(apb0_ir1_clk, "apb0-ir1", "apb0",
409 0x068, BIT(7), 0);
410 /* Not present on A10 */
411 static SUNXI_CCU_GATE(apb0_i2s2_clk, "apb0-i2s2", "apb0",
412 0x068, BIT(8), 0);
413 static SUNXI_CCU_GATE(apb0_keypad_clk, "apb0-keypad", "apb0",
414 0x068, BIT(10), 0);
415
416 static SUNXI_CCU_GATE(apb1_i2c0_clk, "apb1-i2c0", "apb1",
417 0x06c, BIT(0), 0);
418 static SUNXI_CCU_GATE(apb1_i2c1_clk, "apb1-i2c1", "apb1",
419 0x06c, BIT(1), 0);
420 static SUNXI_CCU_GATE(apb1_i2c2_clk, "apb1-i2c2", "apb1",
421 0x06c, BIT(2), 0);
422 /* Not present on A10 */
423 static SUNXI_CCU_GATE(apb1_i2c3_clk, "apb1-i2c3", "apb1",
424 0x06c, BIT(3), 0);
425 static SUNXI_CCU_GATE(apb1_can_clk, "apb1-can", "apb1",
426 0x06c, BIT(4), 0);
427 static SUNXI_CCU_GATE(apb1_scr_clk, "apb1-scr", "apb1",
428 0x06c, BIT(5), 0);
429 static SUNXI_CCU_GATE(apb1_ps20_clk, "apb1-ps20", "apb1",
430 0x06c, BIT(6), 0);
431 static SUNXI_CCU_GATE(apb1_ps21_clk, "apb1-ps21", "apb1",
432 0x06c, BIT(7), 0);
433 /* Not present on A10 */
434 static SUNXI_CCU_GATE(apb1_i2c4_clk, "apb1-i2c4", "apb1",
435 0x06c, BIT(15), 0);
436 static SUNXI_CCU_GATE(apb1_uart0_clk, "apb1-uart0", "apb1",
437 0x06c, BIT(16), 0);
438 static SUNXI_CCU_GATE(apb1_uart1_clk, "apb1-uart1", "apb1",
439 0x06c, BIT(17), 0);
440 static SUNXI_CCU_GATE(apb1_uart2_clk, "apb1-uart2", "apb1",
441 0x06c, BIT(18), 0);
442 static SUNXI_CCU_GATE(apb1_uart3_clk, "apb1-uart3", "apb1",
443 0x06c, BIT(19), 0);
444 static SUNXI_CCU_GATE(apb1_uart4_clk, "apb1-uart4", "apb1",
445 0x06c, BIT(20), 0);
446 static SUNXI_CCU_GATE(apb1_uart5_clk, "apb1-uart5", "apb1",
447 0x06c, BIT(21), 0);
448 static SUNXI_CCU_GATE(apb1_uart6_clk, "apb1-uart6", "apb1",
449 0x06c, BIT(22), 0);
450 static SUNXI_CCU_GATE(apb1_uart7_clk, "apb1-uart7", "apb1",
451 0x06c, BIT(23), 0);
452
453 static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
454 "pll-ddr-other" };
455 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
456 0, 4, /* M */
457 16, 2, /* P */
458 24, 2, /* mux */
459 BIT(31), /* gate */
460 0);
461
462 /* Undocumented on A10 */
463 static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
464 0, 4, /* M */
465 16, 2, /* P */
466 24, 2, /* mux */
467 BIT(31), /* gate */
468 0);
469
470 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
471 0, 4, /* M */
472 16, 2, /* P */
473 24, 2, /* mux */
474 BIT(31), /* gate */
475 0);
476
477 /* MMC output and sample clocks are not present on A10 */
478 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
479 0x088, 8, 3, 0);
480 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
481 0x088, 20, 3, 0);
482
483 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
484 0, 4, /* M */
485 16, 2, /* P */
486 24, 2, /* mux */
487 BIT(31), /* gate */
488 0);
489
490 /* MMC output and sample clocks are not present on A10 */
491 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
492 0x08c, 8, 3, 0);
493 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
494 0x08c, 20, 3, 0);
495
496 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
497 0, 4, /* M */
498 16, 2, /* P */
499 24, 2, /* mux */
500 BIT(31), /* gate */
501 0);
502
503 /* MMC output and sample clocks are not present on A10 */
504 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
505 0x090, 8, 3, 0);
506 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
507 0x090, 20, 3, 0);
508
509 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
510 0, 4, /* M */
511 16, 2, /* P */
512 24, 2, /* mux */
513 BIT(31), /* gate */
514 0);
515
516 /* MMC output and sample clocks are not present on A10 */
517 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
518 0x094, 8, 3, 0);
519 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
520 0x094, 20, 3, 0);
521
522 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
523 0, 4, /* M */
524 16, 2, /* P */
525 24, 2, /* mux */
526 BIT(31), /* gate */
527 0);
528
529 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
530 0, 4, /* M */
531 16, 2, /* P */
532 24, 2, /* mux */
533 BIT(31), /* gate */
534 0);
535
536 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
537 0, 4, /* M */
538 16, 2, /* P */
539 24, 2, /* mux */
540 BIT(31), /* gate */
541 0);
542
543 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
544 0, 4, /* M */
545 16, 2, /* P */
546 24, 2, /* mux */
547 BIT(31), /* gate */
548 0);
549
550 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
551 0, 4, /* M */
552 16, 2, /* P */
553 24, 2, /* mux */
554 BIT(31), /* gate */
555 0);
556
557 /* Undocumented on A10 */
558 static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
559 0, 4, /* M */
560 16, 2, /* P */
561 24, 2, /* mux */
562 BIT(31), /* gate */
563 0);
564
565 /* TODO: Check whether A10 actually supports osc32k as 4th parent? */
566 static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
567 "pll-ddr-other" };
568 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
569 0, 4, /* M */
570 16, 2, /* P */
571 24, 2, /* mux */
572 BIT(31), /* gate */
573 0);
574
575 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
576 0, 4, /* M */
577 16, 2, /* P */
578 24, 2, /* mux */
579 BIT(31), /* gate */
580 0);
581 static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
582 "pll-ddr-other", "osc32k" };
583 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
584 0, 4, /* M */
585 16, 2, /* P */
586 24, 2, /* mux */
587 BIT(31), /* gate */
588 0);
589
590 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
591 0, 4, /* M */
592 16, 2, /* P */
593 24, 2, /* mux */
594 BIT(31), /* gate */
595 0);
596
597 static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
598 "pll-audio-2x", "pll-audio" };
599 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
600 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
601
602 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
603 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
604
605 /* Undocumented on A10 */
606 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
607 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
608
609 static const char *const keypad_parents[] = { "hosc", "losc"};
610 static const u8 keypad_table[] = { 0, 2 };
611 static struct ccu_mp keypad_clk = {
612 .enable = BIT(31),
613 .m = _SUNXI_CCU_DIV(0, 5),
614 .p = _SUNXI_CCU_DIV(16, 2),
615 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
616 .common = {
617 .reg = 0x0c4,
618 .hw.init = CLK_HW_INIT_PARENTS("keypad",
619 keypad_parents,
620 &ccu_mp_ops,
621 0),
622 },
623 };
624
625 /*
626 * SATA supports external clock as parent via BIT(24) and is probably an
627 * optional crystal or oscillator that can be connected to the
628 * SATA-CLKM / SATA-CLKP pins.
629 */
630 static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
631 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
632 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
633
634
635 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "pll-periph",
636 0x0cc, BIT(6), 0);
637 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "pll-periph",
638 0x0cc, BIT(7), 0);
639 static SUNXI_CCU_GATE(usb_phy_clk, "usb-phy", "pll-periph",
640 0x0cc, BIT(8), 0);
641
642 /* TODO: GPS CLK 0x0d0 */
643
644 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
645 0, 4, /* M */
646 16, 2, /* P */
647 24, 2, /* mux */
648 BIT(31), /* gate */
649 0);
650
651 /* Not present on A10 */
652 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
653 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
654
655 /* Not present on A10 */
656 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
657 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
658
659 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
660 0x100, BIT(0), 0);
661 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "pll-ddr",
662 0x100, BIT(1), 0);
663 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "pll-ddr",
664 0x100, BIT(2), 0);
665 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "pll-ddr",
666 0x100, BIT(3), 0);
667 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
668 0x100, BIT(4), 0);
669 static SUNXI_CCU_GATE(dram_tve0_clk, "dram-tve0", "pll-ddr",
670 0x100, BIT(5), 0);
671 static SUNXI_CCU_GATE(dram_tve1_clk, "dram-tve1", "pll-ddr",
672 0x100, BIT(6), 0);
673
674 /* Clock seems to be critical only on sun4i */
675 static SUNXI_CCU_GATE(dram_out_clk, "dram-out", "pll-ddr",
676 0x100, BIT(15), CLK_IS_CRITICAL);
677 static SUNXI_CCU_GATE(dram_de_fe1_clk, "dram-de-fe1", "pll-ddr",
678 0x100, BIT(24), 0);
679 static SUNXI_CCU_GATE(dram_de_fe0_clk, "dram-de-fe0", "pll-ddr",
680 0x100, BIT(25), 0);
681 static SUNXI_CCU_GATE(dram_de_be0_clk, "dram-de-be0", "pll-ddr",
682 0x100, BIT(26), 0);
683 static SUNXI_CCU_GATE(dram_de_be1_clk, "dram-de-be1", "pll-ddr",
684 0x100, BIT(27), 0);
685 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "pll-ddr",
686 0x100, BIT(28), 0);
687 static SUNXI_CCU_GATE(dram_ace_clk, "dram-ace", "pll-ddr",
688 0x100, BIT(29), 0);
689
690 static const char *const de_parents[] = { "pll-video0", "pll-video1",
691 "pll-ddr-other" };
692 static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
693 0x104, 0, 4, 24, 2, BIT(31), 0);
694
695 static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
696 0x108, 0, 4, 24, 2, BIT(31), 0);
697
698 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
699 0x10c, 0, 4, 24, 2, BIT(31), 0);
700
701 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
702 0x110, 0, 4, 24, 2, BIT(31), 0);
703
704 /* Undocumented on A10 */
705 static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
706 0x114, 0, 4, 24, 2, BIT(31), 0);
707
708 static const char *const disp_parents[] = { "pll-video0", "pll-video1",
709 "pll-video0-2x", "pll-video1-2x" };
710 static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
711 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
712 static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
713 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
714
715 static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
716 "pll-ddr-other", "pll-periph" };
717
718 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
719 csi_sclk_parents,
720 0x120, 0, 4, 24, 2, BIT(31), 0);
721
722 /* TVD clock setup for A10 */
723 static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
724 static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
725 0x128, 24, 1, BIT(31), 0);
726
727 /* TVD clock setup for A20 */
728 static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
729 "tvd-sclk2", tvd_parents,
730 0x128,
731 0, 4, /* M */
732 16, 4, /* P */
733 8, 1, /* mux */
734 BIT(15), /* gate */
735 0);
736
737 static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
738 0x128, 0, 4, BIT(31), 0);
739
740 static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
741 disp_parents,
742 0x12c, 0, 4, 24, 2, BIT(31),
743 CLK_SET_RATE_PARENT);
744
745 static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
746 "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
747 0x12c, 11, 1, BIT(15),
748 CLK_SET_RATE_PARENT);
749
750 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
751 disp_parents,
752 0x130, 0, 4, 24, 2, BIT(31),
753 CLK_SET_RATE_PARENT);
754
755 static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
756 "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
757 0x130, 11, 1, BIT(15),
758 CLK_SET_RATE_PARENT);
759
760 static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
761 "pll-video0-2x", "pll-video1-2x"};
762 static const u8 csi_table[] = { 0, 1, 2, 5, 6};
763 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
764 csi_parents, csi_table,
765 0x134, 0, 5, 24, 3, BIT(31), 0);
766
767 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
768 csi_parents, csi_table,
769 0x138, 0, 5, 24, 3, BIT(31), 0);
770
771 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
772
773 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
774 0x140, BIT(31), CLK_SET_RATE_PARENT);
775
776 static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
777
778 static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
779 static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
780 0x148, 0, 4, 24, 1, BIT(31), 0);
781
782 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
783 0x150, 0, 4, 24, 2, BIT(31),
784 CLK_SET_RATE_PARENT);
785
786 static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
787 "pll-ddr-other",
788 "pll-video1" };
789 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
790 0x154, 0, 4, 24, 2, BIT(31),
791 CLK_SET_RATE_PARENT);
792
793 static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
794 "pll-ddr-other", "pll-video1",
795 "pll-gpu" };
796 static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
797 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
798 gpu_parents_sun7i, gpu_table_sun7i,
799 0x154, 0, 4, 24, 3, BIT(31),
800 CLK_SET_RATE_PARENT);
801
802 static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
803 "pll-ddr-other" };
804 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
805 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
806 0);
807 static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
808 "pll-ddr-other" };
809 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
810 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
811 CLK_IS_CRITICAL);
812
813 static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
814
815 static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
816 static const u8 hdmi1_table[] = { 0, 1};
817 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
818 hdmi1_parents, hdmi1_table,
819 0x17c, 0, 4, 24, 2, BIT(31),
820 CLK_SET_RATE_PARENT);
821
822 static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
823 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
824 { .index = 0, .div = 750, },
825 };
826
827 static struct ccu_mp out_a_clk = {
828 .enable = BIT(31),
829 .m = _SUNXI_CCU_DIV(8, 5),
830 .p = _SUNXI_CCU_DIV(20, 2),
831 .mux = {
832 .shift = 24,
833 .width = 2,
834 .fixed_predivs = clk_out_predivs,
835 .n_predivs = ARRAY_SIZE(clk_out_predivs),
836 },
837 .common = {
838 .reg = 0x1f0,
839 .features = CCU_FEATURE_FIXED_PREDIV,
840 .hw.init = CLK_HW_INIT_PARENTS("out-a",
841 out_parents,
842 &ccu_mp_ops,
843 0),
844 },
845 };
846 static struct ccu_mp out_b_clk = {
847 .enable = BIT(31),
848 .m = _SUNXI_CCU_DIV(8, 5),
849 .p = _SUNXI_CCU_DIV(20, 2),
850 .mux = {
851 .shift = 24,
852 .width = 2,
853 .fixed_predivs = clk_out_predivs,
854 .n_predivs = ARRAY_SIZE(clk_out_predivs),
855 },
856 .common = {
857 .reg = 0x1f4,
858 .features = CCU_FEATURE_FIXED_PREDIV,
859 .hw.init = CLK_HW_INIT_PARENTS("out-b",
860 out_parents,
861 &ccu_mp_ops,
862 0),
863 },
864 };
865
866 static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
867 &hosc_clk.common,
868 &pll_core_clk.common,
869 &pll_audio_base_clk.common,
870 &pll_video0_clk.common,
871 &pll_ve_sun4i_clk.common,
872 &pll_ve_sun7i_clk.common,
873 &pll_ddr_base_clk.common,
874 &pll_ddr_clk.common,
875 &pll_ddr_other_clk.common,
876 &pll_periph_base_clk.common,
877 &pll_periph_sata_clk.common,
878 &pll_video1_clk.common,
879 &pll_gpu_clk.common,
880 &cpu_clk.common,
881 &axi_clk.common,
882 &axi_dram_clk.common,
883 &ahb_sun4i_clk.common,
884 &ahb_sun7i_clk.common,
885 &apb0_clk.common,
886 &apb1_clk.common,
887 &ahb_otg_clk.common,
888 &ahb_ehci0_clk.common,
889 &ahb_ohci0_clk.common,
890 &ahb_ehci1_clk.common,
891 &ahb_ohci1_clk.common,
892 &ahb_ss_clk.common,
893 &ahb_dma_clk.common,
894 &ahb_bist_clk.common,
895 &ahb_mmc0_clk.common,
896 &ahb_mmc1_clk.common,
897 &ahb_mmc2_clk.common,
898 &ahb_mmc3_clk.common,
899 &ahb_ms_clk.common,
900 &ahb_nand_clk.common,
901 &ahb_sdram_clk.common,
902 &ahb_ace_clk.common,
903 &ahb_emac_clk.common,
904 &ahb_ts_clk.common,
905 &ahb_spi0_clk.common,
906 &ahb_spi1_clk.common,
907 &ahb_spi2_clk.common,
908 &ahb_spi3_clk.common,
909 &ahb_pata_clk.common,
910 &ahb_sata_clk.common,
911 &ahb_gps_clk.common,
912 &ahb_hstimer_clk.common,
913 &ahb_ve_clk.common,
914 &ahb_tvd_clk.common,
915 &ahb_tve0_clk.common,
916 &ahb_tve1_clk.common,
917 &ahb_lcd0_clk.common,
918 &ahb_lcd1_clk.common,
919 &ahb_csi0_clk.common,
920 &ahb_csi1_clk.common,
921 &ahb_hdmi1_clk.common,
922 &ahb_hdmi0_clk.common,
923 &ahb_de_be0_clk.common,
924 &ahb_de_be1_clk.common,
925 &ahb_de_fe0_clk.common,
926 &ahb_de_fe1_clk.common,
927 &ahb_gmac_clk.common,
928 &ahb_mp_clk.common,
929 &ahb_gpu_clk.common,
930 &apb0_codec_clk.common,
931 &apb0_spdif_clk.common,
932 &apb0_ac97_clk.common,
933 &apb0_i2s0_clk.common,
934 &apb0_i2s1_clk.common,
935 &apb0_pio_clk.common,
936 &apb0_ir0_clk.common,
937 &apb0_ir1_clk.common,
938 &apb0_i2s2_clk.common,
939 &apb0_keypad_clk.common,
940 &apb1_i2c0_clk.common,
941 &apb1_i2c1_clk.common,
942 &apb1_i2c2_clk.common,
943 &apb1_i2c3_clk.common,
944 &apb1_can_clk.common,
945 &apb1_scr_clk.common,
946 &apb1_ps20_clk.common,
947 &apb1_ps21_clk.common,
948 &apb1_i2c4_clk.common,
949 &apb1_uart0_clk.common,
950 &apb1_uart1_clk.common,
951 &apb1_uart2_clk.common,
952 &apb1_uart3_clk.common,
953 &apb1_uart4_clk.common,
954 &apb1_uart5_clk.common,
955 &apb1_uart6_clk.common,
956 &apb1_uart7_clk.common,
957 &nand_clk.common,
958 &ms_clk.common,
959 &mmc0_clk.common,
960 &mmc0_output_clk.common,
961 &mmc0_sample_clk.common,
962 &mmc1_clk.common,
963 &mmc1_output_clk.common,
964 &mmc1_sample_clk.common,
965 &mmc2_clk.common,
966 &mmc2_output_clk.common,
967 &mmc2_sample_clk.common,
968 &mmc3_clk.common,
969 &mmc3_output_clk.common,
970 &mmc3_sample_clk.common,
971 &ts_clk.common,
972 &ss_clk.common,
973 &spi0_clk.common,
974 &spi1_clk.common,
975 &spi2_clk.common,
976 &pata_clk.common,
977 &ir0_sun4i_clk.common,
978 &ir1_sun4i_clk.common,
979 &ir0_sun7i_clk.common,
980 &ir1_sun7i_clk.common,
981 &i2s0_clk.common,
982 &ac97_clk.common,
983 &spdif_clk.common,
984 &keypad_clk.common,
985 &sata_clk.common,
986 &usb_ohci0_clk.common,
987 &usb_ohci1_clk.common,
988 &usb_phy_clk.common,
989 &spi3_clk.common,
990 &i2s1_clk.common,
991 &i2s2_clk.common,
992 &dram_ve_clk.common,
993 &dram_csi0_clk.common,
994 &dram_csi1_clk.common,
995 &dram_ts_clk.common,
996 &dram_tvd_clk.common,
997 &dram_tve0_clk.common,
998 &dram_tve1_clk.common,
999 &dram_out_clk.common,
1000 &dram_de_fe1_clk.common,
1001 &dram_de_fe0_clk.common,
1002 &dram_de_be0_clk.common,
1003 &dram_de_be1_clk.common,
1004 &dram_mp_clk.common,
1005 &dram_ace_clk.common,
1006 &de_be0_clk.common,
1007 &de_be1_clk.common,
1008 &de_fe0_clk.common,
1009 &de_fe1_clk.common,
1010 &de_mp_clk.common,
1011 &tcon0_ch0_clk.common,
1012 &tcon1_ch0_clk.common,
1013 &csi_sclk_clk.common,
1014 &tvd_sun4i_clk.common,
1015 &tvd_sclk1_sun7i_clk.common,
1016 &tvd_sclk2_sun7i_clk.common,
1017 &tcon0_ch1_sclk2_clk.common,
1018 &tcon0_ch1_clk.common,
1019 &tcon1_ch1_sclk2_clk.common,
1020 &tcon1_ch1_clk.common,
1021 &csi0_clk.common,
1022 &csi1_clk.common,
1023 &ve_clk.common,
1024 &codec_clk.common,
1025 &avs_clk.common,
1026 &ace_clk.common,
1027 &hdmi_clk.common,
1028 &gpu_sun4i_clk.common,
1029 &gpu_sun7i_clk.common,
1030 &mbus_sun4i_clk.common,
1031 &mbus_sun7i_clk.common,
1032 &hdmi1_slow_clk.common,
1033 &hdmi1_clk.common,
1034 &out_a_clk.common,
1035 &out_b_clk.common
1036 };
1037
1038 /* Post-divider for pll-audio is hardcoded to 1 */
1039 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
1040 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1041 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
1042 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
1043 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
1044 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1045 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
1046 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
1047 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
1048 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
1049 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
1050 "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
1051
1052
1053 static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
1054 .hws = {
1055 [CLK_HOSC] = &hosc_clk.common.hw,
1056 [CLK_PLL_CORE] = &pll_core_clk.common.hw,
1057 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
1058 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
1059 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
1060 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
1061 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
1062 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
1063 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1064 [CLK_PLL_VE] = &pll_ve_sun4i_clk.common.hw,
1065 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
1066 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
1067 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
1068 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
1069 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
1070 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
1071 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
1072 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1073 [CLK_CPU] = &cpu_clk.common.hw,
1074 [CLK_AXI] = &axi_clk.common.hw,
1075 [CLK_AXI_DRAM] = &axi_dram_clk.common.hw,
1076 [CLK_AHB] = &ahb_sun4i_clk.common.hw,
1077 [CLK_APB0] = &apb0_clk.common.hw,
1078 [CLK_APB1] = &apb1_clk.common.hw,
1079 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
1080 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
1081 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
1082 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
1083 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
1084 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
1085 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
1086 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
1087 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
1088 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
1089 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
1090 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
1091 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
1092 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
1093 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
1094 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
1095 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
1096 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
1097 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
1098 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
1099 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
1100 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
1101 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
1102 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
1103 [CLK_AHB_GPS] = &ahb_gps_clk.common.hw,
1104 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
1105 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
1106 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
1107 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
1108 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
1109 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
1110 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
1111 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
1112 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
1113 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
1114 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
1115 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
1116 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
1117 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
1118 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
1119 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
1120 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
1121 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
1122 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
1123 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
1124 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
1125 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
1126 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
1127 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
1128 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
1129 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
1130 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
1131 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
1132 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
1133 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
1134 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
1135 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
1136 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
1137 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
1138 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
1139 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
1140 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
1141 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
1142 [CLK_NAND] = &nand_clk.common.hw,
1143 [CLK_MS] = &ms_clk.common.hw,
1144 [CLK_MMC0] = &mmc0_clk.common.hw,
1145 [CLK_MMC1] = &mmc1_clk.common.hw,
1146 [CLK_MMC2] = &mmc2_clk.common.hw,
1147 [CLK_MMC3] = &mmc3_clk.common.hw,
1148 [CLK_TS] = &ts_clk.common.hw,
1149 [CLK_SS] = &ss_clk.common.hw,
1150 [CLK_SPI0] = &spi0_clk.common.hw,
1151 [CLK_SPI1] = &spi1_clk.common.hw,
1152 [CLK_SPI2] = &spi2_clk.common.hw,
1153 [CLK_PATA] = &pata_clk.common.hw,
1154 [CLK_IR0] = &ir0_sun4i_clk.common.hw,
1155 [CLK_IR1] = &ir1_sun4i_clk.common.hw,
1156 [CLK_I2S0] = &i2s0_clk.common.hw,
1157 [CLK_AC97] = &ac97_clk.common.hw,
1158 [CLK_SPDIF] = &spdif_clk.common.hw,
1159 [CLK_KEYPAD] = &keypad_clk.common.hw,
1160 [CLK_SATA] = &sata_clk.common.hw,
1161 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1162 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1163 [CLK_USB_PHY] = &usb_phy_clk.common.hw,
1164 /* CLK_GPS is unimplemented */
1165 [CLK_SPI3] = &spi3_clk.common.hw,
1166 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1167 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1168 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1169 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1170 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1171 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
1172 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
1173 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
1174 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
1175 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
1176 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
1177 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
1178 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1179 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
1180 [CLK_DE_BE0] = &de_be0_clk.common.hw,
1181 [CLK_DE_BE1] = &de_be1_clk.common.hw,
1182 [CLK_DE_FE0] = &de_fe0_clk.common.hw,
1183 [CLK_DE_FE1] = &de_fe1_clk.common.hw,
1184 [CLK_DE_MP] = &de_mp_clk.common.hw,
1185 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
1186 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
1187 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1188 [CLK_TVD] = &tvd_sun4i_clk.common.hw,
1189 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
1190 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
1191 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
1192 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
1193 [CLK_CSI0] = &csi0_clk.common.hw,
1194 [CLK_CSI1] = &csi1_clk.common.hw,
1195 [CLK_VE] = &ve_clk.common.hw,
1196 [CLK_CODEC] = &codec_clk.common.hw,
1197 [CLK_AVS] = &avs_clk.common.hw,
1198 [CLK_ACE] = &ace_clk.common.hw,
1199 [CLK_HDMI] = &hdmi_clk.common.hw,
1200 [CLK_GPU] = &gpu_sun7i_clk.common.hw,
1201 [CLK_MBUS] = &mbus_sun4i_clk.common.hw,
1202 },
1203 .num = CLK_NUMBER_SUN4I,
1204 };
1205 static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
1206 .hws = {
1207 [CLK_HOSC] = &hosc_clk.common.hw,
1208 [CLK_PLL_CORE] = &pll_core_clk.common.hw,
1209 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
1210 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
1211 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
1212 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
1213 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
1214 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
1215 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1216 [CLK_PLL_VE] = &pll_ve_sun7i_clk.common.hw,
1217 [CLK_PLL_DDR_BASE] = &pll_ddr_base_clk.common.hw,
1218 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
1219 [CLK_PLL_DDR_OTHER] = &pll_ddr_other_clk.common.hw,
1220 [CLK_PLL_PERIPH_BASE] = &pll_periph_base_clk.common.hw,
1221 [CLK_PLL_PERIPH] = &pll_periph_clk.hw,
1222 [CLK_PLL_PERIPH_SATA] = &pll_periph_sata_clk.common.hw,
1223 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
1224 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1225 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
1226 [CLK_CPU] = &cpu_clk.common.hw,
1227 [CLK_AXI] = &axi_clk.common.hw,
1228 [CLK_AHB] = &ahb_sun7i_clk.common.hw,
1229 [CLK_APB0] = &apb0_clk.common.hw,
1230 [CLK_APB1] = &apb1_clk.common.hw,
1231 [CLK_AHB_OTG] = &ahb_otg_clk.common.hw,
1232 [CLK_AHB_EHCI0] = &ahb_ehci0_clk.common.hw,
1233 [CLK_AHB_OHCI0] = &ahb_ohci0_clk.common.hw,
1234 [CLK_AHB_EHCI1] = &ahb_ehci1_clk.common.hw,
1235 [CLK_AHB_OHCI1] = &ahb_ohci1_clk.common.hw,
1236 [CLK_AHB_SS] = &ahb_ss_clk.common.hw,
1237 [CLK_AHB_DMA] = &ahb_dma_clk.common.hw,
1238 [CLK_AHB_BIST] = &ahb_bist_clk.common.hw,
1239 [CLK_AHB_MMC0] = &ahb_mmc0_clk.common.hw,
1240 [CLK_AHB_MMC1] = &ahb_mmc1_clk.common.hw,
1241 [CLK_AHB_MMC2] = &ahb_mmc2_clk.common.hw,
1242 [CLK_AHB_MMC3] = &ahb_mmc3_clk.common.hw,
1243 [CLK_AHB_MS] = &ahb_ms_clk.common.hw,
1244 [CLK_AHB_NAND] = &ahb_nand_clk.common.hw,
1245 [CLK_AHB_SDRAM] = &ahb_sdram_clk.common.hw,
1246 [CLK_AHB_ACE] = &ahb_ace_clk.common.hw,
1247 [CLK_AHB_EMAC] = &ahb_emac_clk.common.hw,
1248 [CLK_AHB_TS] = &ahb_ts_clk.common.hw,
1249 [CLK_AHB_SPI0] = &ahb_spi0_clk.common.hw,
1250 [CLK_AHB_SPI1] = &ahb_spi1_clk.common.hw,
1251 [CLK_AHB_SPI2] = &ahb_spi2_clk.common.hw,
1252 [CLK_AHB_SPI3] = &ahb_spi3_clk.common.hw,
1253 [CLK_AHB_PATA] = &ahb_pata_clk.common.hw,
1254 [CLK_AHB_SATA] = &ahb_sata_clk.common.hw,
1255 [CLK_AHB_HSTIMER] = &ahb_hstimer_clk.common.hw,
1256 [CLK_AHB_VE] = &ahb_ve_clk.common.hw,
1257 [CLK_AHB_TVD] = &ahb_tvd_clk.common.hw,
1258 [CLK_AHB_TVE0] = &ahb_tve0_clk.common.hw,
1259 [CLK_AHB_TVE1] = &ahb_tve1_clk.common.hw,
1260 [CLK_AHB_LCD0] = &ahb_lcd0_clk.common.hw,
1261 [CLK_AHB_LCD1] = &ahb_lcd1_clk.common.hw,
1262 [CLK_AHB_CSI0] = &ahb_csi0_clk.common.hw,
1263 [CLK_AHB_CSI1] = &ahb_csi1_clk.common.hw,
1264 [CLK_AHB_HDMI1] = &ahb_hdmi1_clk.common.hw,
1265 [CLK_AHB_HDMI0] = &ahb_hdmi0_clk.common.hw,
1266 [CLK_AHB_DE_BE0] = &ahb_de_be0_clk.common.hw,
1267 [CLK_AHB_DE_BE1] = &ahb_de_be1_clk.common.hw,
1268 [CLK_AHB_DE_FE0] = &ahb_de_fe0_clk.common.hw,
1269 [CLK_AHB_DE_FE1] = &ahb_de_fe1_clk.common.hw,
1270 [CLK_AHB_GMAC] = &ahb_gmac_clk.common.hw,
1271 [CLK_AHB_MP] = &ahb_mp_clk.common.hw,
1272 [CLK_AHB_GPU] = &ahb_gpu_clk.common.hw,
1273 [CLK_APB0_CODEC] = &apb0_codec_clk.common.hw,
1274 [CLK_APB0_SPDIF] = &apb0_spdif_clk.common.hw,
1275 [CLK_APB0_AC97] = &apb0_ac97_clk.common.hw,
1276 [CLK_APB0_I2S0] = &apb0_i2s0_clk.common.hw,
1277 [CLK_APB0_I2S1] = &apb0_i2s1_clk.common.hw,
1278 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
1279 [CLK_APB0_IR0] = &apb0_ir0_clk.common.hw,
1280 [CLK_APB0_IR1] = &apb0_ir1_clk.common.hw,
1281 [CLK_APB0_I2S2] = &apb0_i2s2_clk.common.hw,
1282 [CLK_APB0_KEYPAD] = &apb0_keypad_clk.common.hw,
1283 [CLK_APB1_I2C0] = &apb1_i2c0_clk.common.hw,
1284 [CLK_APB1_I2C1] = &apb1_i2c1_clk.common.hw,
1285 [CLK_APB1_I2C2] = &apb1_i2c2_clk.common.hw,
1286 [CLK_APB1_I2C3] = &apb1_i2c3_clk.common.hw,
1287 [CLK_APB1_CAN] = &apb1_can_clk.common.hw,
1288 [CLK_APB1_SCR] = &apb1_scr_clk.common.hw,
1289 [CLK_APB1_PS20] = &apb1_ps20_clk.common.hw,
1290 [CLK_APB1_PS21] = &apb1_ps21_clk.common.hw,
1291 [CLK_APB1_I2C4] = &apb1_i2c4_clk.common.hw,
1292 [CLK_APB1_UART0] = &apb1_uart0_clk.common.hw,
1293 [CLK_APB1_UART1] = &apb1_uart1_clk.common.hw,
1294 [CLK_APB1_UART2] = &apb1_uart2_clk.common.hw,
1295 [CLK_APB1_UART3] = &apb1_uart3_clk.common.hw,
1296 [CLK_APB1_UART4] = &apb1_uart4_clk.common.hw,
1297 [CLK_APB1_UART5] = &apb1_uart5_clk.common.hw,
1298 [CLK_APB1_UART6] = &apb1_uart6_clk.common.hw,
1299 [CLK_APB1_UART7] = &apb1_uart7_clk.common.hw,
1300 [CLK_NAND] = &nand_clk.common.hw,
1301 [CLK_MS] = &ms_clk.common.hw,
1302 [CLK_MMC0] = &mmc0_clk.common.hw,
1303 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
1304 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
1305 [CLK_MMC1] = &mmc1_clk.common.hw,
1306 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
1307 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
1308 [CLK_MMC2] = &mmc2_clk.common.hw,
1309 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
1310 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
1311 [CLK_MMC3] = &mmc3_clk.common.hw,
1312 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
1313 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
1314 [CLK_TS] = &ts_clk.common.hw,
1315 [CLK_SS] = &ss_clk.common.hw,
1316 [CLK_SPI0] = &spi0_clk.common.hw,
1317 [CLK_SPI1] = &spi1_clk.common.hw,
1318 [CLK_SPI2] = &spi2_clk.common.hw,
1319 [CLK_PATA] = &pata_clk.common.hw,
1320 [CLK_IR0] = &ir0_sun7i_clk.common.hw,
1321 [CLK_IR1] = &ir1_sun7i_clk.common.hw,
1322 [CLK_I2S0] = &i2s0_clk.common.hw,
1323 [CLK_AC97] = &ac97_clk.common.hw,
1324 [CLK_SPDIF] = &spdif_clk.common.hw,
1325 [CLK_KEYPAD] = &keypad_clk.common.hw,
1326 [CLK_SATA] = &sata_clk.common.hw,
1327 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1328 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1329 [CLK_USB_PHY] = &usb_phy_clk.common.hw,
1330 /* CLK_GPS is unimplemented */
1331 [CLK_SPI3] = &spi3_clk.common.hw,
1332 [CLK_I2S1] = &i2s1_clk.common.hw,
1333 [CLK_I2S2] = &i2s2_clk.common.hw,
1334 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1335 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1336 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1337 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1338 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1339 [CLK_DRAM_TVE0] = &dram_tve0_clk.common.hw,
1340 [CLK_DRAM_TVE1] = &dram_tve1_clk.common.hw,
1341 [CLK_DRAM_OUT] = &dram_out_clk.common.hw,
1342 [CLK_DRAM_DE_FE1] = &dram_de_fe1_clk.common.hw,
1343 [CLK_DRAM_DE_FE0] = &dram_de_fe0_clk.common.hw,
1344 [CLK_DRAM_DE_BE0] = &dram_de_be0_clk.common.hw,
1345 [CLK_DRAM_DE_BE1] = &dram_de_be1_clk.common.hw,
1346 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1347 [CLK_DRAM_ACE] = &dram_ace_clk.common.hw,
1348 [CLK_DE_BE0] = &de_be0_clk.common.hw,
1349 [CLK_DE_BE1] = &de_be1_clk.common.hw,
1350 [CLK_DE_FE0] = &de_fe0_clk.common.hw,
1351 [CLK_DE_FE1] = &de_fe1_clk.common.hw,
1352 [CLK_DE_MP] = &de_mp_clk.common.hw,
1353 [CLK_TCON0_CH0] = &tcon0_ch0_clk.common.hw,
1354 [CLK_TCON1_CH0] = &tcon1_ch0_clk.common.hw,
1355 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1356 [CLK_TVD_SCLK2] = &tvd_sclk2_sun7i_clk.common.hw,
1357 [CLK_TVD] = &tvd_sclk1_sun7i_clk.common.hw,
1358 [CLK_TCON0_CH1_SCLK2] = &tcon0_ch1_sclk2_clk.common.hw,
1359 [CLK_TCON0_CH1] = &tcon0_ch1_clk.common.hw,
1360 [CLK_TCON1_CH1_SCLK2] = &tcon1_ch1_sclk2_clk.common.hw,
1361 [CLK_TCON1_CH1] = &tcon1_ch1_clk.common.hw,
1362 [CLK_CSI0] = &csi0_clk.common.hw,
1363 [CLK_CSI1] = &csi1_clk.common.hw,
1364 [CLK_VE] = &ve_clk.common.hw,
1365 [CLK_CODEC] = &codec_clk.common.hw,
1366 [CLK_AVS] = &avs_clk.common.hw,
1367 [CLK_ACE] = &ace_clk.common.hw,
1368 [CLK_HDMI] = &hdmi_clk.common.hw,
1369 [CLK_GPU] = &gpu_sun7i_clk.common.hw,
1370 [CLK_MBUS] = &mbus_sun7i_clk.common.hw,
1371 [CLK_HDMI1_SLOW] = &hdmi1_slow_clk.common.hw,
1372 [CLK_HDMI1] = &hdmi1_clk.common.hw,
1373 [CLK_OUT_A] = &out_a_clk.common.hw,
1374 [CLK_OUT_B] = &out_b_clk.common.hw,
1375 },
1376 .num = CLK_NUMBER_SUN7I,
1377 };
1378
1379 static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
1380 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1381 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1382 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1383 [RST_GPS] = { 0x0d0, BIT(0) },
1384 [RST_DE_BE0] = { 0x104, BIT(30) },
1385 [RST_DE_BE1] = { 0x108, BIT(30) },
1386 [RST_DE_FE0] = { 0x10c, BIT(30) },
1387 [RST_DE_FE1] = { 0x110, BIT(30) },
1388 [RST_DE_MP] = { 0x114, BIT(30) },
1389 [RST_TVE0] = { 0x118, BIT(29) },
1390 [RST_TCON0] = { 0x118, BIT(30) },
1391 [RST_TVE1] = { 0x11c, BIT(29) },
1392 [RST_TCON1] = { 0x11c, BIT(30) },
1393 [RST_CSI0] = { 0x134, BIT(30) },
1394 [RST_CSI1] = { 0x138, BIT(30) },
1395 [RST_VE] = { 0x13c, BIT(0) },
1396 [RST_ACE] = { 0x148, BIT(16) },
1397 [RST_LVDS] = { 0x14c, BIT(0) },
1398 [RST_GPU] = { 0x154, BIT(30) },
1399 [RST_HDMI_H] = { 0x170, BIT(0) },
1400 [RST_HDMI_SYS] = { 0x170, BIT(1) },
1401 [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },
1402 };
1403
1404 static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
1405 .ccu_clks = sun4i_sun7i_ccu_clks,
1406 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1407
1408 .hw_clks = &sun4i_a10_hw_clks,
1409
1410 .resets = sunxi_a10_a20_ccu_resets,
1411 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1412 };
1413
1414 static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
1415 .ccu_clks = sun4i_sun7i_ccu_clks,
1416 .num_ccu_clks = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1417
1418 .hw_clks = &sun7i_a20_hw_clks,
1419
1420 .resets = sunxi_a10_a20_ccu_resets,
1421 .num_resets = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1422 };
1423
1424 static void __init sun4i_ccu_init(struct device_node *node,
1425 const struct sunxi_ccu_desc *desc)
1426 {
1427 void __iomem *reg;
1428 u32 val;
1429
1430 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1431 if (IS_ERR(reg)) {
1432 pr_err("%s: Could not map the clock registers\n",
1433 of_node_full_name(node));
1434 return;
1435 }
1436
1437 val = readl(reg + SUN4I_PLL_AUDIO_REG);
1438
1439 /*
1440 * Force VCO and PLL bias current to lowest setting. Higher
1441 * settings interfere with sigma-delta modulation and result
1442 * in audible noise and distortions when using SPDIF or I2S.
1443 */
1444 val &= ~GENMASK(25, 16);
1445
1446 /* Force the PLL-Audio-1x divider to 1 */
1447 val &= ~GENMASK(29, 26);
1448 writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
1449
1450 /*
1451 * Use the peripheral PLL6 as the AHB parent, instead of CPU /
1452 * AXI which have rate changes due to cpufreq.
1453 *
1454 * This is especially a big deal for the HS timer whose parent
1455 * clock is AHB.
1456 *
1457 * NB! These bits are undocumented in A10 manual.
1458 */
1459 val = readl(reg + SUN4I_AHB_REG);
1460 val &= ~GENMASK(7, 6);
1461 writel(val | (2 << 6), reg + SUN4I_AHB_REG);
1462
1463 sunxi_ccu_probe(node, reg, desc);
1464 }
1465
1466 static void __init sun4i_a10_ccu_setup(struct device_node *node)
1467 {
1468 sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
1469 }
1470 CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1471 sun4i_a10_ccu_setup);
1472
1473 static void __init sun7i_a20_ccu_setup(struct device_node *node)
1474 {
1475 sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
1476 }
1477 CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
1478 sun7i_a20_ccu_setup);
Linux with added FPC-III support