drivers/clocksource/qcom-timer.c

   1 /*
   2  *
   3  * Copyright (C) 2007 Google, Inc.
   4  * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clocksource.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/cpu.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/sched_clock.h>
  28
  29 #include <asm/delay.h>
  30
  31 #define TIMER_MATCH_VAL                 0x0000
  32 #define TIMER_COUNT_VAL                 0x0004
  33 #define TIMER_ENABLE                    0x0008
  34 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
  35 #define TIMER_ENABLE_EN                 BIT(0)
  36 #define TIMER_CLEAR                     0x000C
  37 #define DGT_CLK_CTL                     0x10
  38 #define DGT_CLK_CTL_DIV_4               0x3
  39 #define TIMER_STS_GPT0_CLR_PEND         BIT(10)
  40
  41 #define GPT_HZ 32768
  42
  43 static void __iomem *event_base;
  44 static void __iomem *sts_base;
  45
  46 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  47 {
  48         struct clock_event_device *evt = dev_id;
  49         /* Stop the timer tick */
  50         if (clockevent_state_oneshot(evt)) {
  51                 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  52                 ctrl &= ~TIMER_ENABLE_EN;
  53                 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  54         }
  55         evt->event_handler(evt);
  56         return IRQ_HANDLED;
  57 }
  58
  59 static int msm_timer_set_next_event(unsigned long cycles,
  60                                     struct clock_event_device *evt)
  61 {
  62         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  63
  64         ctrl &= ~TIMER_ENABLE_EN;
  65         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  66
  67         writel_relaxed(ctrl, event_base + TIMER_CLEAR);
  68         writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
  69
  70         if (sts_base)
  71                 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
  72                         cpu_relax();
  73
  74         writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
  75         return 0;
  76 }
  77
  78 static int msm_timer_shutdown(struct clock_event_device *evt)
  79 {
  80         u32 ctrl;
  81
  82         ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  83         ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
  84         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  85         return 0;
  86 }
  87
  88 static struct clock_event_device __percpu *msm_evt;
  89
  90 static void __iomem *source_base;
  91
  92 static notrace u64 msm_read_timer_count(struct clocksource *cs)
  93 {
  94         return readl_relaxed(source_base + TIMER_COUNT_VAL);
  95 }
  96
  97 static struct clocksource msm_clocksource = {
  98         .name   = "dg_timer",
  99         .rating = 300,
 100         .read   = msm_read_timer_count,
 101         .mask   = CLOCKSOURCE_MASK(32),
 102         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 103 };
 104
 105 static int msm_timer_irq;
 106 static int msm_timer_has_ppi;
 107
 108 static int msm_local_timer_starting_cpu(unsigned int cpu)
 109 {
 110         struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
 111         int err;
 112
 113         evt->irq = msm_timer_irq;
 114         evt->name = "msm_timer";
 115         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 116         evt->rating = 200;
 117         evt->set_state_shutdown = msm_timer_shutdown;
 118         evt->set_state_oneshot = msm_timer_shutdown;
 119         evt->tick_resume = msm_timer_shutdown;
 120         evt->set_next_event = msm_timer_set_next_event;
 121         evt->cpumask = cpumask_of(cpu);
 122
 123         clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
 124
 125         if (msm_timer_has_ppi) {
 126                 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
 127         } else {
 128                 err = request_irq(evt->irq, msm_timer_interrupt,
 129                                 IRQF_TIMER | IRQF_NOBALANCING |
 130                                 IRQF_TRIGGER_RISING, "gp_timer", evt);
 131                 if (err)
 132                         pr_err("request_irq failed\n");
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int msm_local_timer_dying_cpu(unsigned int cpu)
 139 {
 140         struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
 141
 142         evt->set_state_shutdown(evt);
 143         disable_percpu_irq(evt->irq);
 144         return 0;
 145 }
 146
 147 static u64 notrace msm_sched_clock_read(void)
 148 {
 149         return msm_clocksource.read(&msm_clocksource);
 150 }
 151
 152 static unsigned long msm_read_current_timer(void)
 153 {
 154         return msm_clocksource.read(&msm_clocksource);
 155 }
 156
 157 static struct delay_timer msm_delay_timer = {
 158         .read_current_timer = msm_read_current_timer,
 159 };
 160
 161 static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
 162                                   bool percpu)
 163 {
 164         struct clocksource *cs = &msm_clocksource;
 165         int res = 0;
 166
 167         msm_timer_irq = irq;
 168         msm_timer_has_ppi = percpu;
 169
 170         msm_evt = alloc_percpu(struct clock_event_device);
 171         if (!msm_evt) {
 172                 pr_err("memory allocation failed for clockevents\n");
 173                 goto err;
 174         }
 175
 176         if (percpu)
 177                 res = request_percpu_irq(irq, msm_timer_interrupt,
 178                                          "gp_timer", msm_evt);
 179
 180         if (res) {
 181                 pr_err("request_percpu_irq failed\n");
 182         } else {
 183                 /* Install and invoke hotplug callbacks */
 184                 res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
 185                                         "clockevents/qcom/timer:starting",
 186                                         msm_local_timer_starting_cpu,
 187                                         msm_local_timer_dying_cpu);
 188                 if (res) {
 189                         free_percpu_irq(irq, msm_evt);
 190                         goto err;
 191                 }
 192         }
 193
 194 err:
 195         writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
 196         res = clocksource_register_hz(cs, dgt_hz);
 197         if (res)
 198                 pr_err("clocksource_register failed\n");
 199         sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
 200         msm_delay_timer.freq = dgt_hz;
 201         register_current_timer_delay(&msm_delay_timer);
 202
 203         return res;
 204 }
 205
 206 static int __init msm_dt_timer_init(struct device_node *np)
 207 {
 208         u32 freq;
 209         int irq, ret;
 210         struct resource res;
 211         u32 percpu_offset;
 212         void __iomem *base;
 213         void __iomem *cpu0_base;
 214
 215         base = of_iomap(np, 0);
 216         if (!base) {
 217                 pr_err("Failed to map event base\n");
 218                 return -ENXIO;
 219         }
 220
 221         /* We use GPT0 for the clockevent */
 222         irq = irq_of_parse_and_map(np, 1);
 223         if (irq <= 0) {
 224                 pr_err("Can't get irq\n");
 225                 return -EINVAL;
 226         }
 227
 228         /* We use CPU0's DGT for the clocksource */
 229         if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
 230                 percpu_offset = 0;
 231
 232         ret = of_address_to_resource(np, 0, &res);
 233         if (ret) {
 234                 pr_err("Failed to parse DGT resource\n");
 235                 return ret;
 236         }
 237
 238         cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
 239         if (!cpu0_base) {
 240                 pr_err("Failed to map source base\n");
 241                 return -EINVAL;
 242         }
 243
 244         if (of_property_read_u32(np, "clock-frequency", &freq)) {
 245                 pr_err("Unknown frequency\n");
 246                 return -EINVAL;
 247         }
 248
 249         event_base = base + 0x4;
 250         sts_base = base + 0x88;
 251         source_base = cpu0_base + 0x24;
 252         freq /= 4;
 253         writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
 254
 255         return msm_timer_init(freq, 32, irq, !!percpu_offset);
 256 }
 257 TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
 258 TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);