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Linux 4.19.133
[linux/fpc-iii.git] / drivers / cpufreq / intel_pstate.c
blobe7b3d4ed8eff44a367be371237e4de1c456c306f
1 /*
2 * intel_pstate.c: Native P state management for Intel processors
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/fs.h>
29 #include <linux/acpi.h>
30 #include <linux/vmalloc.h>
31 #include <trace/events/power.h>
32
33 #include <asm/div64.h>
34 #include <asm/msr.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/cpufeature.h>
37 #include <asm/intel-family.h>
38
39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
40
41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
43
44 #ifdef CONFIG_ACPI
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
47 #endif
48
49 #define FRAC_BITS 8
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
52
53 #define EXT_BITS 6
54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
57
58 static inline int32_t mul_fp(int32_t x, int32_t y)
59 {
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61 }
62
63 static inline int32_t div_fp(s64 x, s64 y)
64 {
65 return div64_s64((int64_t)x << FRAC_BITS, y);
66 }
67
68 static inline int ceiling_fp(int32_t x)
69 {
70 int mask, ret;
71
72 ret = fp_toint(x);
73 mask = (1 << FRAC_BITS) - 1;
74 if (x & mask)
75 ret += 1;
76 return ret;
77 }
78
79 static inline int32_t percent_fp(int percent)
80 {
81 return div_fp(percent, 100);
82 }
83
84 static inline u64 mul_ext_fp(u64 x, u64 y)
85 {
86 return (x * y) >> EXT_FRAC_BITS;
87 }
88
89 static inline u64 div_ext_fp(u64 x, u64 y)
90 {
91 return div64_u64(x << EXT_FRAC_BITS, y);
92 }
93
94 static inline int32_t percent_ext_fp(int percent)
95 {
96 return div_ext_fp(percent, 100);
97 }
98
99 /**
100 * struct sample - Store performance sample
101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
104 * P state. This can be different than core_avg_perf
105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
111 * current sample
112 * @time: Current time from scheduler
113 *
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
116 */
117 struct sample {
118 int32_t core_avg_perf;
119 int32_t busy_scaled;
120 u64 aperf;
121 u64 mperf;
122 u64 tsc;
123 u64 time;
124 };
125
126 /**
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
135 * frequency units
136 * @turbo_pstate: Max Turbo P state possible for this platform
137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
139 *
140 * Stores the per cpu model P state limits and current P state.
141 */
142 struct pstate_data {
143 int current_pstate;
144 int min_pstate;
145 int max_pstate;
146 int max_pstate_physical;
147 int scaling;
148 int turbo_pstate;
149 unsigned int max_freq;
150 unsigned int turbo_freq;
151 };
152
153 /**
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
156 * the lowest P state
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
161 *
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
165 */
166 struct vid_data {
167 int min;
168 int max;
169 int turbo;
170 int32_t ratio;
171 };
172
173 /**
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
181 * P-state capacity.
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
183 * P-state capacity.
184 */
185 struct global_params {
186 bool no_turbo;
187 bool turbo_disabled;
188 int max_perf_pct;
189 int min_perf_pct;
190 };
191
192 /**
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
195 * @policy: CPUFreq policy value
196 * @update_util: CPUFreq utility callback information
197 * @update_util_set: CPUFreq utility callback is set
198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
202 * @last_sample_time: Last Sample time
203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
210 * current sample
211 * @sample: Storage for storing last Sample data
212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance
221 * preference/bias
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
223 * operation
224 * @hwp_req_cached: Cached value of the last HWP Request MSR
225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
226 * @last_io_update: Last time when IO wake flag was set
227 * @sched_flags: Store scheduler flags for possible cross CPU update
228 * @hwp_boost_min: Last HWP boosted min performance
229 *
230 * This structure stores per CPU instance data for all CPUs.
231 */
232 struct cpudata {
233 int cpu;
234
235 unsigned int policy;
236 struct update_util_data update_util;
237 bool update_util_set;
238
239 struct pstate_data pstate;
240 struct vid_data vid;
241
242 u64 last_update;
243 u64 last_sample_time;
244 u64 aperf_mperf_shift;
245 u64 prev_aperf;
246 u64 prev_mperf;
247 u64 prev_tsc;
248 u64 prev_cummulative_iowait;
249 struct sample sample;
250 int32_t min_perf_ratio;
251 int32_t max_perf_ratio;
252 #ifdef CONFIG_ACPI
253 struct acpi_processor_performance acpi_perf_data;
254 bool valid_pss_table;
255 #endif
256 unsigned int iowait_boost;
257 s16 epp_powersave;
258 s16 epp_policy;
259 s16 epp_default;
260 s16 epp_saved;
261 u64 hwp_req_cached;
262 u64 hwp_cap_cached;
263 u64 last_io_update;
264 unsigned int sched_flags;
265 u32 hwp_boost_min;
266 };
267
268 static struct cpudata **all_cpu_data;
269
270 /**
271 * struct pstate_funcs - Per CPU model specific callbacks
272 * @get_max: Callback to get maximum non turbo effective P state
273 * @get_max_physical: Callback to get maximum non turbo physical P state
274 * @get_min: Callback to get minimum P state
275 * @get_turbo: Callback to get turbo P state
276 * @get_scaling: Callback to get frequency scaling factor
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
279 *
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
282 */
283 struct pstate_funcs {
284 int (*get_max)(void);
285 int (*get_max_physical)(void);
286 int (*get_min)(void);
287 int (*get_turbo)(void);
288 int (*get_scaling)(void);
289 int (*get_aperf_mperf_shift)(void);
290 u64 (*get_val)(struct cpudata*, int pstate);
291 void (*get_vid)(struct cpudata *);
292 };
293
294 static struct pstate_funcs pstate_funcs __read_mostly;
295
296 static int hwp_active __read_mostly;
297 static int hwp_mode_bdw __read_mostly;
298 static bool per_cpu_limits __read_mostly;
299 static bool hwp_boost __read_mostly;
300
301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
302
303 #ifdef CONFIG_ACPI
304 static bool acpi_ppc;
305 #endif
306
307 static struct global_params global;
308
309 static DEFINE_MUTEX(intel_pstate_driver_lock);
310 static DEFINE_MUTEX(intel_pstate_limits_lock);
311
312 #ifdef CONFIG_ACPI
313
314 static bool intel_pstate_acpi_pm_profile_server(void)
315 {
316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
318 return true;
319
320 return false;
321 }
322
323 static bool intel_pstate_get_ppc_enable_status(void)
324 {
325 if (intel_pstate_acpi_pm_profile_server())
326 return true;
327
328 return acpi_ppc;
329 }
330
331 #ifdef CONFIG_ACPI_CPPC_LIB
332
333 /* The work item is needed to avoid CPU hotplug locking issues */
334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
335 {
336 sched_set_itmt_support();
337 }
338
339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
340
341 static void intel_pstate_set_itmt_prio(int cpu)
342 {
343 struct cppc_perf_caps cppc_perf;
344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
345 int ret;
346
347 ret = cppc_get_perf_caps(cpu, &cppc_perf);
348 if (ret)
349 return;
350
351 /*
352 * The priorities can be set regardless of whether or not
353 * sched_set_itmt_support(true) has been called and it is valid to
354 * update them at any time after it has been called.
355 */
356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
357
358 if (max_highest_perf <= min_highest_perf) {
359 if (cppc_perf.highest_perf > max_highest_perf)
360 max_highest_perf = cppc_perf.highest_perf;
361
362 if (cppc_perf.highest_perf < min_highest_perf)
363 min_highest_perf = cppc_perf.highest_perf;
364
365 if (max_highest_perf > min_highest_perf) {
366 /*
367 * This code can be run during CPU online under the
368 * CPU hotplug locks, so sched_set_itmt_support()
369 * cannot be called from here. Queue up a work item
370 * to invoke it.
371 */
372 schedule_work(&sched_itmt_work);
373 }
374 }
375 }
376 #else
377 static void intel_pstate_set_itmt_prio(int cpu)
378 {
379 }
380 #endif
381
382 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
383 {
384 struct cpudata *cpu;
385 int ret;
386 int i;
387
388 if (hwp_active) {
389 intel_pstate_set_itmt_prio(policy->cpu);
390 return;
391 }
392
393 if (!intel_pstate_get_ppc_enable_status())
394 return;
395
396 cpu = all_cpu_data[policy->cpu];
397
398 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
399 policy->cpu);
400 if (ret)
401 return;
402
403 /*
404 * Check if the control value in _PSS is for PERF_CTL MSR, which should
405 * guarantee that the states returned by it map to the states in our
406 * list directly.
407 */
408 if (cpu->acpi_perf_data.control_register.space_id !=
409 ACPI_ADR_SPACE_FIXED_HARDWARE)
410 goto err;
411
412 /*
413 * If there is only one entry _PSS, simply ignore _PSS and continue as
414 * usual without taking _PSS into account
415 */
416 if (cpu->acpi_perf_data.state_count < 2)
417 goto err;
418
419 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
420 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
421 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
422 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
423 (u32) cpu->acpi_perf_data.states[i].core_frequency,
424 (u32) cpu->acpi_perf_data.states[i].power,
425 (u32) cpu->acpi_perf_data.states[i].control);
426 }
427
428 /*
429 * The _PSS table doesn't contain whole turbo frequency range.
430 * This just contains +1 MHZ above the max non turbo frequency,
431 * with control value corresponding to max turbo ratio. But
432 * when cpufreq set policy is called, it will call with this
433 * max frequency, which will cause a reduced performance as
434 * this driver uses real max turbo frequency as the max
435 * frequency. So correct this frequency in _PSS table to
436 * correct max turbo frequency based on the turbo state.
437 * Also need to convert to MHz as _PSS freq is in MHz.
438 */
439 if (!global.turbo_disabled)
440 cpu->acpi_perf_data.states[0].core_frequency =
441 policy->cpuinfo.max_freq / 1000;
442 cpu->valid_pss_table = true;
443 pr_debug("_PPC limits will be enforced\n");
444
445 return;
446
447 err:
448 cpu->valid_pss_table = false;
449 acpi_processor_unregister_performance(policy->cpu);
450 }
451
452 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
453 {
454 struct cpudata *cpu;
455
456 cpu = all_cpu_data[policy->cpu];
457 if (!cpu->valid_pss_table)
458 return;
459
460 acpi_processor_unregister_performance(policy->cpu);
461 }
462 #else
463 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
464 {
465 }
466
467 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
468 {
469 }
470
471 static inline bool intel_pstate_acpi_pm_profile_server(void)
472 {
473 return false;
474 }
475 #endif
476
477 static inline void update_turbo_state(void)
478 {
479 u64 misc_en;
480 struct cpudata *cpu;
481
482 cpu = all_cpu_data[0];
483 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
484 global.turbo_disabled =
485 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
486 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
487 }
488
489 static int min_perf_pct_min(void)
490 {
491 struct cpudata *cpu = all_cpu_data[0];
492 int turbo_pstate = cpu->pstate.turbo_pstate;
493
494 return turbo_pstate ?
495 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
496 }
497
498 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
499 {
500 u64 epb;
501 int ret;
502
503 if (!static_cpu_has(X86_FEATURE_EPB))
504 return -ENXIO;
505
506 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
507 if (ret)
508 return (s16)ret;
509
510 return (s16)(epb & 0x0f);
511 }
512
513 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
514 {
515 s16 epp;
516
517 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
518 /*
519 * When hwp_req_data is 0, means that caller didn't read
520 * MSR_HWP_REQUEST, so need to read and get EPP.
521 */
522 if (!hwp_req_data) {
523 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
524 &hwp_req_data);
525 if (epp)
526 return epp;
527 }
528 epp = (hwp_req_data >> 24) & 0xff;
529 } else {
530 /* When there is no EPP present, HWP uses EPB settings */
531 epp = intel_pstate_get_epb(cpu_data);
532 }
533
534 return epp;
535 }
536
537 static int intel_pstate_set_epb(int cpu, s16 pref)
538 {
539 u64 epb;
540 int ret;
541
542 if (!static_cpu_has(X86_FEATURE_EPB))
543 return -ENXIO;
544
545 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
546 if (ret)
547 return ret;
548
549 epb = (epb & ~0x0f) | pref;
550 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
551
552 return 0;
553 }
554
555 /*
556 * EPP/EPB display strings corresponding to EPP index in the
557 * energy_perf_strings[]
558 * index String
559 *-------------------------------------
560 * 0 default
561 * 1 performance
562 * 2 balance_performance
563 * 3 balance_power
564 * 4 power
565 */
566 static const char * const energy_perf_strings[] = {
567 "default",
568 "performance",
569 "balance_performance",
570 "balance_power",
571 "power",
572 NULL
573 };
574 static const unsigned int epp_values[] = {
575 HWP_EPP_PERFORMANCE,
576 HWP_EPP_BALANCE_PERFORMANCE,
577 HWP_EPP_BALANCE_POWERSAVE,
578 HWP_EPP_POWERSAVE
579 };
580
581 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
582 {
583 s16 epp;
584 int index = -EINVAL;
585
586 epp = intel_pstate_get_epp(cpu_data, 0);
587 if (epp < 0)
588 return epp;
589
590 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
591 if (epp == HWP_EPP_PERFORMANCE)
592 return 1;
593 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
594 return 2;
595 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
596 return 3;
597 else
598 return 4;
599 } else if (static_cpu_has(X86_FEATURE_EPB)) {
600 /*
601 * Range:
602 * 0x00-0x03 : Performance
603 * 0x04-0x07 : Balance performance
604 * 0x08-0x0B : Balance power
605 * 0x0C-0x0F : Power
606 * The EPB is a 4 bit value, but our ranges restrict the
607 * value which can be set. Here only using top two bits
608 * effectively.
609 */
610 index = (epp >> 2) + 1;
611 }
612
613 return index;
614 }
615
616 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
617 int pref_index)
618 {
619 int epp = -EINVAL;
620 int ret;
621
622 if (!pref_index)
623 epp = cpu_data->epp_default;
624
625 mutex_lock(&intel_pstate_limits_lock);
626
627 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
628 u64 value;
629
630 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
631 if (ret)
632 goto return_pref;
633
634 value &= ~GENMASK_ULL(31, 24);
635
636 if (epp == -EINVAL)
637 epp = epp_values[pref_index - 1];
638
639 value |= (u64)epp << 24;
640 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
641 } else {
642 if (epp == -EINVAL)
643 epp = (pref_index - 1) << 2;
644 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
645 }
646 return_pref:
647 mutex_unlock(&intel_pstate_limits_lock);
648
649 return ret;
650 }
651
652 static ssize_t show_energy_performance_available_preferences(
653 struct cpufreq_policy *policy, char *buf)
654 {
655 int i = 0;
656 int ret = 0;
657
658 while (energy_perf_strings[i] != NULL)
659 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
660
661 ret += sprintf(&buf[ret], "\n");
662
663 return ret;
664 }
665
666 cpufreq_freq_attr_ro(energy_performance_available_preferences);
667
668 static ssize_t store_energy_performance_preference(
669 struct cpufreq_policy *policy, const char *buf, size_t count)
670 {
671 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
672 char str_preference[21];
673 int ret;
674
675 ret = sscanf(buf, "%20s", str_preference);
676 if (ret != 1)
677 return -EINVAL;
678
679 ret = match_string(energy_perf_strings, -1, str_preference);
680 if (ret < 0)
681 return ret;
682
683 intel_pstate_set_energy_pref_index(cpu_data, ret);
684 return count;
685 }
686
687 static ssize_t show_energy_performance_preference(
688 struct cpufreq_policy *policy, char *buf)
689 {
690 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
691 int preference;
692
693 preference = intel_pstate_get_energy_pref_index(cpu_data);
694 if (preference < 0)
695 return preference;
696
697 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
698 }
699
700 cpufreq_freq_attr_rw(energy_performance_preference);
701
702 static struct freq_attr *hwp_cpufreq_attrs[] = {
703 &energy_performance_preference,
704 &energy_performance_available_preferences,
705 NULL,
706 };
707
708 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
709 int *current_max)
710 {
711 u64 cap;
712
713 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
714 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
715 if (global.no_turbo)
716 *current_max = HWP_GUARANTEED_PERF(cap);
717 else
718 *current_max = HWP_HIGHEST_PERF(cap);
719
720 *phy_max = HWP_HIGHEST_PERF(cap);
721 }
722
723 static void intel_pstate_hwp_set(unsigned int cpu)
724 {
725 struct cpudata *cpu_data = all_cpu_data[cpu];
726 int max, min;
727 u64 value;
728 s16 epp;
729
730 max = cpu_data->max_perf_ratio;
731 min = cpu_data->min_perf_ratio;
732
733 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
734 min = max;
735
736 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
737
738 value &= ~HWP_MIN_PERF(~0L);
739 value |= HWP_MIN_PERF(min);
740
741 value &= ~HWP_MAX_PERF(~0L);
742 value |= HWP_MAX_PERF(max);
743
744 if (cpu_data->epp_policy == cpu_data->policy)
745 goto skip_epp;
746
747 cpu_data->epp_policy = cpu_data->policy;
748
749 if (cpu_data->epp_saved >= 0) {
750 epp = cpu_data->epp_saved;
751 cpu_data->epp_saved = -EINVAL;
752 goto update_epp;
753 }
754
755 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
756 epp = intel_pstate_get_epp(cpu_data, value);
757 cpu_data->epp_powersave = epp;
758 /* If EPP read was failed, then don't try to write */
759 if (epp < 0)
760 goto skip_epp;
761
762 epp = 0;
763 } else {
764 /* skip setting EPP, when saved value is invalid */
765 if (cpu_data->epp_powersave < 0)
766 goto skip_epp;
767
768 /*
769 * No need to restore EPP when it is not zero. This
770 * means:
771 * - Policy is not changed
772 * - user has manually changed
773 * - Error reading EPB
774 */
775 epp = intel_pstate_get_epp(cpu_data, value);
776 if (epp)
777 goto skip_epp;
778
779 epp = cpu_data->epp_powersave;
780 }
781 update_epp:
782 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
783 value &= ~GENMASK_ULL(31, 24);
784 value |= (u64)epp << 24;
785 } else {
786 intel_pstate_set_epb(cpu, epp);
787 }
788 skip_epp:
789 WRITE_ONCE(cpu_data->hwp_req_cached, value);
790 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
791 }
792
793 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
794 {
795 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
796
797 if (!hwp_active)
798 return 0;
799
800 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
801
802 return 0;
803 }
804
805 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
806
807 static int intel_pstate_resume(struct cpufreq_policy *policy)
808 {
809 if (!hwp_active)
810 return 0;
811
812 mutex_lock(&intel_pstate_limits_lock);
813
814 if (policy->cpu == 0)
815 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
816
817 all_cpu_data[policy->cpu]->epp_policy = 0;
818 intel_pstate_hwp_set(policy->cpu);
819
820 mutex_unlock(&intel_pstate_limits_lock);
821
822 return 0;
823 }
824
825 static void intel_pstate_update_policies(void)
826 {
827 int cpu;
828
829 for_each_possible_cpu(cpu)
830 cpufreq_update_policy(cpu);
831 }
832
833 /************************** sysfs begin ************************/
834 #define show_one(file_name, object) \
835 static ssize_t show_##file_name \
836 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
837 { \
838 return sprintf(buf, "%u\n", global.object); \
839 }
840
841 static ssize_t intel_pstate_show_status(char *buf);
842 static int intel_pstate_update_status(const char *buf, size_t size);
843
844 static ssize_t show_status(struct kobject *kobj,
845 struct kobj_attribute *attr, char *buf)
846 {
847 ssize_t ret;
848
849 mutex_lock(&intel_pstate_driver_lock);
850 ret = intel_pstate_show_status(buf);
851 mutex_unlock(&intel_pstate_driver_lock);
852
853 return ret;
854 }
855
856 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
857 const char *buf, size_t count)
858 {
859 char *p = memchr(buf, '\n', count);
860 int ret;
861
862 mutex_lock(&intel_pstate_driver_lock);
863 ret = intel_pstate_update_status(buf, p ? p - buf : count);
864 mutex_unlock(&intel_pstate_driver_lock);
865
866 return ret < 0 ? ret : count;
867 }
868
869 static ssize_t show_turbo_pct(struct kobject *kobj,
870 struct kobj_attribute *attr, char *buf)
871 {
872 struct cpudata *cpu;
873 int total, no_turbo, turbo_pct;
874 uint32_t turbo_fp;
875
876 mutex_lock(&intel_pstate_driver_lock);
877
878 if (!intel_pstate_driver) {
879 mutex_unlock(&intel_pstate_driver_lock);
880 return -EAGAIN;
881 }
882
883 cpu = all_cpu_data[0];
884
885 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
886 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
887 turbo_fp = div_fp(no_turbo, total);
888 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
889
890 mutex_unlock(&intel_pstate_driver_lock);
891
892 return sprintf(buf, "%u\n", turbo_pct);
893 }
894
895 static ssize_t show_num_pstates(struct kobject *kobj,
896 struct kobj_attribute *attr, char *buf)
897 {
898 struct cpudata *cpu;
899 int total;
900
901 mutex_lock(&intel_pstate_driver_lock);
902
903 if (!intel_pstate_driver) {
904 mutex_unlock(&intel_pstate_driver_lock);
905 return -EAGAIN;
906 }
907
908 cpu = all_cpu_data[0];
909 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
910
911 mutex_unlock(&intel_pstate_driver_lock);
912
913 return sprintf(buf, "%u\n", total);
914 }
915
916 static ssize_t show_no_turbo(struct kobject *kobj,
917 struct kobj_attribute *attr, char *buf)
918 {
919 ssize_t ret;
920
921 mutex_lock(&intel_pstate_driver_lock);
922
923 if (!intel_pstate_driver) {
924 mutex_unlock(&intel_pstate_driver_lock);
925 return -EAGAIN;
926 }
927
928 update_turbo_state();
929 if (global.turbo_disabled)
930 ret = sprintf(buf, "%u\n", global.turbo_disabled);
931 else
932 ret = sprintf(buf, "%u\n", global.no_turbo);
933
934 mutex_unlock(&intel_pstate_driver_lock);
935
936 return ret;
937 }
938
939 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
940 const char *buf, size_t count)
941 {
942 unsigned int input;
943 int ret;
944
945 ret = sscanf(buf, "%u", &input);
946 if (ret != 1)
947 return -EINVAL;
948
949 mutex_lock(&intel_pstate_driver_lock);
950
951 if (!intel_pstate_driver) {
952 mutex_unlock(&intel_pstate_driver_lock);
953 return -EAGAIN;
954 }
955
956 mutex_lock(&intel_pstate_limits_lock);
957
958 update_turbo_state();
959 if (global.turbo_disabled) {
960 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
961 mutex_unlock(&intel_pstate_limits_lock);
962 mutex_unlock(&intel_pstate_driver_lock);
963 return -EPERM;
964 }
965
966 global.no_turbo = clamp_t(int, input, 0, 1);
967
968 if (global.no_turbo) {
969 struct cpudata *cpu = all_cpu_data[0];
970 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
971
972 /* Squash the global minimum into the permitted range. */
973 if (global.min_perf_pct > pct)
974 global.min_perf_pct = pct;
975 }
976
977 mutex_unlock(&intel_pstate_limits_lock);
978
979 intel_pstate_update_policies();
980
981 mutex_unlock(&intel_pstate_driver_lock);
982
983 return count;
984 }
985
986 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
987 const char *buf, size_t count)
988 {
989 unsigned int input;
990 int ret;
991
992 ret = sscanf(buf, "%u", &input);
993 if (ret != 1)
994 return -EINVAL;
995
996 mutex_lock(&intel_pstate_driver_lock);
997
998 if (!intel_pstate_driver) {
999 mutex_unlock(&intel_pstate_driver_lock);
1000 return -EAGAIN;
1001 }
1002
1003 mutex_lock(&intel_pstate_limits_lock);
1004
1005 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1006
1007 mutex_unlock(&intel_pstate_limits_lock);
1008
1009 intel_pstate_update_policies();
1010
1011 mutex_unlock(&intel_pstate_driver_lock);
1012
1013 return count;
1014 }
1015
1016 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1017 const char *buf, size_t count)
1018 {
1019 unsigned int input;
1020 int ret;
1021
1022 ret = sscanf(buf, "%u", &input);
1023 if (ret != 1)
1024 return -EINVAL;
1025
1026 mutex_lock(&intel_pstate_driver_lock);
1027
1028 if (!intel_pstate_driver) {
1029 mutex_unlock(&intel_pstate_driver_lock);
1030 return -EAGAIN;
1031 }
1032
1033 mutex_lock(&intel_pstate_limits_lock);
1034
1035 global.min_perf_pct = clamp_t(int, input,
1036 min_perf_pct_min(), global.max_perf_pct);
1037
1038 mutex_unlock(&intel_pstate_limits_lock);
1039
1040 intel_pstate_update_policies();
1041
1042 mutex_unlock(&intel_pstate_driver_lock);
1043
1044 return count;
1045 }
1046
1047 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1048 struct kobj_attribute *attr, char *buf)
1049 {
1050 return sprintf(buf, "%u\n", hwp_boost);
1051 }
1052
1053 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1054 struct kobj_attribute *b,
1055 const char *buf, size_t count)
1056 {
1057 unsigned int input;
1058 int ret;
1059
1060 ret = kstrtouint(buf, 10, &input);
1061 if (ret)
1062 return ret;
1063
1064 mutex_lock(&intel_pstate_driver_lock);
1065 hwp_boost = !!input;
1066 intel_pstate_update_policies();
1067 mutex_unlock(&intel_pstate_driver_lock);
1068
1069 return count;
1070 }
1071
1072 show_one(max_perf_pct, max_perf_pct);
1073 show_one(min_perf_pct, min_perf_pct);
1074
1075 define_one_global_rw(status);
1076 define_one_global_rw(no_turbo);
1077 define_one_global_rw(max_perf_pct);
1078 define_one_global_rw(min_perf_pct);
1079 define_one_global_ro(turbo_pct);
1080 define_one_global_ro(num_pstates);
1081 define_one_global_rw(hwp_dynamic_boost);
1082
1083 static struct attribute *intel_pstate_attributes[] = {
1084 &status.attr,
1085 &no_turbo.attr,
1086 &turbo_pct.attr,
1087 &num_pstates.attr,
1088 NULL
1089 };
1090
1091 static const struct attribute_group intel_pstate_attr_group = {
1092 .attrs = intel_pstate_attributes,
1093 };
1094
1095 static void __init intel_pstate_sysfs_expose_params(void)
1096 {
1097 struct kobject *intel_pstate_kobject;
1098 int rc;
1099
1100 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1101 &cpu_subsys.dev_root->kobj);
1102 if (WARN_ON(!intel_pstate_kobject))
1103 return;
1104
1105 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1106 if (WARN_ON(rc))
1107 return;
1108
1109 /*
1110 * If per cpu limits are enforced there are no global limits, so
1111 * return without creating max/min_perf_pct attributes
1112 */
1113 if (per_cpu_limits)
1114 return;
1115
1116 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1117 WARN_ON(rc);
1118
1119 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1120 WARN_ON(rc);
1121
1122 if (hwp_active) {
1123 rc = sysfs_create_file(intel_pstate_kobject,
1124 &hwp_dynamic_boost.attr);
1125 WARN_ON(rc);
1126 }
1127 }
1128 /************************** sysfs end ************************/
1129
1130 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1131 {
1132 /* First disable HWP notification interrupt as we don't process them */
1133 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1134 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1135
1136 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1137 cpudata->epp_policy = 0;
1138 if (cpudata->epp_default == -EINVAL)
1139 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1140 }
1141
1142 #define MSR_IA32_POWER_CTL_BIT_EE 19
1143
1144 /* Disable energy efficiency optimization */
1145 static void intel_pstate_disable_ee(int cpu)
1146 {
1147 u64 power_ctl;
1148 int ret;
1149
1150 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1151 if (ret)
1152 return;
1153
1154 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1155 pr_info("Disabling energy efficiency optimization\n");
1156 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1157 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1158 }
1159 }
1160
1161 static int atom_get_min_pstate(void)
1162 {
1163 u64 value;
1164
1165 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1166 return (value >> 8) & 0x7F;
1167 }
1168
1169 static int atom_get_max_pstate(void)
1170 {
1171 u64 value;
1172
1173 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1174 return (value >> 16) & 0x7F;
1175 }
1176
1177 static int atom_get_turbo_pstate(void)
1178 {
1179 u64 value;
1180
1181 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1182 return value & 0x7F;
1183 }
1184
1185 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1186 {
1187 u64 val;
1188 int32_t vid_fp;
1189 u32 vid;
1190
1191 val = (u64)pstate << 8;
1192 if (global.no_turbo && !global.turbo_disabled)
1193 val |= (u64)1 << 32;
1194
1195 vid_fp = cpudata->vid.min + mul_fp(
1196 int_tofp(pstate - cpudata->pstate.min_pstate),
1197 cpudata->vid.ratio);
1198
1199 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1200 vid = ceiling_fp(vid_fp);
1201
1202 if (pstate > cpudata->pstate.max_pstate)
1203 vid = cpudata->vid.turbo;
1204
1205 return val | vid;
1206 }
1207
1208 static int silvermont_get_scaling(void)
1209 {
1210 u64 value;
1211 int i;
1212 /* Defined in Table 35-6 from SDM (Sept 2015) */
1213 static int silvermont_freq_table[] = {
1214 83300, 100000, 133300, 116700, 80000};
1215
1216 rdmsrl(MSR_FSB_FREQ, value);
1217 i = value & 0x7;
1218 WARN_ON(i > 4);
1219
1220 return silvermont_freq_table[i];
1221 }
1222
1223 static int airmont_get_scaling(void)
1224 {
1225 u64 value;
1226 int i;
1227 /* Defined in Table 35-10 from SDM (Sept 2015) */
1228 static int airmont_freq_table[] = {
1229 83300, 100000, 133300, 116700, 80000,
1230 93300, 90000, 88900, 87500};
1231
1232 rdmsrl(MSR_FSB_FREQ, value);
1233 i = value & 0xF;
1234 WARN_ON(i > 8);
1235
1236 return airmont_freq_table[i];
1237 }
1238
1239 static void atom_get_vid(struct cpudata *cpudata)
1240 {
1241 u64 value;
1242
1243 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1244 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1245 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1246 cpudata->vid.ratio = div_fp(
1247 cpudata->vid.max - cpudata->vid.min,
1248 int_tofp(cpudata->pstate.max_pstate -
1249 cpudata->pstate.min_pstate));
1250
1251 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1252 cpudata->vid.turbo = value & 0x7f;
1253 }
1254
1255 static int core_get_min_pstate(void)
1256 {
1257 u64 value;
1258
1259 rdmsrl(MSR_PLATFORM_INFO, value);
1260 return (value >> 40) & 0xFF;
1261 }
1262
1263 static int core_get_max_pstate_physical(void)
1264 {
1265 u64 value;
1266
1267 rdmsrl(MSR_PLATFORM_INFO, value);
1268 return (value >> 8) & 0xFF;
1269 }
1270
1271 static int core_get_tdp_ratio(u64 plat_info)
1272 {
1273 /* Check how many TDP levels present */
1274 if (plat_info & 0x600000000) {
1275 u64 tdp_ctrl;
1276 u64 tdp_ratio;
1277 int tdp_msr;
1278 int err;
1279
1280 /* Get the TDP level (0, 1, 2) to get ratios */
1281 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1282 if (err)
1283 return err;
1284
1285 /* TDP MSR are continuous starting at 0x648 */
1286 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1287 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1288 if (err)
1289 return err;
1290
1291 /* For level 1 and 2, bits[23:16] contain the ratio */
1292 if (tdp_ctrl & 0x03)
1293 tdp_ratio >>= 16;
1294
1295 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1296 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1297
1298 return (int)tdp_ratio;
1299 }
1300
1301 return -ENXIO;
1302 }
1303
1304 static int core_get_max_pstate(void)
1305 {
1306 u64 tar;
1307 u64 plat_info;
1308 int max_pstate;
1309 int tdp_ratio;
1310 int err;
1311
1312 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1313 max_pstate = (plat_info >> 8) & 0xFF;
1314
1315 tdp_ratio = core_get_tdp_ratio(plat_info);
1316 if (tdp_ratio <= 0)
1317 return max_pstate;
1318
1319 if (hwp_active) {
1320 /* Turbo activation ratio is not used on HWP platforms */
1321 return tdp_ratio;
1322 }
1323
1324 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1325 if (!err) {
1326 int tar_levels;
1327
1328 /* Do some sanity checking for safety */
1329 tar_levels = tar & 0xff;
1330 if (tdp_ratio - 1 == tar_levels) {
1331 max_pstate = tar_levels;
1332 pr_debug("max_pstate=TAC %x\n", max_pstate);
1333 }
1334 }
1335
1336 return max_pstate;
1337 }
1338
1339 static int core_get_turbo_pstate(void)
1340 {
1341 u64 value;
1342 int nont, ret;
1343
1344 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1345 nont = core_get_max_pstate();
1346 ret = (value) & 255;
1347 if (ret <= nont)
1348 ret = nont;
1349 return ret;
1350 }
1351
1352 static inline int core_get_scaling(void)
1353 {
1354 return 100000;
1355 }
1356
1357 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1358 {
1359 u64 val;
1360
1361 val = (u64)pstate << 8;
1362 if (global.no_turbo && !global.turbo_disabled)
1363 val |= (u64)1 << 32;
1364
1365 return val;
1366 }
1367
1368 static int knl_get_aperf_mperf_shift(void)
1369 {
1370 return 10;
1371 }
1372
1373 static int knl_get_turbo_pstate(void)
1374 {
1375 u64 value;
1376 int nont, ret;
1377
1378 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1379 nont = core_get_max_pstate();
1380 ret = (((value) >> 8) & 0xFF);
1381 if (ret <= nont)
1382 ret = nont;
1383 return ret;
1384 }
1385
1386 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1387 {
1388 return global.no_turbo || global.turbo_disabled ?
1389 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1390 }
1391
1392 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1393 {
1394 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1395 cpu->pstate.current_pstate = pstate;
1396 /*
1397 * Generally, there is no guarantee that this code will always run on
1398 * the CPU being updated, so force the register update to run on the
1399 * right CPU.
1400 */
1401 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1402 pstate_funcs.get_val(cpu, pstate));
1403 }
1404
1405 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1406 {
1407 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1408 }
1409
1410 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1411 {
1412 int pstate;
1413
1414 update_turbo_state();
1415 pstate = intel_pstate_get_base_pstate(cpu);
1416 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1417 intel_pstate_set_pstate(cpu, pstate);
1418 }
1419
1420 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1421 {
1422 cpu->pstate.min_pstate = pstate_funcs.get_min();
1423 cpu->pstate.max_pstate = pstate_funcs.get_max();
1424 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1425 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1426 cpu->pstate.scaling = pstate_funcs.get_scaling();
1427 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1428
1429 if (hwp_active && !hwp_mode_bdw) {
1430 unsigned int phy_max, current_max;
1431
1432 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1433 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1434 } else {
1435 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1436 }
1437
1438 if (pstate_funcs.get_aperf_mperf_shift)
1439 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1440
1441 if (pstate_funcs.get_vid)
1442 pstate_funcs.get_vid(cpu);
1443
1444 intel_pstate_set_min_pstate(cpu);
1445 }
1446
1447 /*
1448 * Long hold time will keep high perf limits for long time,
1449 * which negatively impacts perf/watt for some workloads,
1450 * like specpower. 3ms is based on experiements on some
1451 * workoads.
1452 */
1453 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1454
1455 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1456 {
1457 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1458 u32 max_limit = (hwp_req & 0xff00) >> 8;
1459 u32 min_limit = (hwp_req & 0xff);
1460 u32 boost_level1;
1461
1462 /*
1463 * Cases to consider (User changes via sysfs or boot time):
1464 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1465 * No boost, return.
1466 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1467 * Should result in one level boost only for P0.
1468 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1469 * Should result in two level boost:
1470 * (min + p1)/2 and P1.
1471 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1472 * Should result in three level boost:
1473 * (min + p1)/2, P1 and P0.
1474 */
1475
1476 /* If max and min are equal or already at max, nothing to boost */
1477 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1478 return;
1479
1480 if (!cpu->hwp_boost_min)
1481 cpu->hwp_boost_min = min_limit;
1482
1483 /* level at half way mark between min and guranteed */
1484 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1485
1486 if (cpu->hwp_boost_min < boost_level1)
1487 cpu->hwp_boost_min = boost_level1;
1488 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1489 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1490 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1491 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1492 cpu->hwp_boost_min = max_limit;
1493 else
1494 return;
1495
1496 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1497 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1498 cpu->last_update = cpu->sample.time;
1499 }
1500
1501 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1502 {
1503 if (cpu->hwp_boost_min) {
1504 bool expired;
1505
1506 /* Check if we are idle for hold time to boost down */
1507 expired = time_after64(cpu->sample.time, cpu->last_update +
1508 hwp_boost_hold_time_ns);
1509 if (expired) {
1510 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1511 cpu->hwp_boost_min = 0;
1512 }
1513 }
1514 cpu->last_update = cpu->sample.time;
1515 }
1516
1517 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1518 u64 time)
1519 {
1520 cpu->sample.time = time;
1521
1522 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1523 bool do_io = false;
1524
1525 cpu->sched_flags = 0;
1526 /*
1527 * Set iowait_boost flag and update time. Since IO WAIT flag
1528 * is set all the time, we can't just conclude that there is
1529 * some IO bound activity is scheduled on this CPU with just
1530 * one occurrence. If we receive at least two in two
1531 * consecutive ticks, then we treat as boost candidate.
1532 */
1533 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1534 do_io = true;
1535
1536 cpu->last_io_update = time;
1537
1538 if (do_io)
1539 intel_pstate_hwp_boost_up(cpu);
1540
1541 } else {
1542 intel_pstate_hwp_boost_down(cpu);
1543 }
1544 }
1545
1546 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1547 u64 time, unsigned int flags)
1548 {
1549 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1550
1551 cpu->sched_flags |= flags;
1552
1553 if (smp_processor_id() == cpu->cpu)
1554 intel_pstate_update_util_hwp_local(cpu, time);
1555 }
1556
1557 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1558 {
1559 struct sample *sample = &cpu->sample;
1560
1561 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1562 }
1563
1564 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1565 {
1566 u64 aperf, mperf;
1567 unsigned long flags;
1568 u64 tsc;
1569
1570 local_irq_save(flags);
1571 rdmsrl(MSR_IA32_APERF, aperf);
1572 rdmsrl(MSR_IA32_MPERF, mperf);
1573 tsc = rdtsc();
1574 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1575 local_irq_restore(flags);
1576 return false;
1577 }
1578 local_irq_restore(flags);
1579
1580 cpu->last_sample_time = cpu->sample.time;
1581 cpu->sample.time = time;
1582 cpu->sample.aperf = aperf;
1583 cpu->sample.mperf = mperf;
1584 cpu->sample.tsc = tsc;
1585 cpu->sample.aperf -= cpu->prev_aperf;
1586 cpu->sample.mperf -= cpu->prev_mperf;
1587 cpu->sample.tsc -= cpu->prev_tsc;
1588
1589 cpu->prev_aperf = aperf;
1590 cpu->prev_mperf = mperf;
1591 cpu->prev_tsc = tsc;
1592 /*
1593 * First time this function is invoked in a given cycle, all of the
1594 * previous sample data fields are equal to zero or stale and they must
1595 * be populated with meaningful numbers for things to work, so assume
1596 * that sample.time will always be reset before setting the utilization
1597 * update hook and make the caller skip the sample then.
1598 */
1599 if (cpu->last_sample_time) {
1600 intel_pstate_calc_avg_perf(cpu);
1601 return true;
1602 }
1603 return false;
1604 }
1605
1606 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1607 {
1608 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1609 }
1610
1611 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1612 {
1613 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1614 cpu->sample.core_avg_perf);
1615 }
1616
1617 static inline int32_t get_target_pstate(struct cpudata *cpu)
1618 {
1619 struct sample *sample = &cpu->sample;
1620 int32_t busy_frac, boost;
1621 int target, avg_pstate;
1622
1623 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1624 sample->tsc);
1625
1626 boost = cpu->iowait_boost;
1627 cpu->iowait_boost >>= 1;
1628
1629 if (busy_frac < boost)
1630 busy_frac = boost;
1631
1632 sample->busy_scaled = busy_frac * 100;
1633
1634 target = global.no_turbo || global.turbo_disabled ?
1635 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1636 target += target >> 2;
1637 target = mul_fp(target, busy_frac);
1638 if (target < cpu->pstate.min_pstate)
1639 target = cpu->pstate.min_pstate;
1640
1641 /*
1642 * If the average P-state during the previous cycle was higher than the
1643 * current target, add 50% of the difference to the target to reduce
1644 * possible performance oscillations and offset possible performance
1645 * loss related to moving the workload from one CPU to another within
1646 * a package/module.
1647 */
1648 avg_pstate = get_avg_pstate(cpu);
1649 if (avg_pstate > target)
1650 target += (avg_pstate - target) >> 1;
1651
1652 return target;
1653 }
1654
1655 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1656 {
1657 int max_pstate = intel_pstate_get_base_pstate(cpu);
1658 int min_pstate;
1659
1660 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1661 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1662 return clamp_t(int, pstate, min_pstate, max_pstate);
1663 }
1664
1665 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1666 {
1667 if (pstate == cpu->pstate.current_pstate)
1668 return;
1669
1670 cpu->pstate.current_pstate = pstate;
1671 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1672 }
1673
1674 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1675 {
1676 int from = cpu->pstate.current_pstate;
1677 struct sample *sample;
1678 int target_pstate;
1679
1680 update_turbo_state();
1681
1682 target_pstate = get_target_pstate(cpu);
1683 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1684 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1685 intel_pstate_update_pstate(cpu, target_pstate);
1686
1687 sample = &cpu->sample;
1688 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1689 fp_toint(sample->busy_scaled),
1690 from,
1691 cpu->pstate.current_pstate,
1692 sample->mperf,
1693 sample->aperf,
1694 sample->tsc,
1695 get_avg_frequency(cpu),
1696 fp_toint(cpu->iowait_boost * 100));
1697 }
1698
1699 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1700 unsigned int flags)
1701 {
1702 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1703 u64 delta_ns;
1704
1705 /* Don't allow remote callbacks */
1706 if (smp_processor_id() != cpu->cpu)
1707 return;
1708
1709 if (flags & SCHED_CPUFREQ_IOWAIT) {
1710 cpu->iowait_boost = int_tofp(1);
1711 cpu->last_update = time;
1712 /*
1713 * The last time the busy was 100% so P-state was max anyway
1714 * so avoid overhead of computation.
1715 */
1716 if (fp_toint(cpu->sample.busy_scaled) == 100)
1717 return;
1718
1719 goto set_pstate;
1720 } else if (cpu->iowait_boost) {
1721 /* Clear iowait_boost if the CPU may have been idle. */
1722 delta_ns = time - cpu->last_update;
1723 if (delta_ns > TICK_NSEC)
1724 cpu->iowait_boost = 0;
1725 }
1726 cpu->last_update = time;
1727 delta_ns = time - cpu->sample.time;
1728 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1729 return;
1730
1731 set_pstate:
1732 if (intel_pstate_sample(cpu, time))
1733 intel_pstate_adjust_pstate(cpu);
1734 }
1735
1736 static struct pstate_funcs core_funcs = {
1737 .get_max = core_get_max_pstate,
1738 .get_max_physical = core_get_max_pstate_physical,
1739 .get_min = core_get_min_pstate,
1740 .get_turbo = core_get_turbo_pstate,
1741 .get_scaling = core_get_scaling,
1742 .get_val = core_get_val,
1743 };
1744
1745 static const struct pstate_funcs silvermont_funcs = {
1746 .get_max = atom_get_max_pstate,
1747 .get_max_physical = atom_get_max_pstate,
1748 .get_min = atom_get_min_pstate,
1749 .get_turbo = atom_get_turbo_pstate,
1750 .get_val = atom_get_val,
1751 .get_scaling = silvermont_get_scaling,
1752 .get_vid = atom_get_vid,
1753 };
1754
1755 static const struct pstate_funcs airmont_funcs = {
1756 .get_max = atom_get_max_pstate,
1757 .get_max_physical = atom_get_max_pstate,
1758 .get_min = atom_get_min_pstate,
1759 .get_turbo = atom_get_turbo_pstate,
1760 .get_val = atom_get_val,
1761 .get_scaling = airmont_get_scaling,
1762 .get_vid = atom_get_vid,
1763 };
1764
1765 static const struct pstate_funcs knl_funcs = {
1766 .get_max = core_get_max_pstate,
1767 .get_max_physical = core_get_max_pstate_physical,
1768 .get_min = core_get_min_pstate,
1769 .get_turbo = knl_get_turbo_pstate,
1770 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1771 .get_scaling = core_get_scaling,
1772 .get_val = core_get_val,
1773 };
1774
1775 #define ICPU(model, policy) \
1776 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1777 (unsigned long)&policy }
1778
1779 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1780 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1781 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1782 ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs),
1783 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1784 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1785 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1786 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1787 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1788 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1789 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1790 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1791 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1792 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1793 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1794 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1795 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1796 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1797 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1798 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1799 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, core_funcs),
1800 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1801 {}
1802 };
1803 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1804
1805 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1806 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1807 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1808 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1809 {}
1810 };
1811
1812 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1813 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1814 {}
1815 };
1816
1817 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1818 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1819 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1820 {}
1821 };
1822
1823 static int intel_pstate_init_cpu(unsigned int cpunum)
1824 {
1825 struct cpudata *cpu;
1826
1827 cpu = all_cpu_data[cpunum];
1828
1829 if (!cpu) {
1830 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1831 if (!cpu)
1832 return -ENOMEM;
1833
1834 all_cpu_data[cpunum] = cpu;
1835
1836 cpu->epp_default = -EINVAL;
1837 cpu->epp_powersave = -EINVAL;
1838 cpu->epp_saved = -EINVAL;
1839 }
1840
1841 cpu = all_cpu_data[cpunum];
1842
1843 cpu->cpu = cpunum;
1844
1845 if (hwp_active) {
1846 const struct x86_cpu_id *id;
1847
1848 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1849 if (id)
1850 intel_pstate_disable_ee(cpunum);
1851
1852 intel_pstate_hwp_enable(cpu);
1853
1854 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1855 if (id && intel_pstate_acpi_pm_profile_server())
1856 hwp_boost = true;
1857 }
1858
1859 intel_pstate_get_cpu_pstates(cpu);
1860
1861 pr_debug("controlling: cpu %d\n", cpunum);
1862
1863 return 0;
1864 }
1865
1866 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1867 {
1868 struct cpudata *cpu = all_cpu_data[cpu_num];
1869
1870 if (hwp_active && !hwp_boost)
1871 return;
1872
1873 if (cpu->update_util_set)
1874 return;
1875
1876 /* Prevent intel_pstate_update_util() from using stale data. */
1877 cpu->sample.time = 0;
1878 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1879 (hwp_active ?
1880 intel_pstate_update_util_hwp :
1881 intel_pstate_update_util));
1882 cpu->update_util_set = true;
1883 }
1884
1885 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1886 {
1887 struct cpudata *cpu_data = all_cpu_data[cpu];
1888
1889 if (!cpu_data->update_util_set)
1890 return;
1891
1892 cpufreq_remove_update_util_hook(cpu);
1893 cpu_data->update_util_set = false;
1894 synchronize_sched();
1895 }
1896
1897 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1898 {
1899 return global.turbo_disabled || global.no_turbo ?
1900 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1901 }
1902
1903 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1904 struct cpudata *cpu)
1905 {
1906 int max_freq = intel_pstate_get_max_freq(cpu);
1907 int32_t max_policy_perf, min_policy_perf;
1908 int max_state, turbo_max;
1909
1910 /*
1911 * HWP needs some special consideration, because on BDX the
1912 * HWP_REQUEST uses abstract value to represent performance
1913 * rather than pure ratios.
1914 */
1915 if (hwp_active) {
1916 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1917 } else {
1918 max_state = intel_pstate_get_base_pstate(cpu);
1919 turbo_max = cpu->pstate.turbo_pstate;
1920 }
1921
1922 max_policy_perf = max_state * policy->max / max_freq;
1923 if (policy->max == policy->min) {
1924 min_policy_perf = max_policy_perf;
1925 } else {
1926 min_policy_perf = max_state * policy->min / max_freq;
1927 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1928 0, max_policy_perf);
1929 }
1930
1931 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1932 policy->cpu, max_state,
1933 min_policy_perf, max_policy_perf);
1934
1935 /* Normalize user input to [min_perf, max_perf] */
1936 if (per_cpu_limits) {
1937 cpu->min_perf_ratio = min_policy_perf;
1938 cpu->max_perf_ratio = max_policy_perf;
1939 } else {
1940 int32_t global_min, global_max;
1941
1942 /* Global limits are in percent of the maximum turbo P-state. */
1943 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1944 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1945 global_min = clamp_t(int32_t, global_min, 0, global_max);
1946
1947 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1948 global_min, global_max);
1949
1950 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1951 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1952 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1953 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1954
1955 /* Make sure min_perf <= max_perf */
1956 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1957 cpu->max_perf_ratio);
1958
1959 }
1960 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1961 cpu->max_perf_ratio,
1962 cpu->min_perf_ratio);
1963 }
1964
1965 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1966 {
1967 struct cpudata *cpu;
1968
1969 if (!policy->cpuinfo.max_freq)
1970 return -ENODEV;
1971
1972 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1973 policy->cpuinfo.max_freq, policy->max);
1974
1975 cpu = all_cpu_data[policy->cpu];
1976 cpu->policy = policy->policy;
1977
1978 mutex_lock(&intel_pstate_limits_lock);
1979
1980 intel_pstate_update_perf_limits(policy, cpu);
1981
1982 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1983 /*
1984 * NOHZ_FULL CPUs need this as the governor callback may not
1985 * be invoked on them.
1986 */
1987 intel_pstate_clear_update_util_hook(policy->cpu);
1988 intel_pstate_max_within_limits(cpu);
1989 } else {
1990 intel_pstate_set_update_util_hook(policy->cpu);
1991 }
1992
1993 if (hwp_active) {
1994 /*
1995 * When hwp_boost was active before and dynamically it
1996 * was turned off, in that case we need to clear the
1997 * update util hook.
1998 */
1999 if (!hwp_boost)
2000 intel_pstate_clear_update_util_hook(policy->cpu);
2001 intel_pstate_hwp_set(policy->cpu);
2002 }
2003
2004 mutex_unlock(&intel_pstate_limits_lock);
2005
2006 return 0;
2007 }
2008
2009 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2010 struct cpudata *cpu)
2011 {
2012 if (!hwp_active &&
2013 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2014 policy->max < policy->cpuinfo.max_freq &&
2015 policy->max > cpu->pstate.max_freq) {
2016 pr_debug("policy->max > max non turbo frequency\n");
2017 policy->max = policy->cpuinfo.max_freq;
2018 }
2019 }
2020
2021 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2022 {
2023 struct cpudata *cpu = all_cpu_data[policy->cpu];
2024
2025 update_turbo_state();
2026 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2027 intel_pstate_get_max_freq(cpu));
2028
2029 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2030 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2031 return -EINVAL;
2032
2033 intel_pstate_adjust_policy_max(policy, cpu);
2034
2035 return 0;
2036 }
2037
2038 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2039 {
2040 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2041 }
2042
2043 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2044 {
2045 pr_debug("CPU %d exiting\n", policy->cpu);
2046
2047 intel_pstate_clear_update_util_hook(policy->cpu);
2048 if (hwp_active)
2049 intel_pstate_hwp_save_state(policy);
2050 else
2051 intel_cpufreq_stop_cpu(policy);
2052 }
2053
2054 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2055 {
2056 intel_pstate_exit_perf_limits(policy);
2057
2058 policy->fast_switch_possible = false;
2059
2060 return 0;
2061 }
2062
2063 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2064 {
2065 struct cpudata *cpu;
2066 int rc;
2067
2068 rc = intel_pstate_init_cpu(policy->cpu);
2069 if (rc)
2070 return rc;
2071
2072 cpu = all_cpu_data[policy->cpu];
2073
2074 cpu->max_perf_ratio = 0xFF;
2075 cpu->min_perf_ratio = 0;
2076
2077 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2078 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2079
2080 /* cpuinfo and default policy values */
2081 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2082 update_turbo_state();
2083 policy->cpuinfo.max_freq = global.turbo_disabled ?
2084 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2085 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2086
2087 if (hwp_active) {
2088 unsigned int max_freq;
2089
2090 max_freq = global.turbo_disabled ?
2091 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2092 if (max_freq < policy->cpuinfo.max_freq)
2093 policy->cpuinfo.max_freq = max_freq;
2094 }
2095
2096 intel_pstate_init_acpi_perf_limits(policy);
2097
2098 policy->fast_switch_possible = true;
2099
2100 return 0;
2101 }
2102
2103 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2104 {
2105 int ret = __intel_pstate_cpu_init(policy);
2106
2107 if (ret)
2108 return ret;
2109
2110 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2111 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2112 else
2113 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2114
2115 return 0;
2116 }
2117
2118 static struct cpufreq_driver intel_pstate = {
2119 .flags = CPUFREQ_CONST_LOOPS,
2120 .verify = intel_pstate_verify_policy,
2121 .setpolicy = intel_pstate_set_policy,
2122 .suspend = intel_pstate_hwp_save_state,
2123 .resume = intel_pstate_resume,
2124 .init = intel_pstate_cpu_init,
2125 .exit = intel_pstate_cpu_exit,
2126 .stop_cpu = intel_pstate_stop_cpu,
2127 .name = "intel_pstate",
2128 };
2129
2130 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2131 {
2132 struct cpudata *cpu = all_cpu_data[policy->cpu];
2133
2134 update_turbo_state();
2135 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2136 intel_pstate_get_max_freq(cpu));
2137
2138 intel_pstate_adjust_policy_max(policy, cpu);
2139
2140 intel_pstate_update_perf_limits(policy, cpu);
2141
2142 return 0;
2143 }
2144
2145 /* Use of trace in passive mode:
2146 *
2147 * In passive mode the trace core_busy field (also known as the
2148 * performance field, and lablelled as such on the graphs; also known as
2149 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2150 * driver call was via the normal or fast switch path. Various graphs
2151 * output from the intel_pstate_tracer.py utility that include core_busy
2152 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2153 * so we use 10 to indicate the the normal path through the driver, and
2154 * 90 to indicate the fast switch path through the driver.
2155 * The scaled_busy field is not used, and is set to 0.
2156 */
2157
2158 #define INTEL_PSTATE_TRACE_TARGET 10
2159 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2160
2161 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2162 {
2163 struct sample *sample;
2164
2165 if (!trace_pstate_sample_enabled())
2166 return;
2167
2168 if (!intel_pstate_sample(cpu, ktime_get()))
2169 return;
2170
2171 sample = &cpu->sample;
2172 trace_pstate_sample(trace_type,
2173 0,
2174 old_pstate,
2175 cpu->pstate.current_pstate,
2176 sample->mperf,
2177 sample->aperf,
2178 sample->tsc,
2179 get_avg_frequency(cpu),
2180 fp_toint(cpu->iowait_boost * 100));
2181 }
2182
2183 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2184 unsigned int target_freq,
2185 unsigned int relation)
2186 {
2187 struct cpudata *cpu = all_cpu_data[policy->cpu];
2188 struct cpufreq_freqs freqs;
2189 int target_pstate, old_pstate;
2190
2191 update_turbo_state();
2192
2193 freqs.old = policy->cur;
2194 freqs.new = target_freq;
2195
2196 cpufreq_freq_transition_begin(policy, &freqs);
2197 switch (relation) {
2198 case CPUFREQ_RELATION_L:
2199 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2200 break;
2201 case CPUFREQ_RELATION_H:
2202 target_pstate = freqs.new / cpu->pstate.scaling;
2203 break;
2204 default:
2205 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2206 break;
2207 }
2208 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2209 old_pstate = cpu->pstate.current_pstate;
2210 if (target_pstate != cpu->pstate.current_pstate) {
2211 cpu->pstate.current_pstate = target_pstate;
2212 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2213 pstate_funcs.get_val(cpu, target_pstate));
2214 }
2215 freqs.new = target_pstate * cpu->pstate.scaling;
2216 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2217 cpufreq_freq_transition_end(policy, &freqs, false);
2218
2219 return 0;
2220 }
2221
2222 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2223 unsigned int target_freq)
2224 {
2225 struct cpudata *cpu = all_cpu_data[policy->cpu];
2226 int target_pstate, old_pstate;
2227
2228 update_turbo_state();
2229
2230 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2231 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2232 old_pstate = cpu->pstate.current_pstate;
2233 intel_pstate_update_pstate(cpu, target_pstate);
2234 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2235 return target_pstate * cpu->pstate.scaling;
2236 }
2237
2238 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2239 {
2240 int ret = __intel_pstate_cpu_init(policy);
2241
2242 if (ret)
2243 return ret;
2244
2245 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2246 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2247 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2248 policy->cur = policy->cpuinfo.min_freq;
2249
2250 return 0;
2251 }
2252
2253 static struct cpufreq_driver intel_cpufreq = {
2254 .flags = CPUFREQ_CONST_LOOPS,
2255 .verify = intel_cpufreq_verify_policy,
2256 .target = intel_cpufreq_target,
2257 .fast_switch = intel_cpufreq_fast_switch,
2258 .init = intel_cpufreq_cpu_init,
2259 .exit = intel_pstate_cpu_exit,
2260 .stop_cpu = intel_cpufreq_stop_cpu,
2261 .name = "intel_cpufreq",
2262 };
2263
2264 static struct cpufreq_driver *default_driver = &intel_pstate;
2265
2266 static void intel_pstate_driver_cleanup(void)
2267 {
2268 unsigned int cpu;
2269
2270 get_online_cpus();
2271 for_each_online_cpu(cpu) {
2272 if (all_cpu_data[cpu]) {
2273 if (intel_pstate_driver == &intel_pstate)
2274 intel_pstate_clear_update_util_hook(cpu);
2275
2276 kfree(all_cpu_data[cpu]);
2277 all_cpu_data[cpu] = NULL;
2278 }
2279 }
2280 put_online_cpus();
2281 intel_pstate_driver = NULL;
2282 }
2283
2284 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2285 {
2286 int ret;
2287
2288 memset(&global, 0, sizeof(global));
2289 global.max_perf_pct = 100;
2290
2291 intel_pstate_driver = driver;
2292 ret = cpufreq_register_driver(intel_pstate_driver);
2293 if (ret) {
2294 intel_pstate_driver_cleanup();
2295 return ret;
2296 }
2297
2298 global.min_perf_pct = min_perf_pct_min();
2299
2300 return 0;
2301 }
2302
2303 static int intel_pstate_unregister_driver(void)
2304 {
2305 if (hwp_active)
2306 return -EBUSY;
2307
2308 cpufreq_unregister_driver(intel_pstate_driver);
2309 intel_pstate_driver_cleanup();
2310
2311 return 0;
2312 }
2313
2314 static ssize_t intel_pstate_show_status(char *buf)
2315 {
2316 if (!intel_pstate_driver)
2317 return sprintf(buf, "off\n");
2318
2319 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2320 "active" : "passive");
2321 }
2322
2323 static int intel_pstate_update_status(const char *buf, size_t size)
2324 {
2325 int ret;
2326
2327 if (size == 3 && !strncmp(buf, "off", size))
2328 return intel_pstate_driver ?
2329 intel_pstate_unregister_driver() : -EINVAL;
2330
2331 if (size == 6 && !strncmp(buf, "active", size)) {
2332 if (intel_pstate_driver) {
2333 if (intel_pstate_driver == &intel_pstate)
2334 return 0;
2335
2336 ret = intel_pstate_unregister_driver();
2337 if (ret)
2338 return ret;
2339 }
2340
2341 return intel_pstate_register_driver(&intel_pstate);
2342 }
2343
2344 if (size == 7 && !strncmp(buf, "passive", size)) {
2345 if (intel_pstate_driver) {
2346 if (intel_pstate_driver == &intel_cpufreq)
2347 return 0;
2348
2349 ret = intel_pstate_unregister_driver();
2350 if (ret)
2351 return ret;
2352 }
2353
2354 return intel_pstate_register_driver(&intel_cpufreq);
2355 }
2356
2357 return -EINVAL;
2358 }
2359
2360 static int no_load __initdata;
2361 static int no_hwp __initdata;
2362 static int hwp_only __initdata;
2363 static unsigned int force_load __initdata;
2364
2365 static int __init intel_pstate_msrs_not_valid(void)
2366 {
2367 if (!pstate_funcs.get_max() ||
2368 !pstate_funcs.get_min() ||
2369 !pstate_funcs.get_turbo())
2370 return -ENODEV;
2371
2372 return 0;
2373 }
2374
2375 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2376 {
2377 pstate_funcs.get_max = funcs->get_max;
2378 pstate_funcs.get_max_physical = funcs->get_max_physical;
2379 pstate_funcs.get_min = funcs->get_min;
2380 pstate_funcs.get_turbo = funcs->get_turbo;
2381 pstate_funcs.get_scaling = funcs->get_scaling;
2382 pstate_funcs.get_val = funcs->get_val;
2383 pstate_funcs.get_vid = funcs->get_vid;
2384 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2385 }
2386
2387 #ifdef CONFIG_ACPI
2388
2389 static bool __init intel_pstate_no_acpi_pss(void)
2390 {
2391 int i;
2392
2393 for_each_possible_cpu(i) {
2394 acpi_status status;
2395 union acpi_object *pss;
2396 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2397 struct acpi_processor *pr = per_cpu(processors, i);
2398
2399 if (!pr)
2400 continue;
2401
2402 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2403 if (ACPI_FAILURE(status))
2404 continue;
2405
2406 pss = buffer.pointer;
2407 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2408 kfree(pss);
2409 return false;
2410 }
2411
2412 kfree(pss);
2413 }
2414
2415 return true;
2416 }
2417
2418 static bool __init intel_pstate_no_acpi_pcch(void)
2419 {
2420 acpi_status status;
2421 acpi_handle handle;
2422
2423 status = acpi_get_handle(NULL, "\\_SB", &handle);
2424 if (ACPI_FAILURE(status))
2425 return true;
2426
2427 return !acpi_has_method(handle, "PCCH");
2428 }
2429
2430 static bool __init intel_pstate_has_acpi_ppc(void)
2431 {
2432 int i;
2433
2434 for_each_possible_cpu(i) {
2435 struct acpi_processor *pr = per_cpu(processors, i);
2436
2437 if (!pr)
2438 continue;
2439 if (acpi_has_method(pr->handle, "_PPC"))
2440 return true;
2441 }
2442 return false;
2443 }
2444
2445 enum {
2446 PSS,
2447 PPC,
2448 };
2449
2450 /* Hardware vendor-specific info that has its own power management modes */
2451 static struct acpi_platform_list plat_info[] __initdata = {
2452 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2453 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2454 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2455 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2456 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2457 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2458 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2459 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2460 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2461 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2462 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2463 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2464 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2465 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2466 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2467 { } /* End */
2468 };
2469
2470 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2471 {
2472 const struct x86_cpu_id *id;
2473 u64 misc_pwr;
2474 int idx;
2475
2476 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2477 if (id) {
2478 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2479 if ( misc_pwr & (1 << 8))
2480 return true;
2481 }
2482
2483 idx = acpi_match_platform_list(plat_info);
2484 if (idx < 0)
2485 return false;
2486
2487 switch (plat_info[idx].data) {
2488 case PSS:
2489 if (!intel_pstate_no_acpi_pss())
2490 return false;
2491
2492 return intel_pstate_no_acpi_pcch();
2493 case PPC:
2494 return intel_pstate_has_acpi_ppc() && !force_load;
2495 }
2496
2497 return false;
2498 }
2499
2500 static void intel_pstate_request_control_from_smm(void)
2501 {
2502 /*
2503 * It may be unsafe to request P-states control from SMM if _PPC support
2504 * has not been enabled.
2505 */
2506 if (acpi_ppc)
2507 acpi_processor_pstate_control();
2508 }
2509 #else /* CONFIG_ACPI not enabled */
2510 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2511 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2512 static inline void intel_pstate_request_control_from_smm(void) {}
2513 #endif /* CONFIG_ACPI */
2514
2515 #define INTEL_PSTATE_HWP_BROADWELL 0x01
2516
2517 #define ICPU_HWP(model, hwp_mode) \
2518 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2519
2520 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2521 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2522 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2523 ICPU_HWP(X86_MODEL_ANY, 0),
2524 {}
2525 };
2526
2527 static int __init intel_pstate_init(void)
2528 {
2529 const struct x86_cpu_id *id;
2530 int rc;
2531
2532 if (no_load)
2533 return -ENODEV;
2534
2535 id = x86_match_cpu(hwp_support_ids);
2536 if (id) {
2537 copy_cpu_funcs(&core_funcs);
2538 if (!no_hwp) {
2539 hwp_active++;
2540 hwp_mode_bdw = id->driver_data;
2541 intel_pstate.attr = hwp_cpufreq_attrs;
2542 goto hwp_cpu_matched;
2543 }
2544 } else {
2545 id = x86_match_cpu(intel_pstate_cpu_ids);
2546 if (!id)
2547 return -ENODEV;
2548
2549 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2550 }
2551
2552 if (intel_pstate_msrs_not_valid())
2553 return -ENODEV;
2554
2555 hwp_cpu_matched:
2556 /*
2557 * The Intel pstate driver will be ignored if the platform
2558 * firmware has its own power management modes.
2559 */
2560 if (intel_pstate_platform_pwr_mgmt_exists())
2561 return -ENODEV;
2562
2563 if (!hwp_active && hwp_only)
2564 return -ENOTSUPP;
2565
2566 pr_info("Intel P-state driver initializing\n");
2567
2568 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2569 if (!all_cpu_data)
2570 return -ENOMEM;
2571
2572 intel_pstate_request_control_from_smm();
2573
2574 intel_pstate_sysfs_expose_params();
2575
2576 mutex_lock(&intel_pstate_driver_lock);
2577 rc = intel_pstate_register_driver(default_driver);
2578 mutex_unlock(&intel_pstate_driver_lock);
2579 if (rc)
2580 return rc;
2581
2582 if (hwp_active)
2583 pr_info("HWP enabled\n");
2584
2585 return 0;
2586 }
2587 device_initcall(intel_pstate_init);
2588
2589 static int __init intel_pstate_setup(char *str)
2590 {
2591 if (!str)
2592 return -EINVAL;
2593
2594 if (!strcmp(str, "disable")) {
2595 no_load = 1;
2596 } else if (!strcmp(str, "passive")) {
2597 pr_info("Passive mode enabled\n");
2598 default_driver = &intel_cpufreq;
2599 no_hwp = 1;
2600 }
2601 if (!strcmp(str, "no_hwp")) {
2602 pr_info("HWP disabled\n");
2603 no_hwp = 1;
2604 }
2605 if (!strcmp(str, "force"))
2606 force_load = 1;
2607 if (!strcmp(str, "hwp_only"))
2608 hwp_only = 1;
2609 if (!strcmp(str, "per_cpu_perf_limits"))
2610 per_cpu_limits = true;
2611
2612 #ifdef CONFIG_ACPI
2613 if (!strcmp(str, "support_acpi_ppc"))
2614 acpi_ppc = true;
2615 #endif
2616
2617 return 0;
2618 }
2619 early_param("intel_pstate", intel_pstate_setup);
2620
2621 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2622 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2623 MODULE_LICENSE("GPL");
Linux with added FPC-III support