?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / crypto / amcc / crypto4xx_core.c
blob68d5ea818b6c014c1bbe9d49c3f458eafc927df5
1 /**
2 * AMCC SoC PPC4xx Crypto Driver
3 *
4 * Copyright (c) 2008 Applied Micro Circuits Corporation.
5 * All rights reserved. James Hsiao <jhsiao@amcc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * This file implements AMCC crypto offload Linux device driver for use with
18 * Linux CryptoAPI.
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/interrupt.h>
23 #include <linux/spinlock_types.h>
24 #include <linux/random.h>
25 #include <linux/scatterlist.h>
26 #include <linux/crypto.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_platform.h>
34 #include <linux/slab.h>
35 #include <asm/dcr.h>
36 #include <asm/dcr-regs.h>
37 #include <asm/cacheflush.h>
38 #include <crypto/aead.h>
39 #include <crypto/aes.h>
40 #include <crypto/ctr.h>
41 #include <crypto/gcm.h>
42 #include <crypto/sha.h>
43 #include <crypto/scatterwalk.h>
44 #include <crypto/skcipher.h>
45 #include <crypto/internal/aead.h>
46 #include <crypto/internal/skcipher.h>
47 #include "crypto4xx_reg_def.h"
48 #include "crypto4xx_core.h"
49 #include "crypto4xx_sa.h"
50 #include "crypto4xx_trng.h"
51
52 #define PPC4XX_SEC_VERSION_STR "0.5"
53
54 /**
55 * PPC4xx Crypto Engine Initialization Routine
56 */
57 static void crypto4xx_hw_init(struct crypto4xx_device *dev)
58 {
59 union ce_ring_size ring_size;
60 union ce_ring_control ring_ctrl;
61 union ce_part_ring_size part_ring_size;
62 union ce_io_threshold io_threshold;
63 u32 rand_num;
64 union ce_pe_dma_cfg pe_dma_cfg;
65 u32 device_ctrl;
66
67 writel(PPC4XX_BYTE_ORDER, dev->ce_base + CRYPTO4XX_BYTE_ORDER_CFG);
68 /* setup pe dma, include reset sg, pdr and pe, then release reset */
69 pe_dma_cfg.w = 0;
70 pe_dma_cfg.bf.bo_sgpd_en = 1;
71 pe_dma_cfg.bf.bo_data_en = 0;
72 pe_dma_cfg.bf.bo_sa_en = 1;
73 pe_dma_cfg.bf.bo_pd_en = 1;
74 pe_dma_cfg.bf.dynamic_sa_en = 1;
75 pe_dma_cfg.bf.reset_sg = 1;
76 pe_dma_cfg.bf.reset_pdr = 1;
77 pe_dma_cfg.bf.reset_pe = 1;
78 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
79 /* un reset pe,sg and pdr */
80 pe_dma_cfg.bf.pe_mode = 0;
81 pe_dma_cfg.bf.reset_sg = 0;
82 pe_dma_cfg.bf.reset_pdr = 0;
83 pe_dma_cfg.bf.reset_pe = 0;
84 pe_dma_cfg.bf.bo_td_en = 0;
85 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
86 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_PDR_BASE);
87 writel(dev->pdr_pa, dev->ce_base + CRYPTO4XX_RDR_BASE);
88 writel(PPC4XX_PRNG_CTRL_AUTO_EN, dev->ce_base + CRYPTO4XX_PRNG_CTRL);
89 get_random_bytes(&rand_num, sizeof(rand_num));
90 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_L);
91 get_random_bytes(&rand_num, sizeof(rand_num));
92 writel(rand_num, dev->ce_base + CRYPTO4XX_PRNG_SEED_H);
93 ring_size.w = 0;
94 ring_size.bf.ring_offset = PPC4XX_PD_SIZE;
95 ring_size.bf.ring_size = PPC4XX_NUM_PD;
96 writel(ring_size.w, dev->ce_base + CRYPTO4XX_RING_SIZE);
97 ring_ctrl.w = 0;
98 writel(ring_ctrl.w, dev->ce_base + CRYPTO4XX_RING_CTRL);
99 device_ctrl = readl(dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
100 device_ctrl |= PPC4XX_DC_3DES_EN;
101 writel(device_ctrl, dev->ce_base + CRYPTO4XX_DEVICE_CTRL);
102 writel(dev->gdr_pa, dev->ce_base + CRYPTO4XX_GATH_RING_BASE);
103 writel(dev->sdr_pa, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE);
104 part_ring_size.w = 0;
105 part_ring_size.bf.sdr_size = PPC4XX_SDR_SIZE;
106 part_ring_size.bf.gdr_size = PPC4XX_GDR_SIZE;
107 writel(part_ring_size.w, dev->ce_base + CRYPTO4XX_PART_RING_SIZE);
108 writel(PPC4XX_SD_BUFFER_SIZE, dev->ce_base + CRYPTO4XX_PART_RING_CFG);
109 io_threshold.w = 0;
110 io_threshold.bf.output_threshold = PPC4XX_OUTPUT_THRESHOLD;
111 io_threshold.bf.input_threshold = PPC4XX_INPUT_THRESHOLD;
112 writel(io_threshold.w, dev->ce_base + CRYPTO4XX_IO_THRESHOLD);
113 writel(0, dev->ce_base + CRYPTO4XX_PDR_BASE_UADDR);
114 writel(0, dev->ce_base + CRYPTO4XX_RDR_BASE_UADDR);
115 writel(0, dev->ce_base + CRYPTO4XX_PKT_SRC_UADDR);
116 writel(0, dev->ce_base + CRYPTO4XX_PKT_DEST_UADDR);
117 writel(0, dev->ce_base + CRYPTO4XX_SA_UADDR);
118 writel(0, dev->ce_base + CRYPTO4XX_GATH_RING_BASE_UADDR);
119 writel(0, dev->ce_base + CRYPTO4XX_SCAT_RING_BASE_UADDR);
120 /* un reset pe,sg and pdr */
121 pe_dma_cfg.bf.pe_mode = 1;
122 pe_dma_cfg.bf.reset_sg = 0;
123 pe_dma_cfg.bf.reset_pdr = 0;
124 pe_dma_cfg.bf.reset_pe = 0;
125 pe_dma_cfg.bf.bo_td_en = 0;
126 writel(pe_dma_cfg.w, dev->ce_base + CRYPTO4XX_PE_DMA_CFG);
127 /*clear all pending interrupt*/
128 writel(PPC4XX_INTERRUPT_CLR, dev->ce_base + CRYPTO4XX_INT_CLR);
129 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
130 writel(PPC4XX_INT_DESCR_CNT, dev->ce_base + CRYPTO4XX_INT_DESCR_CNT);
131 writel(PPC4XX_INT_CFG, dev->ce_base + CRYPTO4XX_INT_CFG);
132 if (dev->is_revb) {
133 writel(PPC4XX_INT_TIMEOUT_CNT_REVB << 10,
134 dev->ce_base + CRYPTO4XX_INT_TIMEOUT_CNT);
135 writel(PPC4XX_PD_DONE_INT | PPC4XX_TMO_ERR_INT,
136 dev->ce_base + CRYPTO4XX_INT_EN);
137 } else {
138 writel(PPC4XX_PD_DONE_INT, dev->ce_base + CRYPTO4XX_INT_EN);
139 }
140 }
141
142 int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size)
143 {
144 ctx->sa_in = kcalloc(size, 4, GFP_ATOMIC);
145 if (ctx->sa_in == NULL)
146 return -ENOMEM;
147
148 ctx->sa_out = kcalloc(size, 4, GFP_ATOMIC);
149 if (ctx->sa_out == NULL) {
150 kfree(ctx->sa_in);
151 ctx->sa_in = NULL;
152 return -ENOMEM;
153 }
154
155 ctx->sa_len = size;
156
157 return 0;
158 }
159
160 void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
161 {
162 kfree(ctx->sa_in);
163 ctx->sa_in = NULL;
164 kfree(ctx->sa_out);
165 ctx->sa_out = NULL;
166 ctx->sa_len = 0;
167 }
168
169 /**
170 * alloc memory for the gather ring
171 * no need to alloc buf for the ring
172 * gdr_tail, gdr_head and gdr_count are initialized by this function
173 */
174 static u32 crypto4xx_build_pdr(struct crypto4xx_device *dev)
175 {
176 int i;
177 dev->pdr = dma_alloc_coherent(dev->core_dev->device,
178 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
179 &dev->pdr_pa, GFP_ATOMIC);
180 if (!dev->pdr)
181 return -ENOMEM;
182
183 dev->pdr_uinfo = kcalloc(PPC4XX_NUM_PD, sizeof(struct pd_uinfo),
184 GFP_KERNEL);
185 if (!dev->pdr_uinfo) {
186 dma_free_coherent(dev->core_dev->device,
187 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
188 dev->pdr,
189 dev->pdr_pa);
190 return -ENOMEM;
191 }
192 memset(dev->pdr, 0, sizeof(struct ce_pd) * PPC4XX_NUM_PD);
193 dev->shadow_sa_pool = dma_alloc_coherent(dev->core_dev->device,
194 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
195 &dev->shadow_sa_pool_pa,
196 GFP_ATOMIC);
197 if (!dev->shadow_sa_pool)
198 return -ENOMEM;
199
200 dev->shadow_sr_pool = dma_alloc_coherent(dev->core_dev->device,
201 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
202 &dev->shadow_sr_pool_pa, GFP_ATOMIC);
203 if (!dev->shadow_sr_pool)
204 return -ENOMEM;
205 for (i = 0; i < PPC4XX_NUM_PD; i++) {
206 struct ce_pd *pd = &dev->pdr[i];
207 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[i];
208
209 pd->sa = dev->shadow_sa_pool_pa +
210 sizeof(union shadow_sa_buf) * i;
211
212 /* alloc 256 bytes which is enough for any kind of dynamic sa */
213 pd_uinfo->sa_va = &dev->shadow_sa_pool[i].sa;
214
215 /* alloc state record */
216 pd_uinfo->sr_va = &dev->shadow_sr_pool[i];
217 pd_uinfo->sr_pa = dev->shadow_sr_pool_pa +
218 sizeof(struct sa_state_record) * i;
219 }
220
221 return 0;
222 }
223
224 static void crypto4xx_destroy_pdr(struct crypto4xx_device *dev)
225 {
226 if (dev->pdr)
227 dma_free_coherent(dev->core_dev->device,
228 sizeof(struct ce_pd) * PPC4XX_NUM_PD,
229 dev->pdr, dev->pdr_pa);
230
231 if (dev->shadow_sa_pool)
232 dma_free_coherent(dev->core_dev->device,
233 sizeof(union shadow_sa_buf) * PPC4XX_NUM_PD,
234 dev->shadow_sa_pool, dev->shadow_sa_pool_pa);
235
236 if (dev->shadow_sr_pool)
237 dma_free_coherent(dev->core_dev->device,
238 sizeof(struct sa_state_record) * PPC4XX_NUM_PD,
239 dev->shadow_sr_pool, dev->shadow_sr_pool_pa);
240
241 kfree(dev->pdr_uinfo);
242 }
243
244 static u32 crypto4xx_get_pd_from_pdr_nolock(struct crypto4xx_device *dev)
245 {
246 u32 retval;
247 u32 tmp;
248
249 retval = dev->pdr_head;
250 tmp = (dev->pdr_head + 1) % PPC4XX_NUM_PD;
251
252 if (tmp == dev->pdr_tail)
253 return ERING_WAS_FULL;
254
255 dev->pdr_head = tmp;
256
257 return retval;
258 }
259
260 static u32 crypto4xx_put_pd_to_pdr(struct crypto4xx_device *dev, u32 idx)
261 {
262 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
263 u32 tail;
264 unsigned long flags;
265
266 spin_lock_irqsave(&dev->core_dev->lock, flags);
267 pd_uinfo->state = PD_ENTRY_FREE;
268
269 if (dev->pdr_tail != PPC4XX_LAST_PD)
270 dev->pdr_tail++;
271 else
272 dev->pdr_tail = 0;
273 tail = dev->pdr_tail;
274 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
275
276 return tail;
277 }
278
279 /**
280 * alloc memory for the gather ring
281 * no need to alloc buf for the ring
282 * gdr_tail, gdr_head and gdr_count are initialized by this function
283 */
284 static u32 crypto4xx_build_gdr(struct crypto4xx_device *dev)
285 {
286 dev->gdr = dma_zalloc_coherent(dev->core_dev->device,
287 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
288 &dev->gdr_pa, GFP_ATOMIC);
289 if (!dev->gdr)
290 return -ENOMEM;
291
292 return 0;
293 }
294
295 static inline void crypto4xx_destroy_gdr(struct crypto4xx_device *dev)
296 {
297 dma_free_coherent(dev->core_dev->device,
298 sizeof(struct ce_gd) * PPC4XX_NUM_GD,
299 dev->gdr, dev->gdr_pa);
300 }
301
302 /*
303 * when this function is called.
304 * preemption or interrupt must be disabled
305 */
306 static u32 crypto4xx_get_n_gd(struct crypto4xx_device *dev, int n)
307 {
308 u32 retval;
309 u32 tmp;
310
311 if (n >= PPC4XX_NUM_GD)
312 return ERING_WAS_FULL;
313
314 retval = dev->gdr_head;
315 tmp = (dev->gdr_head + n) % PPC4XX_NUM_GD;
316 if (dev->gdr_head > dev->gdr_tail) {
317 if (tmp < dev->gdr_head && tmp >= dev->gdr_tail)
318 return ERING_WAS_FULL;
319 } else if (dev->gdr_head < dev->gdr_tail) {
320 if (tmp < dev->gdr_head || tmp >= dev->gdr_tail)
321 return ERING_WAS_FULL;
322 }
323 dev->gdr_head = tmp;
324
325 return retval;
326 }
327
328 static u32 crypto4xx_put_gd_to_gdr(struct crypto4xx_device *dev)
329 {
330 unsigned long flags;
331
332 spin_lock_irqsave(&dev->core_dev->lock, flags);
333 if (dev->gdr_tail == dev->gdr_head) {
334 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
335 return 0;
336 }
337
338 if (dev->gdr_tail != PPC4XX_LAST_GD)
339 dev->gdr_tail++;
340 else
341 dev->gdr_tail = 0;
342
343 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
344
345 return 0;
346 }
347
348 static inline struct ce_gd *crypto4xx_get_gdp(struct crypto4xx_device *dev,
349 dma_addr_t *gd_dma, u32 idx)
350 {
351 *gd_dma = dev->gdr_pa + sizeof(struct ce_gd) * idx;
352
353 return &dev->gdr[idx];
354 }
355
356 /**
357 * alloc memory for the scatter ring
358 * need to alloc buf for the ring
359 * sdr_tail, sdr_head and sdr_count are initialized by this function
360 */
361 static u32 crypto4xx_build_sdr(struct crypto4xx_device *dev)
362 {
363 int i;
364
365 /* alloc memory for scatter descriptor ring */
366 dev->sdr = dma_alloc_coherent(dev->core_dev->device,
367 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
368 &dev->sdr_pa, GFP_ATOMIC);
369 if (!dev->sdr)
370 return -ENOMEM;
371
372 dev->scatter_buffer_va =
373 dma_alloc_coherent(dev->core_dev->device,
374 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
375 &dev->scatter_buffer_pa, GFP_ATOMIC);
376 if (!dev->scatter_buffer_va)
377 return -ENOMEM;
378
379 for (i = 0; i < PPC4XX_NUM_SD; i++) {
380 dev->sdr[i].ptr = dev->scatter_buffer_pa +
381 PPC4XX_SD_BUFFER_SIZE * i;
382 }
383
384 return 0;
385 }
386
387 static void crypto4xx_destroy_sdr(struct crypto4xx_device *dev)
388 {
389 if (dev->sdr)
390 dma_free_coherent(dev->core_dev->device,
391 sizeof(struct ce_sd) * PPC4XX_NUM_SD,
392 dev->sdr, dev->sdr_pa);
393
394 if (dev->scatter_buffer_va)
395 dma_free_coherent(dev->core_dev->device,
396 PPC4XX_SD_BUFFER_SIZE * PPC4XX_NUM_SD,
397 dev->scatter_buffer_va,
398 dev->scatter_buffer_pa);
399 }
400
401 /*
402 * when this function is called.
403 * preemption or interrupt must be disabled
404 */
405 static u32 crypto4xx_get_n_sd(struct crypto4xx_device *dev, int n)
406 {
407 u32 retval;
408 u32 tmp;
409
410 if (n >= PPC4XX_NUM_SD)
411 return ERING_WAS_FULL;
412
413 retval = dev->sdr_head;
414 tmp = (dev->sdr_head + n) % PPC4XX_NUM_SD;
415 if (dev->sdr_head > dev->gdr_tail) {
416 if (tmp < dev->sdr_head && tmp >= dev->sdr_tail)
417 return ERING_WAS_FULL;
418 } else if (dev->sdr_head < dev->sdr_tail) {
419 if (tmp < dev->sdr_head || tmp >= dev->sdr_tail)
420 return ERING_WAS_FULL;
421 } /* the head = tail, or empty case is already take cared */
422 dev->sdr_head = tmp;
423
424 return retval;
425 }
426
427 static u32 crypto4xx_put_sd_to_sdr(struct crypto4xx_device *dev)
428 {
429 unsigned long flags;
430
431 spin_lock_irqsave(&dev->core_dev->lock, flags);
432 if (dev->sdr_tail == dev->sdr_head) {
433 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
434 return 0;
435 }
436 if (dev->sdr_tail != PPC4XX_LAST_SD)
437 dev->sdr_tail++;
438 else
439 dev->sdr_tail = 0;
440 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
441
442 return 0;
443 }
444
445 static inline struct ce_sd *crypto4xx_get_sdp(struct crypto4xx_device *dev,
446 dma_addr_t *sd_dma, u32 idx)
447 {
448 *sd_dma = dev->sdr_pa + sizeof(struct ce_sd) * idx;
449
450 return &dev->sdr[idx];
451 }
452
453 static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
454 struct ce_pd *pd,
455 struct pd_uinfo *pd_uinfo,
456 u32 nbytes,
457 struct scatterlist *dst)
458 {
459 unsigned int first_sd = pd_uinfo->first_sd;
460 unsigned int last_sd;
461 unsigned int overflow = 0;
462 unsigned int to_copy;
463 unsigned int dst_start = 0;
464
465 /*
466 * Because the scatter buffers are all neatly organized in one
467 * big continuous ringbuffer; scatterwalk_map_and_copy() can
468 * be instructed to copy a range of buffers in one go.
469 */
470
471 last_sd = (first_sd + pd_uinfo->num_sd);
472 if (last_sd > PPC4XX_LAST_SD) {
473 last_sd = PPC4XX_LAST_SD;
474 overflow = last_sd % PPC4XX_NUM_SD;
475 }
476
477 while (nbytes) {
478 void *buf = dev->scatter_buffer_va +
479 first_sd * PPC4XX_SD_BUFFER_SIZE;
480
481 to_copy = min(nbytes, PPC4XX_SD_BUFFER_SIZE *
482 (1 + last_sd - first_sd));
483 scatterwalk_map_and_copy(buf, dst, dst_start, to_copy, 1);
484 nbytes -= to_copy;
485
486 if (overflow) {
487 first_sd = 0;
488 last_sd = overflow;
489 dst_start += to_copy;
490 overflow = 0;
491 }
492 }
493 }
494
495 static void crypto4xx_copy_digest_to_dst(void *dst,
496 struct pd_uinfo *pd_uinfo,
497 struct crypto4xx_ctx *ctx)
498 {
499 struct dynamic_sa_ctl *sa = (struct dynamic_sa_ctl *) ctx->sa_in;
500
501 if (sa->sa_command_0.bf.hash_alg == SA_HASH_ALG_SHA1) {
502 memcpy(dst, pd_uinfo->sr_va->save_digest,
503 SA_HASH_ALG_SHA1_DIGEST_SIZE);
504 }
505 }
506
507 static void crypto4xx_ret_sg_desc(struct crypto4xx_device *dev,
508 struct pd_uinfo *pd_uinfo)
509 {
510 int i;
511 if (pd_uinfo->num_gd) {
512 for (i = 0; i < pd_uinfo->num_gd; i++)
513 crypto4xx_put_gd_to_gdr(dev);
514 pd_uinfo->first_gd = 0xffffffff;
515 pd_uinfo->num_gd = 0;
516 }
517 if (pd_uinfo->num_sd) {
518 for (i = 0; i < pd_uinfo->num_sd; i++)
519 crypto4xx_put_sd_to_sdr(dev);
520
521 pd_uinfo->first_sd = 0xffffffff;
522 pd_uinfo->num_sd = 0;
523 }
524 }
525
526 static void crypto4xx_cipher_done(struct crypto4xx_device *dev,
527 struct pd_uinfo *pd_uinfo,
528 struct ce_pd *pd)
529 {
530 struct skcipher_request *req;
531 struct scatterlist *dst;
532 dma_addr_t addr;
533
534 req = skcipher_request_cast(pd_uinfo->async_req);
535
536 if (pd_uinfo->using_sd) {
537 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
538 req->cryptlen, req->dst);
539 } else {
540 dst = pd_uinfo->dest_va;
541 addr = dma_map_page(dev->core_dev->device, sg_page(dst),
542 dst->offset, dst->length, DMA_FROM_DEVICE);
543 }
544
545 if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) {
546 struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
547
548 crypto4xx_memcpy_from_le32((u32 *)req->iv,
549 pd_uinfo->sr_va->save_iv,
550 crypto_skcipher_ivsize(skcipher));
551 }
552
553 crypto4xx_ret_sg_desc(dev, pd_uinfo);
554
555 if (pd_uinfo->state & PD_ENTRY_BUSY)
556 skcipher_request_complete(req, -EINPROGRESS);
557 skcipher_request_complete(req, 0);
558 }
559
560 static void crypto4xx_ahash_done(struct crypto4xx_device *dev,
561 struct pd_uinfo *pd_uinfo)
562 {
563 struct crypto4xx_ctx *ctx;
564 struct ahash_request *ahash_req;
565
566 ahash_req = ahash_request_cast(pd_uinfo->async_req);
567 ctx = crypto_tfm_ctx(ahash_req->base.tfm);
568
569 crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo,
570 crypto_tfm_ctx(ahash_req->base.tfm));
571 crypto4xx_ret_sg_desc(dev, pd_uinfo);
572
573 if (pd_uinfo->state & PD_ENTRY_BUSY)
574 ahash_request_complete(ahash_req, -EINPROGRESS);
575 ahash_request_complete(ahash_req, 0);
576 }
577
578 static void crypto4xx_aead_done(struct crypto4xx_device *dev,
579 struct pd_uinfo *pd_uinfo,
580 struct ce_pd *pd)
581 {
582 struct aead_request *aead_req = container_of(pd_uinfo->async_req,
583 struct aead_request, base);
584 struct scatterlist *dst = pd_uinfo->dest_va;
585 size_t cp_len = crypto_aead_authsize(
586 crypto_aead_reqtfm(aead_req));
587 u32 icv[AES_BLOCK_SIZE];
588 int err = 0;
589
590 if (pd_uinfo->using_sd) {
591 crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
592 pd->pd_ctl_len.bf.pkt_len,
593 dst);
594 } else {
595 __dma_sync_page(sg_page(dst), dst->offset, dst->length,
596 DMA_FROM_DEVICE);
597 }
598
599 if (pd_uinfo->sa_va->sa_command_0.bf.dir == DIR_OUTBOUND) {
600 /* append icv at the end */
601 crypto4xx_memcpy_from_le32(icv, pd_uinfo->sr_va->save_digest,
602 sizeof(icv));
603
604 scatterwalk_map_and_copy(icv, dst, aead_req->cryptlen,
605 cp_len, 1);
606 } else {
607 /* check icv at the end */
608 scatterwalk_map_and_copy(icv, aead_req->src,
609 aead_req->assoclen + aead_req->cryptlen -
610 cp_len, cp_len, 0);
611
612 crypto4xx_memcpy_from_le32(icv, icv, sizeof(icv));
613
614 if (crypto_memneq(icv, pd_uinfo->sr_va->save_digest, cp_len))
615 err = -EBADMSG;
616 }
617
618 crypto4xx_ret_sg_desc(dev, pd_uinfo);
619
620 if (pd->pd_ctl.bf.status & 0xff) {
621 if (!__ratelimit(&dev->aead_ratelimit)) {
622 if (pd->pd_ctl.bf.status & 2)
623 pr_err("pad fail error\n");
624 if (pd->pd_ctl.bf.status & 4)
625 pr_err("seqnum fail\n");
626 if (pd->pd_ctl.bf.status & 8)
627 pr_err("error _notify\n");
628 pr_err("aead return err status = 0x%02x\n",
629 pd->pd_ctl.bf.status & 0xff);
630 pr_err("pd pad_ctl = 0x%08x\n",
631 pd->pd_ctl.bf.pd_pad_ctl);
632 }
633 err = -EINVAL;
634 }
635
636 if (pd_uinfo->state & PD_ENTRY_BUSY)
637 aead_request_complete(aead_req, -EINPROGRESS);
638
639 aead_request_complete(aead_req, err);
640 }
641
642 static void crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
643 {
644 struct ce_pd *pd = &dev->pdr[idx];
645 struct pd_uinfo *pd_uinfo = &dev->pdr_uinfo[idx];
646
647 switch (crypto_tfm_alg_type(pd_uinfo->async_req->tfm)) {
648 case CRYPTO_ALG_TYPE_SKCIPHER:
649 crypto4xx_cipher_done(dev, pd_uinfo, pd);
650 break;
651 case CRYPTO_ALG_TYPE_AEAD:
652 crypto4xx_aead_done(dev, pd_uinfo, pd);
653 break;
654 case CRYPTO_ALG_TYPE_AHASH:
655 crypto4xx_ahash_done(dev, pd_uinfo);
656 break;
657 }
658 }
659
660 static void crypto4xx_stop_all(struct crypto4xx_core_device *core_dev)
661 {
662 crypto4xx_destroy_pdr(core_dev->dev);
663 crypto4xx_destroy_gdr(core_dev->dev);
664 crypto4xx_destroy_sdr(core_dev->dev);
665 iounmap(core_dev->dev->ce_base);
666 kfree(core_dev->dev);
667 kfree(core_dev);
668 }
669
670 static u32 get_next_gd(u32 current)
671 {
672 if (current != PPC4XX_LAST_GD)
673 return current + 1;
674 else
675 return 0;
676 }
677
678 static u32 get_next_sd(u32 current)
679 {
680 if (current != PPC4XX_LAST_SD)
681 return current + 1;
682 else
683 return 0;
684 }
685
686 int crypto4xx_build_pd(struct crypto_async_request *req,
687 struct crypto4xx_ctx *ctx,
688 struct scatterlist *src,
689 struct scatterlist *dst,
690 const unsigned int datalen,
691 const __le32 *iv, const u32 iv_len,
692 const struct dynamic_sa_ctl *req_sa,
693 const unsigned int sa_len,
694 const unsigned int assoclen,
695 struct scatterlist *_dst)
696 {
697 struct crypto4xx_device *dev = ctx->dev;
698 struct dynamic_sa_ctl *sa;
699 struct ce_gd *gd;
700 struct ce_pd *pd;
701 u32 num_gd, num_sd;
702 u32 fst_gd = 0xffffffff;
703 u32 fst_sd = 0xffffffff;
704 u32 pd_entry;
705 unsigned long flags;
706 struct pd_uinfo *pd_uinfo;
707 unsigned int nbytes = datalen;
708 size_t offset_to_sr_ptr;
709 u32 gd_idx = 0;
710 int tmp;
711 bool is_busy, force_sd;
712
713 /*
714 * There's a very subtile/disguised "bug" in the hardware that
715 * gets indirectly mentioned in 18.1.3.5 Encryption/Decryption
716 * of the hardware spec:
717 * *drum roll* the AES/(T)DES OFB and CFB modes are listed as
718 * operation modes for >>> "Block ciphers" <<<.
719 *
720 * To workaround this issue and stop the hardware from causing
721 * "overran dst buffer" on crypttexts that are not a multiple
722 * of 16 (AES_BLOCK_SIZE), we force the driver to use the
723 * scatter buffers.
724 */
725 force_sd = (req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_CFB
726 || req_sa->sa_command_1.bf.crypto_mode9_8 == CRYPTO_MODE_OFB)
727 && (datalen % AES_BLOCK_SIZE);
728
729 /* figure how many gd are needed */
730 tmp = sg_nents_for_len(src, assoclen + datalen);
731 if (tmp < 0) {
732 dev_err(dev->core_dev->device, "Invalid number of src SG.\n");
733 return tmp;
734 }
735 if (tmp == 1)
736 tmp = 0;
737 num_gd = tmp;
738
739 if (assoclen) {
740 nbytes += assoclen;
741 dst = scatterwalk_ffwd(_dst, dst, assoclen);
742 }
743
744 /* figure how many sd are needed */
745 if (sg_is_last(dst) && force_sd == false) {
746 num_sd = 0;
747 } else {
748 if (datalen > PPC4XX_SD_BUFFER_SIZE) {
749 num_sd = datalen / PPC4XX_SD_BUFFER_SIZE;
750 if (datalen % PPC4XX_SD_BUFFER_SIZE)
751 num_sd++;
752 } else {
753 num_sd = 1;
754 }
755 }
756
757 /*
758 * The follow section of code needs to be protected
759 * The gather ring and scatter ring needs to be consecutive
760 * In case of run out of any kind of descriptor, the descriptor
761 * already got must be return the original place.
762 */
763 spin_lock_irqsave(&dev->core_dev->lock, flags);
764 /*
765 * Let the caller know to slow down, once more than 13/16ths = 81%
766 * of the available data contexts are being used simultaneously.
767 *
768 * With PPC4XX_NUM_PD = 256, this will leave a "backlog queue" for
769 * 31 more contexts. Before new requests have to be rejected.
770 */
771 if (req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG) {
772 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
773 ((PPC4XX_NUM_PD * 13) / 16);
774 } else {
775 /*
776 * To fix contention issues between ipsec (no blacklog) and
777 * dm-crypto (backlog) reserve 32 entries for "no backlog"
778 * data contexts.
779 */
780 is_busy = ((dev->pdr_head - dev->pdr_tail) % PPC4XX_NUM_PD) >=
781 ((PPC4XX_NUM_PD * 15) / 16);
782
783 if (is_busy) {
784 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
785 return -EBUSY;
786 }
787 }
788
789 if (num_gd) {
790 fst_gd = crypto4xx_get_n_gd(dev, num_gd);
791 if (fst_gd == ERING_WAS_FULL) {
792 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
793 return -EAGAIN;
794 }
795 }
796 if (num_sd) {
797 fst_sd = crypto4xx_get_n_sd(dev, num_sd);
798 if (fst_sd == ERING_WAS_FULL) {
799 if (num_gd)
800 dev->gdr_head = fst_gd;
801 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
802 return -EAGAIN;
803 }
804 }
805 pd_entry = crypto4xx_get_pd_from_pdr_nolock(dev);
806 if (pd_entry == ERING_WAS_FULL) {
807 if (num_gd)
808 dev->gdr_head = fst_gd;
809 if (num_sd)
810 dev->sdr_head = fst_sd;
811 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
812 return -EAGAIN;
813 }
814 spin_unlock_irqrestore(&dev->core_dev->lock, flags);
815
816 pd = &dev->pdr[pd_entry];
817 pd->sa_len = sa_len;
818
819 pd_uinfo = &dev->pdr_uinfo[pd_entry];
820 pd_uinfo->num_gd = num_gd;
821 pd_uinfo->num_sd = num_sd;
822 pd_uinfo->dest_va = dst;
823 pd_uinfo->async_req = req;
824
825 if (iv_len)
826 memcpy(pd_uinfo->sr_va->save_iv, iv, iv_len);
827
828 sa = pd_uinfo->sa_va;
829 memcpy(sa, req_sa, sa_len * 4);
830
831 sa->sa_command_1.bf.hash_crypto_offset = (assoclen >> 2);
832 offset_to_sr_ptr = get_dynamic_sa_offset_state_ptr_field(sa);
833 *(u32 *)((unsigned long)sa + offset_to_sr_ptr) = pd_uinfo->sr_pa;
834
835 if (num_gd) {
836 dma_addr_t gd_dma;
837 struct scatterlist *sg;
838
839 /* get first gd we are going to use */
840 gd_idx = fst_gd;
841 pd_uinfo->first_gd = fst_gd;
842 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
843 pd->src = gd_dma;
844 /* enable gather */
845 sa->sa_command_0.bf.gather = 1;
846 /* walk the sg, and setup gather array */
847
848 sg = src;
849 while (nbytes) {
850 size_t len;
851
852 len = min(sg->length, nbytes);
853 gd->ptr = dma_map_page(dev->core_dev->device,
854 sg_page(sg), sg->offset, len, DMA_TO_DEVICE);
855 gd->ctl_len.len = len;
856 gd->ctl_len.done = 0;
857 gd->ctl_len.ready = 1;
858 if (len >= nbytes)
859 break;
860
861 nbytes -= sg->length;
862 gd_idx = get_next_gd(gd_idx);
863 gd = crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
864 sg = sg_next(sg);
865 }
866 } else {
867 pd->src = (u32)dma_map_page(dev->core_dev->device, sg_page(src),
868 src->offset, min(nbytes, src->length),
869 DMA_TO_DEVICE);
870 /*
871 * Disable gather in sa command
872 */
873 sa->sa_command_0.bf.gather = 0;
874 /*
875 * Indicate gather array is not used
876 */
877 pd_uinfo->first_gd = 0xffffffff;
878 }
879 if (!num_sd) {
880 /*
881 * we know application give us dst a whole piece of memory
882 * no need to use scatter ring.
883 */
884 pd_uinfo->using_sd = 0;
885 pd_uinfo->first_sd = 0xffffffff;
886 sa->sa_command_0.bf.scatter = 0;
887 pd->dest = (u32)dma_map_page(dev->core_dev->device,
888 sg_page(dst), dst->offset,
889 min(datalen, dst->length),
890 DMA_TO_DEVICE);
891 } else {
892 dma_addr_t sd_dma;
893 struct ce_sd *sd = NULL;
894
895 u32 sd_idx = fst_sd;
896 nbytes = datalen;
897 sa->sa_command_0.bf.scatter = 1;
898 pd_uinfo->using_sd = 1;
899 pd_uinfo->first_sd = fst_sd;
900 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
901 pd->dest = sd_dma;
902 /* setup scatter descriptor */
903 sd->ctl.done = 0;
904 sd->ctl.rdy = 1;
905 /* sd->ptr should be setup by sd_init routine*/
906 if (nbytes >= PPC4XX_SD_BUFFER_SIZE)
907 nbytes -= PPC4XX_SD_BUFFER_SIZE;
908 else
909 nbytes = 0;
910 while (nbytes) {
911 sd_idx = get_next_sd(sd_idx);
912 sd = crypto4xx_get_sdp(dev, &sd_dma, sd_idx);
913 /* setup scatter descriptor */
914 sd->ctl.done = 0;
915 sd->ctl.rdy = 1;
916 if (nbytes >= PPC4XX_SD_BUFFER_SIZE) {
917 nbytes -= PPC4XX_SD_BUFFER_SIZE;
918 } else {
919 /*
920 * SD entry can hold PPC4XX_SD_BUFFER_SIZE,
921 * which is more than nbytes, so done.
922 */
923 nbytes = 0;
924 }
925 }
926 }
927
928 pd->pd_ctl.w = PD_CTL_HOST_READY |
929 ((crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AHASH) |
930 (crypto_tfm_alg_type(req->tfm) == CRYPTO_ALG_TYPE_AEAD) ?
931 PD_CTL_HASH_FINAL : 0);
932 pd->pd_ctl_len.w = 0x00400000 | (assoclen + datalen);
933 pd_uinfo->state = PD_ENTRY_INUSE | (is_busy ? PD_ENTRY_BUSY : 0);
934
935 wmb();
936 /* write any value to push engine to read a pd */
937 writel(0, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
938 writel(1, dev->ce_base + CRYPTO4XX_INT_DESCR_RD);
939 return is_busy ? -EBUSY : -EINPROGRESS;
940 }
941
942 /**
943 * Algorithm Registration Functions
944 */
945 static void crypto4xx_ctx_init(struct crypto4xx_alg *amcc_alg,
946 struct crypto4xx_ctx *ctx)
947 {
948 ctx->dev = amcc_alg->dev;
949 ctx->sa_in = NULL;
950 ctx->sa_out = NULL;
951 ctx->sa_len = 0;
952 }
953
954 static int crypto4xx_sk_init(struct crypto_skcipher *sk)
955 {
956 struct skcipher_alg *alg = crypto_skcipher_alg(sk);
957 struct crypto4xx_alg *amcc_alg;
958 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
959
960 if (alg->base.cra_flags & CRYPTO_ALG_NEED_FALLBACK) {
961 ctx->sw_cipher.cipher =
962 crypto_alloc_skcipher(alg->base.cra_name, 0,
963 CRYPTO_ALG_NEED_FALLBACK |
964 CRYPTO_ALG_ASYNC);
965 if (IS_ERR(ctx->sw_cipher.cipher))
966 return PTR_ERR(ctx->sw_cipher.cipher);
967
968 crypto_skcipher_set_reqsize(sk,
969 sizeof(struct skcipher_request) + 32 +
970 crypto_skcipher_reqsize(ctx->sw_cipher.cipher));
971 }
972
973 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.cipher);
974 crypto4xx_ctx_init(amcc_alg, ctx);
975 return 0;
976 }
977
978 static void crypto4xx_common_exit(struct crypto4xx_ctx *ctx)
979 {
980 crypto4xx_free_sa(ctx);
981 }
982
983 static void crypto4xx_sk_exit(struct crypto_skcipher *sk)
984 {
985 struct crypto4xx_ctx *ctx = crypto_skcipher_ctx(sk);
986
987 crypto4xx_common_exit(ctx);
988 if (ctx->sw_cipher.cipher)
989 crypto_free_skcipher(ctx->sw_cipher.cipher);
990 }
991
992 static int crypto4xx_aead_init(struct crypto_aead *tfm)
993 {
994 struct aead_alg *alg = crypto_aead_alg(tfm);
995 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
996 struct crypto4xx_alg *amcc_alg;
997
998 ctx->sw_cipher.aead = crypto_alloc_aead(alg->base.cra_name, 0,
999 CRYPTO_ALG_NEED_FALLBACK |
1000 CRYPTO_ALG_ASYNC);
1001 if (IS_ERR(ctx->sw_cipher.aead))
1002 return PTR_ERR(ctx->sw_cipher.aead);
1003
1004 amcc_alg = container_of(alg, struct crypto4xx_alg, alg.u.aead);
1005 crypto4xx_ctx_init(amcc_alg, ctx);
1006 crypto_aead_set_reqsize(tfm, max(sizeof(struct aead_request) + 32 +
1007 crypto_aead_reqsize(ctx->sw_cipher.aead),
1008 sizeof(struct crypto4xx_aead_reqctx)));
1009 return 0;
1010 }
1011
1012 static void crypto4xx_aead_exit(struct crypto_aead *tfm)
1013 {
1014 struct crypto4xx_ctx *ctx = crypto_aead_ctx(tfm);
1015
1016 crypto4xx_common_exit(ctx);
1017 crypto_free_aead(ctx->sw_cipher.aead);
1018 }
1019
1020 static int crypto4xx_register_alg(struct crypto4xx_device *sec_dev,
1021 struct crypto4xx_alg_common *crypto_alg,
1022 int array_size)
1023 {
1024 struct crypto4xx_alg *alg;
1025 int i;
1026 int rc = 0;
1027
1028 for (i = 0; i < array_size; i++) {
1029 alg = kzalloc(sizeof(struct crypto4xx_alg), GFP_KERNEL);
1030 if (!alg)
1031 return -ENOMEM;
1032
1033 alg->alg = crypto_alg[i];
1034 alg->dev = sec_dev;
1035
1036 switch (alg->alg.type) {
1037 case CRYPTO_ALG_TYPE_AEAD:
1038 rc = crypto_register_aead(&alg->alg.u.aead);
1039 break;
1040
1041 case CRYPTO_ALG_TYPE_AHASH:
1042 rc = crypto_register_ahash(&alg->alg.u.hash);
1043 break;
1044
1045 default:
1046 rc = crypto_register_skcipher(&alg->alg.u.cipher);
1047 break;
1048 }
1049
1050 if (rc)
1051 kfree(alg);
1052 else
1053 list_add_tail(&alg->entry, &sec_dev->alg_list);
1054 }
1055
1056 return 0;
1057 }
1058
1059 static void crypto4xx_unregister_alg(struct crypto4xx_device *sec_dev)
1060 {
1061 struct crypto4xx_alg *alg, *tmp;
1062
1063 list_for_each_entry_safe(alg, tmp, &sec_dev->alg_list, entry) {
1064 list_del(&alg->entry);
1065 switch (alg->alg.type) {
1066 case CRYPTO_ALG_TYPE_AHASH:
1067 crypto_unregister_ahash(&alg->alg.u.hash);
1068 break;
1069
1070 case CRYPTO_ALG_TYPE_AEAD:
1071 crypto_unregister_aead(&alg->alg.u.aead);
1072 break;
1073
1074 default:
1075 crypto_unregister_skcipher(&alg->alg.u.cipher);
1076 }
1077 kfree(alg);
1078 }
1079 }
1080
1081 static void crypto4xx_bh_tasklet_cb(unsigned long data)
1082 {
1083 struct device *dev = (struct device *)data;
1084 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1085 struct pd_uinfo *pd_uinfo;
1086 struct ce_pd *pd;
1087 u32 tail = core_dev->dev->pdr_tail;
1088 u32 head = core_dev->dev->pdr_head;
1089
1090 do {
1091 pd_uinfo = &core_dev->dev->pdr_uinfo[tail];
1092 pd = &core_dev->dev->pdr[tail];
1093 if ((pd_uinfo->state & PD_ENTRY_INUSE) &&
1094 ((READ_ONCE(pd->pd_ctl.w) &
1095 (PD_CTL_PE_DONE | PD_CTL_HOST_READY)) ==
1096 PD_CTL_PE_DONE)) {
1097 crypto4xx_pd_done(core_dev->dev, tail);
1098 tail = crypto4xx_put_pd_to_pdr(core_dev->dev, tail);
1099 } else {
1100 /* if tail not done, break */
1101 break;
1102 }
1103 } while (head != tail);
1104 }
1105
1106 /**
1107 * Top Half of isr.
1108 */
1109 static inline irqreturn_t crypto4xx_interrupt_handler(int irq, void *data,
1110 u32 clr_val)
1111 {
1112 struct device *dev = (struct device *)data;
1113 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1114
1115 writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
1116 tasklet_schedule(&core_dev->tasklet);
1117
1118 return IRQ_HANDLED;
1119 }
1120
1121 static irqreturn_t crypto4xx_ce_interrupt_handler(int irq, void *data)
1122 {
1123 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR);
1124 }
1125
1126 static irqreturn_t crypto4xx_ce_interrupt_handler_revb(int irq, void *data)
1127 {
1128 return crypto4xx_interrupt_handler(irq, data, PPC4XX_INTERRUPT_CLR |
1129 PPC4XX_TMO_ERR_INT);
1130 }
1131
1132 /**
1133 * Supported Crypto Algorithms
1134 */
1135 static struct crypto4xx_alg_common crypto4xx_alg[] = {
1136 /* Crypto AES modes */
1137 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1138 .base = {
1139 .cra_name = "cbc(aes)",
1140 .cra_driver_name = "cbc-aes-ppc4xx",
1141 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1142 .cra_flags = CRYPTO_ALG_ASYNC |
1143 CRYPTO_ALG_KERN_DRIVER_ONLY,
1144 .cra_blocksize = AES_BLOCK_SIZE,
1145 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1146 .cra_module = THIS_MODULE,
1147 },
1148 .min_keysize = AES_MIN_KEY_SIZE,
1149 .max_keysize = AES_MAX_KEY_SIZE,
1150 .ivsize = AES_IV_SIZE,
1151 .setkey = crypto4xx_setkey_aes_cbc,
1152 .encrypt = crypto4xx_encrypt_iv_block,
1153 .decrypt = crypto4xx_decrypt_iv_block,
1154 .init = crypto4xx_sk_init,
1155 .exit = crypto4xx_sk_exit,
1156 } },
1157 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1158 .base = {
1159 .cra_name = "cfb(aes)",
1160 .cra_driver_name = "cfb-aes-ppc4xx",
1161 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1162 .cra_flags = CRYPTO_ALG_ASYNC |
1163 CRYPTO_ALG_KERN_DRIVER_ONLY,
1164 .cra_blocksize = AES_BLOCK_SIZE,
1165 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1166 .cra_module = THIS_MODULE,
1167 },
1168 .min_keysize = AES_MIN_KEY_SIZE,
1169 .max_keysize = AES_MAX_KEY_SIZE,
1170 .ivsize = AES_IV_SIZE,
1171 .setkey = crypto4xx_setkey_aes_cfb,
1172 .encrypt = crypto4xx_encrypt_iv_stream,
1173 .decrypt = crypto4xx_decrypt_iv_stream,
1174 .init = crypto4xx_sk_init,
1175 .exit = crypto4xx_sk_exit,
1176 } },
1177 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1178 .base = {
1179 .cra_name = "ctr(aes)",
1180 .cra_driver_name = "ctr-aes-ppc4xx",
1181 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1182 .cra_flags = CRYPTO_ALG_NEED_FALLBACK |
1183 CRYPTO_ALG_ASYNC |
1184 CRYPTO_ALG_KERN_DRIVER_ONLY,
1185 .cra_blocksize = 1,
1186 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1187 .cra_module = THIS_MODULE,
1188 },
1189 .min_keysize = AES_MIN_KEY_SIZE,
1190 .max_keysize = AES_MAX_KEY_SIZE,
1191 .ivsize = AES_IV_SIZE,
1192 .setkey = crypto4xx_setkey_aes_ctr,
1193 .encrypt = crypto4xx_encrypt_ctr,
1194 .decrypt = crypto4xx_decrypt_ctr,
1195 .init = crypto4xx_sk_init,
1196 .exit = crypto4xx_sk_exit,
1197 } },
1198 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1199 .base = {
1200 .cra_name = "rfc3686(ctr(aes))",
1201 .cra_driver_name = "rfc3686-ctr-aes-ppc4xx",
1202 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1203 .cra_flags = CRYPTO_ALG_ASYNC |
1204 CRYPTO_ALG_KERN_DRIVER_ONLY,
1205 .cra_blocksize = 1,
1206 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1207 .cra_module = THIS_MODULE,
1208 },
1209 .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1210 .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
1211 .ivsize = CTR_RFC3686_IV_SIZE,
1212 .setkey = crypto4xx_setkey_rfc3686,
1213 .encrypt = crypto4xx_rfc3686_encrypt,
1214 .decrypt = crypto4xx_rfc3686_decrypt,
1215 .init = crypto4xx_sk_init,
1216 .exit = crypto4xx_sk_exit,
1217 } },
1218 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1219 .base = {
1220 .cra_name = "ecb(aes)",
1221 .cra_driver_name = "ecb-aes-ppc4xx",
1222 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1223 .cra_flags = CRYPTO_ALG_ASYNC |
1224 CRYPTO_ALG_KERN_DRIVER_ONLY,
1225 .cra_blocksize = 1,
1226 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1227 .cra_module = THIS_MODULE,
1228 },
1229 .min_keysize = AES_MIN_KEY_SIZE,
1230 .max_keysize = AES_MAX_KEY_SIZE,
1231 .setkey = crypto4xx_setkey_aes_ecb,
1232 .encrypt = crypto4xx_encrypt_noiv_block,
1233 .decrypt = crypto4xx_decrypt_noiv_block,
1234 .init = crypto4xx_sk_init,
1235 .exit = crypto4xx_sk_exit,
1236 } },
1237 { .type = CRYPTO_ALG_TYPE_SKCIPHER, .u.cipher = {
1238 .base = {
1239 .cra_name = "ofb(aes)",
1240 .cra_driver_name = "ofb-aes-ppc4xx",
1241 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1242 .cra_flags = CRYPTO_ALG_ASYNC |
1243 CRYPTO_ALG_KERN_DRIVER_ONLY,
1244 .cra_blocksize = 1,
1245 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1246 .cra_module = THIS_MODULE,
1247 },
1248 .min_keysize = AES_MIN_KEY_SIZE,
1249 .max_keysize = AES_MAX_KEY_SIZE,
1250 .ivsize = AES_IV_SIZE,
1251 .setkey = crypto4xx_setkey_aes_ofb,
1252 .encrypt = crypto4xx_encrypt_iv_stream,
1253 .decrypt = crypto4xx_decrypt_iv_stream,
1254 .init = crypto4xx_sk_init,
1255 .exit = crypto4xx_sk_exit,
1256 } },
1257
1258 /* AEAD */
1259 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1260 .setkey = crypto4xx_setkey_aes_ccm,
1261 .setauthsize = crypto4xx_setauthsize_aead,
1262 .encrypt = crypto4xx_encrypt_aes_ccm,
1263 .decrypt = crypto4xx_decrypt_aes_ccm,
1264 .init = crypto4xx_aead_init,
1265 .exit = crypto4xx_aead_exit,
1266 .ivsize = AES_BLOCK_SIZE,
1267 .maxauthsize = 16,
1268 .base = {
1269 .cra_name = "ccm(aes)",
1270 .cra_driver_name = "ccm-aes-ppc4xx",
1271 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1272 .cra_flags = CRYPTO_ALG_ASYNC |
1273 CRYPTO_ALG_NEED_FALLBACK |
1274 CRYPTO_ALG_KERN_DRIVER_ONLY,
1275 .cra_blocksize = 1,
1276 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1277 .cra_module = THIS_MODULE,
1278 },
1279 } },
1280 { .type = CRYPTO_ALG_TYPE_AEAD, .u.aead = {
1281 .setkey = crypto4xx_setkey_aes_gcm,
1282 .setauthsize = crypto4xx_setauthsize_aead,
1283 .encrypt = crypto4xx_encrypt_aes_gcm,
1284 .decrypt = crypto4xx_decrypt_aes_gcm,
1285 .init = crypto4xx_aead_init,
1286 .exit = crypto4xx_aead_exit,
1287 .ivsize = GCM_AES_IV_SIZE,
1288 .maxauthsize = 16,
1289 .base = {
1290 .cra_name = "gcm(aes)",
1291 .cra_driver_name = "gcm-aes-ppc4xx",
1292 .cra_priority = CRYPTO4XX_CRYPTO_PRIORITY,
1293 .cra_flags = CRYPTO_ALG_ASYNC |
1294 CRYPTO_ALG_NEED_FALLBACK |
1295 CRYPTO_ALG_KERN_DRIVER_ONLY,
1296 .cra_blocksize = 1,
1297 .cra_ctxsize = sizeof(struct crypto4xx_ctx),
1298 .cra_module = THIS_MODULE,
1299 },
1300 } },
1301 };
1302
1303 /**
1304 * Module Initialization Routine
1305 */
1306 static int crypto4xx_probe(struct platform_device *ofdev)
1307 {
1308 int rc;
1309 struct resource res;
1310 struct device *dev = &ofdev->dev;
1311 struct crypto4xx_core_device *core_dev;
1312 u32 pvr;
1313 bool is_revb = true;
1314
1315 rc = of_address_to_resource(ofdev->dev.of_node, 0, &res);
1316 if (rc)
1317 return -ENODEV;
1318
1319 if (of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto")) {
1320 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1321 mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET);
1322 mtdcri(SDR0, PPC460EX_SDR0_SRST,
1323 mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET);
1324 } else if (of_find_compatible_node(NULL, NULL,
1325 "amcc,ppc405ex-crypto")) {
1326 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1327 mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET);
1328 mtdcri(SDR0, PPC405EX_SDR0_SRST,
1329 mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET);
1330 is_revb = false;
1331 } else if (of_find_compatible_node(NULL, NULL,
1332 "amcc,ppc460sx-crypto")) {
1333 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1334 mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET);
1335 mtdcri(SDR0, PPC460SX_SDR0_SRST,
1336 mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET);
1337 } else {
1338 printk(KERN_ERR "Crypto Function Not supported!\n");
1339 return -EINVAL;
1340 }
1341
1342 core_dev = kzalloc(sizeof(struct crypto4xx_core_device), GFP_KERNEL);
1343 if (!core_dev)
1344 return -ENOMEM;
1345
1346 dev_set_drvdata(dev, core_dev);
1347 core_dev->ofdev = ofdev;
1348 core_dev->dev = kzalloc(sizeof(struct crypto4xx_device), GFP_KERNEL);
1349 rc = -ENOMEM;
1350 if (!core_dev->dev)
1351 goto err_alloc_dev;
1352
1353 /*
1354 * Older version of 460EX/GT have a hardware bug.
1355 * Hence they do not support H/W based security intr coalescing
1356 */
1357 pvr = mfspr(SPRN_PVR);
1358 if (is_revb && ((pvr >> 4) == 0x130218A)) {
1359 u32 min = PVR_MIN(pvr);
1360
1361 if (min < 4) {
1362 dev_info(dev, "RevA detected - disable interrupt coalescing\n");
1363 is_revb = false;
1364 }
1365 }
1366
1367 core_dev->dev->core_dev = core_dev;
1368 core_dev->dev->is_revb = is_revb;
1369 core_dev->device = dev;
1370 spin_lock_init(&core_dev->lock);
1371 INIT_LIST_HEAD(&core_dev->dev->alg_list);
1372 ratelimit_default_init(&core_dev->dev->aead_ratelimit);
1373 rc = crypto4xx_build_pdr(core_dev->dev);
1374 if (rc)
1375 goto err_build_pdr;
1376
1377 rc = crypto4xx_build_gdr(core_dev->dev);
1378 if (rc)
1379 goto err_build_pdr;
1380
1381 rc = crypto4xx_build_sdr(core_dev->dev);
1382 if (rc)
1383 goto err_build_sdr;
1384
1385 /* Init tasklet for bottom half processing */
1386 tasklet_init(&core_dev->tasklet, crypto4xx_bh_tasklet_cb,
1387 (unsigned long) dev);
1388
1389 core_dev->dev->ce_base = of_iomap(ofdev->dev.of_node, 0);
1390 if (!core_dev->dev->ce_base) {
1391 dev_err(dev, "failed to of_iomap\n");
1392 rc = -ENOMEM;
1393 goto err_iomap;
1394 }
1395
1396 /* Register for Crypto isr, Crypto Engine IRQ */
1397 core_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1398 rc = request_irq(core_dev->irq, is_revb ?
1399 crypto4xx_ce_interrupt_handler_revb :
1400 crypto4xx_ce_interrupt_handler, 0,
1401 KBUILD_MODNAME, dev);
1402 if (rc)
1403 goto err_request_irq;
1404
1405 /* need to setup pdr, rdr, gdr and sdr before this */
1406 crypto4xx_hw_init(core_dev->dev);
1407
1408 /* Register security algorithms with Linux CryptoAPI */
1409 rc = crypto4xx_register_alg(core_dev->dev, crypto4xx_alg,
1410 ARRAY_SIZE(crypto4xx_alg));
1411 if (rc)
1412 goto err_start_dev;
1413
1414 ppc4xx_trng_probe(core_dev);
1415 return 0;
1416
1417 err_start_dev:
1418 free_irq(core_dev->irq, dev);
1419 err_request_irq:
1420 irq_dispose_mapping(core_dev->irq);
1421 iounmap(core_dev->dev->ce_base);
1422 err_iomap:
1423 tasklet_kill(&core_dev->tasklet);
1424 err_build_sdr:
1425 crypto4xx_destroy_sdr(core_dev->dev);
1426 crypto4xx_destroy_gdr(core_dev->dev);
1427 err_build_pdr:
1428 crypto4xx_destroy_pdr(core_dev->dev);
1429 kfree(core_dev->dev);
1430 err_alloc_dev:
1431 kfree(core_dev);
1432
1433 return rc;
1434 }
1435
1436 static int crypto4xx_remove(struct platform_device *ofdev)
1437 {
1438 struct device *dev = &ofdev->dev;
1439 struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
1440
1441 ppc4xx_trng_remove(core_dev);
1442
1443 free_irq(core_dev->irq, dev);
1444 irq_dispose_mapping(core_dev->irq);
1445
1446 tasklet_kill(&core_dev->tasklet);
1447 /* Un-register with Linux CryptoAPI */
1448 crypto4xx_unregister_alg(core_dev->dev);
1449 /* Free all allocated memory */
1450 crypto4xx_stop_all(core_dev);
1451
1452 return 0;
1453 }
1454
1455 static const struct of_device_id crypto4xx_match[] = {
1456 { .compatible = "amcc,ppc4xx-crypto",},
1457 { },
1458 };
1459 MODULE_DEVICE_TABLE(of, crypto4xx_match);
1460
1461 static struct platform_driver crypto4xx_driver = {
1462 .driver = {
1463 .name = KBUILD_MODNAME,
1464 .of_match_table = crypto4xx_match,
1465 },
1466 .probe = crypto4xx_probe,
1467 .remove = crypto4xx_remove,
1468 };
1469
1470 module_platform_driver(crypto4xx_driver);
1471
1472 MODULE_LICENSE("GPL");
1473 MODULE_AUTHOR("James Hsiao <jhsiao@amcc.com>");
1474 MODULE_DESCRIPTION("Driver for AMCC PPC4xx crypto accelerator");
Linux with added FPC-III support