?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / crypto / mxs-dcp.c
blobb0c592073a4a3e99d8b8e1d7188a9ee6101d6009
1 /*
2 * Freescale i.MX23/i.MX28 Data Co-Processor driver
3 *
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14 #include <linux/dma-mapping.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/kthread.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/platform_device.h>
22 #include <linux/stmp_device.h>
23
24 #include <crypto/aes.h>
25 #include <crypto/sha.h>
26 #include <crypto/internal/hash.h>
27 #include <crypto/internal/skcipher.h>
28 #include <crypto/scatterwalk.h>
29
30 #define DCP_MAX_CHANS 4
31 #define DCP_BUF_SZ PAGE_SIZE
32 #define DCP_SHA_PAY_SZ 64
33
34 #define DCP_ALIGNMENT 64
35
36 /*
37 * Null hashes to align with hw behavior on imx6sl and ull
38 * these are flipped for consistency with hw output
39 */
40 static const uint8_t sha1_null_hash[] =
41 "\x09\x07\xd8\xaf\x90\x18\x60\x95\xef\xbf"
42 "\x55\x32\x0d\x4b\x6b\x5e\xee\xa3\x39\xda";
43
44 static const uint8_t sha256_null_hash[] =
45 "\x55\xb8\x52\x78\x1b\x99\x95\xa4"
46 "\x4c\x93\x9b\x64\xe4\x41\xae\x27"
47 "\x24\xb9\x6f\x99\xc8\xf4\xfb\x9a"
48 "\x14\x1c\xfc\x98\x42\xc4\xb0\xe3";
49
50 /* DCP DMA descriptor. */
51 struct dcp_dma_desc {
52 uint32_t next_cmd_addr;
53 uint32_t control0;
54 uint32_t control1;
55 uint32_t source;
56 uint32_t destination;
57 uint32_t size;
58 uint32_t payload;
59 uint32_t status;
60 };
61
62 /* Coherent aligned block for bounce buffering. */
63 struct dcp_coherent_block {
64 uint8_t aes_in_buf[DCP_BUF_SZ];
65 uint8_t aes_out_buf[DCP_BUF_SZ];
66 uint8_t sha_in_buf[DCP_BUF_SZ];
67 uint8_t sha_out_buf[DCP_SHA_PAY_SZ];
68
69 uint8_t aes_key[2 * AES_KEYSIZE_128];
70
71 struct dcp_dma_desc desc[DCP_MAX_CHANS];
72 };
73
74 struct dcp {
75 struct device *dev;
76 void __iomem *base;
77
78 uint32_t caps;
79
80 struct dcp_coherent_block *coh;
81
82 struct completion completion[DCP_MAX_CHANS];
83 spinlock_t lock[DCP_MAX_CHANS];
84 struct task_struct *thread[DCP_MAX_CHANS];
85 struct crypto_queue queue[DCP_MAX_CHANS];
86 };
87
88 enum dcp_chan {
89 DCP_CHAN_HASH_SHA = 0,
90 DCP_CHAN_CRYPTO = 2,
91 };
92
93 struct dcp_async_ctx {
94 /* Common context */
95 enum dcp_chan chan;
96 uint32_t fill;
97
98 /* SHA Hash-specific context */
99 struct mutex mutex;
100 uint32_t alg;
101 unsigned int hot:1;
102
103 /* Crypto-specific context */
104 struct crypto_skcipher *fallback;
105 unsigned int key_len;
106 uint8_t key[AES_KEYSIZE_128];
107 };
108
109 struct dcp_aes_req_ctx {
110 unsigned int enc:1;
111 unsigned int ecb:1;
112 };
113
114 struct dcp_sha_req_ctx {
115 unsigned int init:1;
116 unsigned int fini:1;
117 };
118
119 /*
120 * There can even be only one instance of the MXS DCP due to the
121 * design of Linux Crypto API.
122 */
123 static struct dcp *global_sdcp;
124
125 /* DCP register layout. */
126 #define MXS_DCP_CTRL 0x00
127 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
128 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
129
130 #define MXS_DCP_STAT 0x10
131 #define MXS_DCP_STAT_CLR 0x18
132 #define MXS_DCP_STAT_IRQ_MASK 0xf
133
134 #define MXS_DCP_CHANNELCTRL 0x20
135 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
136
137 #define MXS_DCP_CAPABILITY1 0x40
138 #define MXS_DCP_CAPABILITY1_SHA256 (4 << 16)
139 #define MXS_DCP_CAPABILITY1_SHA1 (1 << 16)
140 #define MXS_DCP_CAPABILITY1_AES128 (1 << 0)
141
142 #define MXS_DCP_CONTEXT 0x50
143
144 #define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40))
145
146 #define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40))
147
148 #define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40))
149 #define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40))
150
151 /* DMA descriptor bits. */
152 #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13)
153 #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12)
154 #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11)
155 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8)
156 #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9)
157 #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6)
158 #define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5)
159 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1)
160 #define MXS_DCP_CONTROL0_INTERRUPT (1 << 0)
161
162 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16)
163 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16)
164 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4)
165 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4)
166 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0)
167
168 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
169 {
170 struct dcp *sdcp = global_sdcp;
171 const int chan = actx->chan;
172 uint32_t stat;
173 unsigned long ret;
174 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
175
176 dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
177 DMA_TO_DEVICE);
178
179 reinit_completion(&sdcp->completion[chan]);
180
181 /* Clear status register. */
182 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
183
184 /* Load the DMA descriptor. */
185 writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
186
187 /* Increment the semaphore to start the DMA transfer. */
188 writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
189
190 ret = wait_for_completion_timeout(&sdcp->completion[chan],
191 msecs_to_jiffies(1000));
192 if (!ret) {
193 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
194 chan, readl(sdcp->base + MXS_DCP_STAT));
195 return -ETIMEDOUT;
196 }
197
198 stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
199 if (stat & 0xff) {
200 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
201 chan, stat);
202 return -EINVAL;
203 }
204
205 dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
206
207 return 0;
208 }
209
210 /*
211 * Encryption (AES128)
212 */
213 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
214 struct ablkcipher_request *req, int init)
215 {
216 struct dcp *sdcp = global_sdcp;
217 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
218 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
219 int ret;
220
221 dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
222 2 * AES_KEYSIZE_128,
223 DMA_TO_DEVICE);
224 dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
225 DCP_BUF_SZ, DMA_TO_DEVICE);
226 dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
227 DCP_BUF_SZ, DMA_FROM_DEVICE);
228
229 if (actx->fill % AES_BLOCK_SIZE) {
230 dev_err(sdcp->dev, "Invalid block size!\n");
231 ret = -EINVAL;
232 goto aes_done_run;
233 }
234
235 /* Fill in the DMA descriptor. */
236 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
237 MXS_DCP_CONTROL0_INTERRUPT |
238 MXS_DCP_CONTROL0_ENABLE_CIPHER;
239
240 /* Payload contains the key. */
241 desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
242
243 if (rctx->enc)
244 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
245 if (init)
246 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
247
248 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
249
250 if (rctx->ecb)
251 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
252 else
253 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
254
255 desc->next_cmd_addr = 0;
256 desc->source = src_phys;
257 desc->destination = dst_phys;
258 desc->size = actx->fill;
259 desc->payload = key_phys;
260 desc->status = 0;
261
262 ret = mxs_dcp_start_dma(actx);
263
264 aes_done_run:
265 dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
266 DMA_TO_DEVICE);
267 dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
268 dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
269
270 return ret;
271 }
272
273 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
274 {
275 struct dcp *sdcp = global_sdcp;
276
277 struct ablkcipher_request *req = ablkcipher_request_cast(arq);
278 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
279 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
280
281 struct scatterlist *dst = req->dst;
282 struct scatterlist *src = req->src;
283 const int nents = sg_nents(req->src);
284
285 const int out_off = DCP_BUF_SZ;
286 uint8_t *in_buf = sdcp->coh->aes_in_buf;
287 uint8_t *out_buf = sdcp->coh->aes_out_buf;
288
289 uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
290 uint32_t dst_off = 0;
291 uint32_t last_out_len = 0;
292
293 uint8_t *key = sdcp->coh->aes_key;
294
295 int ret = 0;
296 int split = 0;
297 unsigned int i, len, clen, rem = 0, tlen = 0;
298 int init = 0;
299 bool limit_hit = false;
300
301 actx->fill = 0;
302
303 /* Copy the key from the temporary location. */
304 memcpy(key, actx->key, actx->key_len);
305
306 if (!rctx->ecb) {
307 /* Copy the CBC IV just past the key. */
308 memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128);
309 /* CBC needs the INIT set. */
310 init = 1;
311 } else {
312 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
313 }
314
315 for_each_sg(req->src, src, nents, i) {
316 src_buf = sg_virt(src);
317 len = sg_dma_len(src);
318 tlen += len;
319 limit_hit = tlen > req->nbytes;
320
321 if (limit_hit)
322 len = req->nbytes - (tlen - len);
323
324 do {
325 if (actx->fill + len > out_off)
326 clen = out_off - actx->fill;
327 else
328 clen = len;
329
330 memcpy(in_buf + actx->fill, src_buf, clen);
331 len -= clen;
332 src_buf += clen;
333 actx->fill += clen;
334
335 /*
336 * If we filled the buffer or this is the last SG,
337 * submit the buffer.
338 */
339 if (actx->fill == out_off || sg_is_last(src) ||
340 limit_hit) {
341 ret = mxs_dcp_run_aes(actx, req, init);
342 if (ret)
343 return ret;
344 init = 0;
345
346 out_tmp = out_buf;
347 last_out_len = actx->fill;
348 while (dst && actx->fill) {
349 if (!split) {
350 dst_buf = sg_virt(dst);
351 dst_off = 0;
352 }
353 rem = min(sg_dma_len(dst) - dst_off,
354 actx->fill);
355
356 memcpy(dst_buf + dst_off, out_tmp, rem);
357 out_tmp += rem;
358 dst_off += rem;
359 actx->fill -= rem;
360
361 if (dst_off == sg_dma_len(dst)) {
362 dst = sg_next(dst);
363 split = 0;
364 } else {
365 split = 1;
366 }
367 }
368 }
369 } while (len);
370
371 if (limit_hit)
372 break;
373 }
374
375 /* Copy the IV for CBC for chaining */
376 if (!rctx->ecb) {
377 if (rctx->enc)
378 memcpy(req->info, out_buf+(last_out_len-AES_BLOCK_SIZE),
379 AES_BLOCK_SIZE);
380 else
381 memcpy(req->info, in_buf+(last_out_len-AES_BLOCK_SIZE),
382 AES_BLOCK_SIZE);
383 }
384
385 return ret;
386 }
387
388 static int dcp_chan_thread_aes(void *data)
389 {
390 struct dcp *sdcp = global_sdcp;
391 const int chan = DCP_CHAN_CRYPTO;
392
393 struct crypto_async_request *backlog;
394 struct crypto_async_request *arq;
395
396 int ret;
397
398 while (!kthread_should_stop()) {
399 set_current_state(TASK_INTERRUPTIBLE);
400
401 spin_lock(&sdcp->lock[chan]);
402 backlog = crypto_get_backlog(&sdcp->queue[chan]);
403 arq = crypto_dequeue_request(&sdcp->queue[chan]);
404 spin_unlock(&sdcp->lock[chan]);
405
406 if (!backlog && !arq) {
407 schedule();
408 continue;
409 }
410
411 set_current_state(TASK_RUNNING);
412
413 if (backlog)
414 backlog->complete(backlog, -EINPROGRESS);
415
416 if (arq) {
417 ret = mxs_dcp_aes_block_crypt(arq);
418 arq->complete(arq, ret);
419 }
420 }
421
422 return 0;
423 }
424
425 static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc)
426 {
427 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
428 struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(tfm);
429 SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
430 int ret;
431
432 skcipher_request_set_tfm(subreq, ctx->fallback);
433 skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL);
434 skcipher_request_set_crypt(subreq, req->src, req->dst,
435 req->nbytes, req->info);
436
437 if (enc)
438 ret = crypto_skcipher_encrypt(subreq);
439 else
440 ret = crypto_skcipher_decrypt(subreq);
441
442 skcipher_request_zero(subreq);
443
444 return ret;
445 }
446
447 static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb)
448 {
449 struct dcp *sdcp = global_sdcp;
450 struct crypto_async_request *arq = &req->base;
451 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
452 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
453 int ret;
454
455 if (unlikely(actx->key_len != AES_KEYSIZE_128))
456 return mxs_dcp_block_fallback(req, enc);
457
458 rctx->enc = enc;
459 rctx->ecb = ecb;
460 actx->chan = DCP_CHAN_CRYPTO;
461
462 spin_lock(&sdcp->lock[actx->chan]);
463 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
464 spin_unlock(&sdcp->lock[actx->chan]);
465
466 wake_up_process(sdcp->thread[actx->chan]);
467
468 return -EINPROGRESS;
469 }
470
471 static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req)
472 {
473 return mxs_dcp_aes_enqueue(req, 0, 1);
474 }
475
476 static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req)
477 {
478 return mxs_dcp_aes_enqueue(req, 1, 1);
479 }
480
481 static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
482 {
483 return mxs_dcp_aes_enqueue(req, 0, 0);
484 }
485
486 static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
487 {
488 return mxs_dcp_aes_enqueue(req, 1, 0);
489 }
490
491 static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
492 unsigned int len)
493 {
494 struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm);
495 unsigned int ret;
496
497 /*
498 * AES 128 is supposed by the hardware, store key into temporary
499 * buffer and exit. We must use the temporary buffer here, since
500 * there can still be an operation in progress.
501 */
502 actx->key_len = len;
503 if (len == AES_KEYSIZE_128) {
504 memcpy(actx->key, key, len);
505 return 0;
506 }
507
508 /*
509 * If the requested AES key size is not supported by the hardware,
510 * but is supported by in-kernel software implementation, we use
511 * software fallback.
512 */
513 crypto_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK);
514 crypto_skcipher_set_flags(actx->fallback,
515 tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
516
517 ret = crypto_skcipher_setkey(actx->fallback, key, len);
518 if (!ret)
519 return 0;
520
521 tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
522 tfm->base.crt_flags |= crypto_skcipher_get_flags(actx->fallback) &
523 CRYPTO_TFM_RES_MASK;
524
525 return ret;
526 }
527
528 static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
529 {
530 const char *name = crypto_tfm_alg_name(tfm);
531 const uint32_t flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK;
532 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
533 struct crypto_skcipher *blk;
534
535 blk = crypto_alloc_skcipher(name, 0, flags);
536 if (IS_ERR(blk))
537 return PTR_ERR(blk);
538
539 actx->fallback = blk;
540 tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx);
541 return 0;
542 }
543
544 static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm)
545 {
546 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
547
548 crypto_free_skcipher(actx->fallback);
549 }
550
551 /*
552 * Hashing (SHA1/SHA256)
553 */
554 static int mxs_dcp_run_sha(struct ahash_request *req)
555 {
556 struct dcp *sdcp = global_sdcp;
557 int ret;
558
559 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
560 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
561 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
562 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
563
564 dma_addr_t digest_phys = 0;
565 dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
566 DCP_BUF_SZ, DMA_TO_DEVICE);
567
568 /* Fill in the DMA descriptor. */
569 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
570 MXS_DCP_CONTROL0_INTERRUPT |
571 MXS_DCP_CONTROL0_ENABLE_HASH;
572 if (rctx->init)
573 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
574
575 desc->control1 = actx->alg;
576 desc->next_cmd_addr = 0;
577 desc->source = buf_phys;
578 desc->destination = 0;
579 desc->size = actx->fill;
580 desc->payload = 0;
581 desc->status = 0;
582
583 /*
584 * Align driver with hw behavior when generating null hashes
585 */
586 if (rctx->init && rctx->fini && desc->size == 0) {
587 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
588 const uint8_t *sha_buf =
589 (actx->alg == MXS_DCP_CONTROL1_HASH_SELECT_SHA1) ?
590 sha1_null_hash : sha256_null_hash;
591 memcpy(sdcp->coh->sha_out_buf, sha_buf, halg->digestsize);
592 ret = 0;
593 goto done_run;
594 }
595
596 /* Set HASH_TERM bit for last transfer block. */
597 if (rctx->fini) {
598 digest_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_out_buf,
599 DCP_SHA_PAY_SZ, DMA_FROM_DEVICE);
600 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
601 desc->payload = digest_phys;
602 }
603
604 ret = mxs_dcp_start_dma(actx);
605
606 if (rctx->fini)
607 dma_unmap_single(sdcp->dev, digest_phys, DCP_SHA_PAY_SZ,
608 DMA_FROM_DEVICE);
609
610 done_run:
611 dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
612
613 return ret;
614 }
615
616 static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
617 {
618 struct dcp *sdcp = global_sdcp;
619
620 struct ahash_request *req = ahash_request_cast(arq);
621 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
622 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
623 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
624 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
625
626 uint8_t *in_buf = sdcp->coh->sha_in_buf;
627 uint8_t *out_buf = sdcp->coh->sha_out_buf;
628
629 struct scatterlist *src;
630
631 unsigned int i, len, clen, oft = 0;
632 int ret;
633
634 int fin = rctx->fini;
635 if (fin)
636 rctx->fini = 0;
637
638 src = req->src;
639 len = req->nbytes;
640
641 while (len) {
642 if (actx->fill + len > DCP_BUF_SZ)
643 clen = DCP_BUF_SZ - actx->fill;
644 else
645 clen = len;
646
647 scatterwalk_map_and_copy(in_buf + actx->fill, src, oft, clen,
648 0);
649
650 len -= clen;
651 oft += clen;
652 actx->fill += clen;
653
654 /*
655 * If we filled the buffer and still have some
656 * more data, submit the buffer.
657 */
658 if (len && actx->fill == DCP_BUF_SZ) {
659 ret = mxs_dcp_run_sha(req);
660 if (ret)
661 return ret;
662 actx->fill = 0;
663 rctx->init = 0;
664 }
665 }
666
667 if (fin) {
668 rctx->fini = 1;
669
670 /* Submit whatever is left. */
671 if (!req->result)
672 return -EINVAL;
673
674 ret = mxs_dcp_run_sha(req);
675 if (ret)
676 return ret;
677
678 actx->fill = 0;
679
680 /* For some reason the result is flipped */
681 for (i = 0; i < halg->digestsize; i++)
682 req->result[i] = out_buf[halg->digestsize - i - 1];
683 }
684
685 return 0;
686 }
687
688 static int dcp_chan_thread_sha(void *data)
689 {
690 struct dcp *sdcp = global_sdcp;
691 const int chan = DCP_CHAN_HASH_SHA;
692
693 struct crypto_async_request *backlog;
694 struct crypto_async_request *arq;
695
696 struct dcp_sha_req_ctx *rctx;
697
698 struct ahash_request *req;
699 int ret, fini;
700
701 while (!kthread_should_stop()) {
702 set_current_state(TASK_INTERRUPTIBLE);
703
704 spin_lock(&sdcp->lock[chan]);
705 backlog = crypto_get_backlog(&sdcp->queue[chan]);
706 arq = crypto_dequeue_request(&sdcp->queue[chan]);
707 spin_unlock(&sdcp->lock[chan]);
708
709 if (!backlog && !arq) {
710 schedule();
711 continue;
712 }
713
714 set_current_state(TASK_RUNNING);
715
716 if (backlog)
717 backlog->complete(backlog, -EINPROGRESS);
718
719 if (arq) {
720 req = ahash_request_cast(arq);
721 rctx = ahash_request_ctx(req);
722
723 ret = dcp_sha_req_to_buf(arq);
724 fini = rctx->fini;
725 arq->complete(arq, ret);
726 }
727 }
728
729 return 0;
730 }
731
732 static int dcp_sha_init(struct ahash_request *req)
733 {
734 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
735 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
736
737 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
738
739 /*
740 * Start hashing session. The code below only inits the
741 * hashing session context, nothing more.
742 */
743 memset(actx, 0, sizeof(*actx));
744
745 if (strcmp(halg->base.cra_name, "sha1") == 0)
746 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
747 else
748 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
749
750 actx->fill = 0;
751 actx->hot = 0;
752 actx->chan = DCP_CHAN_HASH_SHA;
753
754 mutex_init(&actx->mutex);
755
756 return 0;
757 }
758
759 static int dcp_sha_update_fx(struct ahash_request *req, int fini)
760 {
761 struct dcp *sdcp = global_sdcp;
762
763 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
764 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
765 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
766
767 int ret;
768
769 /*
770 * Ignore requests that have no data in them and are not
771 * the trailing requests in the stream of requests.
772 */
773 if (!req->nbytes && !fini)
774 return 0;
775
776 mutex_lock(&actx->mutex);
777
778 rctx->fini = fini;
779
780 if (!actx->hot) {
781 actx->hot = 1;
782 rctx->init = 1;
783 }
784
785 spin_lock(&sdcp->lock[actx->chan]);
786 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
787 spin_unlock(&sdcp->lock[actx->chan]);
788
789 wake_up_process(sdcp->thread[actx->chan]);
790 mutex_unlock(&actx->mutex);
791
792 return -EINPROGRESS;
793 }
794
795 static int dcp_sha_update(struct ahash_request *req)
796 {
797 return dcp_sha_update_fx(req, 0);
798 }
799
800 static int dcp_sha_final(struct ahash_request *req)
801 {
802 ahash_request_set_crypt(req, NULL, req->result, 0);
803 req->nbytes = 0;
804 return dcp_sha_update_fx(req, 1);
805 }
806
807 static int dcp_sha_finup(struct ahash_request *req)
808 {
809 return dcp_sha_update_fx(req, 1);
810 }
811
812 static int dcp_sha_digest(struct ahash_request *req)
813 {
814 int ret;
815
816 ret = dcp_sha_init(req);
817 if (ret)
818 return ret;
819
820 return dcp_sha_finup(req);
821 }
822
823 static int dcp_sha_noimport(struct ahash_request *req, const void *in)
824 {
825 return -ENOSYS;
826 }
827
828 static int dcp_sha_noexport(struct ahash_request *req, void *out)
829 {
830 return -ENOSYS;
831 }
832
833 static int dcp_sha_cra_init(struct crypto_tfm *tfm)
834 {
835 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
836 sizeof(struct dcp_sha_req_ctx));
837 return 0;
838 }
839
840 static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
841 {
842 }
843
844 /* AES 128 ECB and AES 128 CBC */
845 static struct crypto_alg dcp_aes_algs[] = {
846 {
847 .cra_name = "ecb(aes)",
848 .cra_driver_name = "ecb-aes-dcp",
849 .cra_priority = 400,
850 .cra_alignmask = 15,
851 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
852 CRYPTO_ALG_ASYNC |
853 CRYPTO_ALG_NEED_FALLBACK,
854 .cra_init = mxs_dcp_aes_fallback_init,
855 .cra_exit = mxs_dcp_aes_fallback_exit,
856 .cra_blocksize = AES_BLOCK_SIZE,
857 .cra_ctxsize = sizeof(struct dcp_async_ctx),
858 .cra_type = &crypto_ablkcipher_type,
859 .cra_module = THIS_MODULE,
860 .cra_u = {
861 .ablkcipher = {
862 .min_keysize = AES_MIN_KEY_SIZE,
863 .max_keysize = AES_MAX_KEY_SIZE,
864 .setkey = mxs_dcp_aes_setkey,
865 .encrypt = mxs_dcp_aes_ecb_encrypt,
866 .decrypt = mxs_dcp_aes_ecb_decrypt
867 },
868 },
869 }, {
870 .cra_name = "cbc(aes)",
871 .cra_driver_name = "cbc-aes-dcp",
872 .cra_priority = 400,
873 .cra_alignmask = 15,
874 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
875 CRYPTO_ALG_ASYNC |
876 CRYPTO_ALG_NEED_FALLBACK,
877 .cra_init = mxs_dcp_aes_fallback_init,
878 .cra_exit = mxs_dcp_aes_fallback_exit,
879 .cra_blocksize = AES_BLOCK_SIZE,
880 .cra_ctxsize = sizeof(struct dcp_async_ctx),
881 .cra_type = &crypto_ablkcipher_type,
882 .cra_module = THIS_MODULE,
883 .cra_u = {
884 .ablkcipher = {
885 .min_keysize = AES_MIN_KEY_SIZE,
886 .max_keysize = AES_MAX_KEY_SIZE,
887 .setkey = mxs_dcp_aes_setkey,
888 .encrypt = mxs_dcp_aes_cbc_encrypt,
889 .decrypt = mxs_dcp_aes_cbc_decrypt,
890 .ivsize = AES_BLOCK_SIZE,
891 },
892 },
893 },
894 };
895
896 /* SHA1 */
897 static struct ahash_alg dcp_sha1_alg = {
898 .init = dcp_sha_init,
899 .update = dcp_sha_update,
900 .final = dcp_sha_final,
901 .finup = dcp_sha_finup,
902 .digest = dcp_sha_digest,
903 .import = dcp_sha_noimport,
904 .export = dcp_sha_noexport,
905 .halg = {
906 .digestsize = SHA1_DIGEST_SIZE,
907 .base = {
908 .cra_name = "sha1",
909 .cra_driver_name = "sha1-dcp",
910 .cra_priority = 400,
911 .cra_alignmask = 63,
912 .cra_flags = CRYPTO_ALG_ASYNC,
913 .cra_blocksize = SHA1_BLOCK_SIZE,
914 .cra_ctxsize = sizeof(struct dcp_async_ctx),
915 .cra_module = THIS_MODULE,
916 .cra_init = dcp_sha_cra_init,
917 .cra_exit = dcp_sha_cra_exit,
918 },
919 },
920 };
921
922 /* SHA256 */
923 static struct ahash_alg dcp_sha256_alg = {
924 .init = dcp_sha_init,
925 .update = dcp_sha_update,
926 .final = dcp_sha_final,
927 .finup = dcp_sha_finup,
928 .digest = dcp_sha_digest,
929 .import = dcp_sha_noimport,
930 .export = dcp_sha_noexport,
931 .halg = {
932 .digestsize = SHA256_DIGEST_SIZE,
933 .base = {
934 .cra_name = "sha256",
935 .cra_driver_name = "sha256-dcp",
936 .cra_priority = 400,
937 .cra_alignmask = 63,
938 .cra_flags = CRYPTO_ALG_ASYNC,
939 .cra_blocksize = SHA256_BLOCK_SIZE,
940 .cra_ctxsize = sizeof(struct dcp_async_ctx),
941 .cra_module = THIS_MODULE,
942 .cra_init = dcp_sha_cra_init,
943 .cra_exit = dcp_sha_cra_exit,
944 },
945 },
946 };
947
948 static irqreturn_t mxs_dcp_irq(int irq, void *context)
949 {
950 struct dcp *sdcp = context;
951 uint32_t stat;
952 int i;
953
954 stat = readl(sdcp->base + MXS_DCP_STAT);
955 stat &= MXS_DCP_STAT_IRQ_MASK;
956 if (!stat)
957 return IRQ_NONE;
958
959 /* Clear the interrupts. */
960 writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
961
962 /* Complete the DMA requests that finished. */
963 for (i = 0; i < DCP_MAX_CHANS; i++)
964 if (stat & (1 << i))
965 complete(&sdcp->completion[i]);
966
967 return IRQ_HANDLED;
968 }
969
970 static int mxs_dcp_probe(struct platform_device *pdev)
971 {
972 struct device *dev = &pdev->dev;
973 struct dcp *sdcp = NULL;
974 int i, ret;
975
976 struct resource *iores;
977 int dcp_vmi_irq, dcp_irq;
978
979 if (global_sdcp) {
980 dev_err(dev, "Only one DCP instance allowed!\n");
981 return -ENODEV;
982 }
983
984 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
985 dcp_vmi_irq = platform_get_irq(pdev, 0);
986 if (dcp_vmi_irq < 0) {
987 dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_vmi_irq);
988 return dcp_vmi_irq;
989 }
990
991 dcp_irq = platform_get_irq(pdev, 1);
992 if (dcp_irq < 0) {
993 dev_err(dev, "Failed to get IRQ: (%d)!\n", dcp_irq);
994 return dcp_irq;
995 }
996
997 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
998 if (!sdcp)
999 return -ENOMEM;
1000
1001 sdcp->dev = dev;
1002 sdcp->base = devm_ioremap_resource(dev, iores);
1003 if (IS_ERR(sdcp->base))
1004 return PTR_ERR(sdcp->base);
1005
1006
1007 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
1008 "dcp-vmi-irq", sdcp);
1009 if (ret) {
1010 dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
1011 return ret;
1012 }
1013
1014 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
1015 "dcp-irq", sdcp);
1016 if (ret) {
1017 dev_err(dev, "Failed to claim DCP IRQ!\n");
1018 return ret;
1019 }
1020
1021 /* Allocate coherent helper block. */
1022 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
1023 GFP_KERNEL);
1024 if (!sdcp->coh)
1025 return -ENOMEM;
1026
1027 /* Re-align the structure so it fits the DCP constraints. */
1028 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
1029
1030 /* Restart the DCP block. */
1031 ret = stmp_reset_block(sdcp->base);
1032 if (ret)
1033 return ret;
1034
1035 /* Initialize control register. */
1036 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
1037 MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
1038 sdcp->base + MXS_DCP_CTRL);
1039
1040 /* Enable all DCP DMA channels. */
1041 writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
1042 sdcp->base + MXS_DCP_CHANNELCTRL);
1043
1044 /*
1045 * We do not enable context switching. Give the context buffer a
1046 * pointer to an illegal address so if context switching is
1047 * inadvertantly enabled, the DCP will return an error instead of
1048 * trashing good memory. The DCP DMA cannot access ROM, so any ROM
1049 * address will do.
1050 */
1051 writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
1052 for (i = 0; i < DCP_MAX_CHANS; i++)
1053 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
1054 writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
1055
1056 global_sdcp = sdcp;
1057
1058 platform_set_drvdata(pdev, sdcp);
1059
1060 for (i = 0; i < DCP_MAX_CHANS; i++) {
1061 spin_lock_init(&sdcp->lock[i]);
1062 init_completion(&sdcp->completion[i]);
1063 crypto_init_queue(&sdcp->queue[i], 50);
1064 }
1065
1066 /* Create the SHA and AES handler threads. */
1067 sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
1068 NULL, "mxs_dcp_chan/sha");
1069 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1070 dev_err(dev, "Error starting SHA thread!\n");
1071 return PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
1072 }
1073
1074 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
1075 NULL, "mxs_dcp_chan/aes");
1076 if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
1077 dev_err(dev, "Error starting SHA thread!\n");
1078 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1079 goto err_destroy_sha_thread;
1080 }
1081
1082 /* Register the various crypto algorithms. */
1083 sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1084
1085 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1086 ret = crypto_register_algs(dcp_aes_algs,
1087 ARRAY_SIZE(dcp_aes_algs));
1088 if (ret) {
1089 /* Failed to register algorithm. */
1090 dev_err(dev, "Failed to register AES crypto!\n");
1091 goto err_destroy_aes_thread;
1092 }
1093 }
1094
1095 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1096 ret = crypto_register_ahash(&dcp_sha1_alg);
1097 if (ret) {
1098 dev_err(dev, "Failed to register %s hash!\n",
1099 dcp_sha1_alg.halg.base.cra_name);
1100 goto err_unregister_aes;
1101 }
1102 }
1103
1104 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1105 ret = crypto_register_ahash(&dcp_sha256_alg);
1106 if (ret) {
1107 dev_err(dev, "Failed to register %s hash!\n",
1108 dcp_sha256_alg.halg.base.cra_name);
1109 goto err_unregister_sha1;
1110 }
1111 }
1112
1113 return 0;
1114
1115 err_unregister_sha1:
1116 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1117 crypto_unregister_ahash(&dcp_sha1_alg);
1118
1119 err_unregister_aes:
1120 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1121 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1122
1123 err_destroy_aes_thread:
1124 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1125
1126 err_destroy_sha_thread:
1127 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1128 return ret;
1129 }
1130
1131 static int mxs_dcp_remove(struct platform_device *pdev)
1132 {
1133 struct dcp *sdcp = platform_get_drvdata(pdev);
1134
1135 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1136 crypto_unregister_ahash(&dcp_sha256_alg);
1137
1138 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1139 crypto_unregister_ahash(&dcp_sha1_alg);
1140
1141 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1142 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1143
1144 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1145 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1146
1147 platform_set_drvdata(pdev, NULL);
1148
1149 global_sdcp = NULL;
1150
1151 return 0;
1152 }
1153
1154 static const struct of_device_id mxs_dcp_dt_ids[] = {
1155 { .compatible = "fsl,imx23-dcp", .data = NULL, },
1156 { .compatible = "fsl,imx28-dcp", .data = NULL, },
1157 { /* sentinel */ }
1158 };
1159
1160 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1161
1162 static struct platform_driver mxs_dcp_driver = {
1163 .probe = mxs_dcp_probe,
1164 .remove = mxs_dcp_remove,
1165 .driver = {
1166 .name = "mxs-dcp",
1167 .of_match_table = mxs_dcp_dt_ids,
1168 },
1169 };
1170
1171 module_platform_driver(mxs_dcp_driver);
1172
1173 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1174 MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1175 MODULE_LICENSE("GPL");
1176 MODULE_ALIAS("platform:mxs-dcp");
Linux with added FPC-III support