?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / crypto / omap-sham.c
blob2faaa4069cdd861af637d58240c623c3c1af4361
1 /*
2 * Cryptographic API.
3 *
4 * Support for OMAP SHA1/MD5 HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 * Some ideas are from old omap-sha1-md5.c driver.
15 */
16
17 #define pr_fmt(fmt) "%s: " fmt, __func__
18
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
27 #include <linux/io.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/delay.h>
38 #include <linux/crypto.h>
39 #include <linux/cryptohash.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/algapi.h>
42 #include <crypto/sha.h>
43 #include <crypto/hash.h>
44 #include <crypto/hmac.h>
45 #include <crypto/internal/hash.h>
46
47 #define MD5_DIGEST_SIZE 16
48
49 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
50 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
51 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
52
53 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
54
55 #define SHA_REG_CTRL 0x18
56 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
57 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
58 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
59 #define SHA_REG_CTRL_ALGO (1 << 2)
60 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
61 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
62
63 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
64
65 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66 #define SHA_REG_MASK_DMA_EN (1 << 3)
67 #define SHA_REG_MASK_IT_EN (1 << 2)
68 #define SHA_REG_MASK_SOFTRESET (1 << 1)
69 #define SHA_REG_AUTOIDLE (1 << 0)
70
71 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
72 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
73
74 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
75 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
76 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
77 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
78 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
79
80 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
81 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
82 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
85 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
86 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
87
88 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
89
90 #define SHA_REG_IRQSTATUS 0x118
91 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
93 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
95
96 #define SHA_REG_IRQENA 0x11C
97 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
98 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
99 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
100 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
101
102 #define DEFAULT_TIMEOUT_INTERVAL HZ
103
104 #define DEFAULT_AUTOSUSPEND_DELAY 1000
105
106 /* mostly device flags */
107 #define FLAGS_BUSY 0
108 #define FLAGS_FINAL 1
109 #define FLAGS_DMA_ACTIVE 2
110 #define FLAGS_OUTPUT_READY 3
111 #define FLAGS_INIT 4
112 #define FLAGS_CPU 5
113 #define FLAGS_DMA_READY 6
114 #define FLAGS_AUTO_XOR 7
115 #define FLAGS_BE32_SHA1 8
116 #define FLAGS_SGS_COPIED 9
117 #define FLAGS_SGS_ALLOCED 10
118 /* context flags */
119 #define FLAGS_FINUP 16
120
121 #define FLAGS_MODE_SHIFT 18
122 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
127 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
128 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
129
130 #define FLAGS_HMAC 21
131 #define FLAGS_ERROR 22
132
133 #define OP_UPDATE 1
134 #define OP_FINAL 2
135
136 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
137 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
138
139 #define BUFLEN SHA512_BLOCK_SIZE
140 #define OMAP_SHA_DMA_THRESHOLD 256
141
142 struct omap_sham_dev;
143
144 struct omap_sham_reqctx {
145 struct omap_sham_dev *dd;
146 unsigned long flags;
147 unsigned long op;
148
149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
150 size_t digcnt;
151 size_t bufcnt;
152 size_t buflen;
153
154 /* walk state */
155 struct scatterlist *sg;
156 struct scatterlist sgl[2];
157 int offset; /* offset in current sg */
158 int sg_len;
159 unsigned int total; /* total request */
160
161 u8 buffer[0] OMAP_ALIGNED;
162 };
163
164 struct omap_sham_hmac_ctx {
165 struct crypto_shash *shash;
166 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
167 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
168 };
169
170 struct omap_sham_ctx {
171 unsigned long flags;
172
173 /* fallback stuff */
174 struct crypto_shash *fallback;
175
176 struct omap_sham_hmac_ctx base[0];
177 };
178
179 #define OMAP_SHAM_QUEUE_LENGTH 10
180
181 struct omap_sham_algs_info {
182 struct ahash_alg *algs_list;
183 unsigned int size;
184 unsigned int registered;
185 };
186
187 struct omap_sham_pdata {
188 struct omap_sham_algs_info *algs_info;
189 unsigned int algs_info_size;
190 unsigned long flags;
191 int digest_size;
192
193 void (*copy_hash)(struct ahash_request *req, int out);
194 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
195 int final, int dma);
196 void (*trigger)(struct omap_sham_dev *dd, size_t length);
197 int (*poll_irq)(struct omap_sham_dev *dd);
198 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
199
200 u32 odigest_ofs;
201 u32 idigest_ofs;
202 u32 din_ofs;
203 u32 digcnt_ofs;
204 u32 rev_ofs;
205 u32 mask_ofs;
206 u32 sysstatus_ofs;
207 u32 mode_ofs;
208 u32 length_ofs;
209
210 u32 major_mask;
211 u32 major_shift;
212 u32 minor_mask;
213 u32 minor_shift;
214 };
215
216 struct omap_sham_dev {
217 struct list_head list;
218 unsigned long phys_base;
219 struct device *dev;
220 void __iomem *io_base;
221 int irq;
222 spinlock_t lock;
223 int err;
224 struct dma_chan *dma_lch;
225 struct tasklet_struct done_task;
226 u8 polling_mode;
227 u8 xmit_buf[BUFLEN] OMAP_ALIGNED;
228
229 unsigned long flags;
230 int fallback_sz;
231 struct crypto_queue queue;
232 struct ahash_request *req;
233
234 const struct omap_sham_pdata *pdata;
235 };
236
237 struct omap_sham_drv {
238 struct list_head dev_list;
239 spinlock_t lock;
240 unsigned long flags;
241 };
242
243 static struct omap_sham_drv sham = {
244 .dev_list = LIST_HEAD_INIT(sham.dev_list),
245 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
246 };
247
248 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
249 {
250 return __raw_readl(dd->io_base + offset);
251 }
252
253 static inline void omap_sham_write(struct omap_sham_dev *dd,
254 u32 offset, u32 value)
255 {
256 __raw_writel(value, dd->io_base + offset);
257 }
258
259 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
260 u32 value, u32 mask)
261 {
262 u32 val;
263
264 val = omap_sham_read(dd, address);
265 val &= ~mask;
266 val |= value;
267 omap_sham_write(dd, address, val);
268 }
269
270 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
271 {
272 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
273
274 while (!(omap_sham_read(dd, offset) & bit)) {
275 if (time_is_before_jiffies(timeout))
276 return -ETIMEDOUT;
277 }
278
279 return 0;
280 }
281
282 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
283 {
284 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
285 struct omap_sham_dev *dd = ctx->dd;
286 u32 *hash = (u32 *)ctx->digest;
287 int i;
288
289 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
290 if (out)
291 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
292 else
293 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
294 }
295 }
296
297 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
298 {
299 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
300 struct omap_sham_dev *dd = ctx->dd;
301 int i;
302
303 if (ctx->flags & BIT(FLAGS_HMAC)) {
304 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
305 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
306 struct omap_sham_hmac_ctx *bctx = tctx->base;
307 u32 *opad = (u32 *)bctx->opad;
308
309 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
310 if (out)
311 opad[i] = omap_sham_read(dd,
312 SHA_REG_ODIGEST(dd, i));
313 else
314 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
315 opad[i]);
316 }
317 }
318
319 omap_sham_copy_hash_omap2(req, out);
320 }
321
322 static void omap_sham_copy_ready_hash(struct ahash_request *req)
323 {
324 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
325 u32 *in = (u32 *)ctx->digest;
326 u32 *hash = (u32 *)req->result;
327 int i, d, big_endian = 0;
328
329 if (!hash)
330 return;
331
332 switch (ctx->flags & FLAGS_MODE_MASK) {
333 case FLAGS_MODE_MD5:
334 d = MD5_DIGEST_SIZE / sizeof(u32);
335 break;
336 case FLAGS_MODE_SHA1:
337 /* OMAP2 SHA1 is big endian */
338 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
339 big_endian = 1;
340 d = SHA1_DIGEST_SIZE / sizeof(u32);
341 break;
342 case FLAGS_MODE_SHA224:
343 d = SHA224_DIGEST_SIZE / sizeof(u32);
344 break;
345 case FLAGS_MODE_SHA256:
346 d = SHA256_DIGEST_SIZE / sizeof(u32);
347 break;
348 case FLAGS_MODE_SHA384:
349 d = SHA384_DIGEST_SIZE / sizeof(u32);
350 break;
351 case FLAGS_MODE_SHA512:
352 d = SHA512_DIGEST_SIZE / sizeof(u32);
353 break;
354 default:
355 d = 0;
356 }
357
358 if (big_endian)
359 for (i = 0; i < d; i++)
360 hash[i] = be32_to_cpu(in[i]);
361 else
362 for (i = 0; i < d; i++)
363 hash[i] = le32_to_cpu(in[i]);
364 }
365
366 static int omap_sham_hw_init(struct omap_sham_dev *dd)
367 {
368 int err;
369
370 err = pm_runtime_get_sync(dd->dev);
371 if (err < 0) {
372 dev_err(dd->dev, "failed to get sync: %d\n", err);
373 return err;
374 }
375
376 if (!test_bit(FLAGS_INIT, &dd->flags)) {
377 set_bit(FLAGS_INIT, &dd->flags);
378 dd->err = 0;
379 }
380
381 return 0;
382 }
383
384 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
385 int final, int dma)
386 {
387 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
388 u32 val = length << 5, mask;
389
390 if (likely(ctx->digcnt))
391 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
392
393 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
394 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
395 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
396 /*
397 * Setting ALGO_CONST only for the first iteration
398 * and CLOSE_HASH only for the last one.
399 */
400 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
401 val |= SHA_REG_CTRL_ALGO;
402 if (!ctx->digcnt)
403 val |= SHA_REG_CTRL_ALGO_CONST;
404 if (final)
405 val |= SHA_REG_CTRL_CLOSE_HASH;
406
407 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
408 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
409
410 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
411 }
412
413 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
414 {
415 }
416
417 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
418 {
419 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
420 }
421
422 static int get_block_size(struct omap_sham_reqctx *ctx)
423 {
424 int d;
425
426 switch (ctx->flags & FLAGS_MODE_MASK) {
427 case FLAGS_MODE_MD5:
428 case FLAGS_MODE_SHA1:
429 d = SHA1_BLOCK_SIZE;
430 break;
431 case FLAGS_MODE_SHA224:
432 case FLAGS_MODE_SHA256:
433 d = SHA256_BLOCK_SIZE;
434 break;
435 case FLAGS_MODE_SHA384:
436 case FLAGS_MODE_SHA512:
437 d = SHA512_BLOCK_SIZE;
438 break;
439 default:
440 d = 0;
441 }
442
443 return d;
444 }
445
446 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
447 u32 *value, int count)
448 {
449 for (; count--; value++, offset += 4)
450 omap_sham_write(dd, offset, *value);
451 }
452
453 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
454 int final, int dma)
455 {
456 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
457 u32 val, mask;
458
459 /*
460 * Setting ALGO_CONST only for the first iteration and
461 * CLOSE_HASH only for the last one. Note that flags mode bits
462 * correspond to algorithm encoding in mode register.
463 */
464 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
465 if (!ctx->digcnt) {
466 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
467 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
468 struct omap_sham_hmac_ctx *bctx = tctx->base;
469 int bs, nr_dr;
470
471 val |= SHA_REG_MODE_ALGO_CONSTANT;
472
473 if (ctx->flags & BIT(FLAGS_HMAC)) {
474 bs = get_block_size(ctx);
475 nr_dr = bs / (2 * sizeof(u32));
476 val |= SHA_REG_MODE_HMAC_KEY_PROC;
477 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
478 (u32 *)bctx->ipad, nr_dr);
479 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
480 (u32 *)bctx->ipad + nr_dr, nr_dr);
481 ctx->digcnt += bs;
482 }
483 }
484
485 if (final) {
486 val |= SHA_REG_MODE_CLOSE_HASH;
487
488 if (ctx->flags & BIT(FLAGS_HMAC))
489 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
490 }
491
492 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
493 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
494 SHA_REG_MODE_HMAC_KEY_PROC;
495
496 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
497 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
498 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
499 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
500 SHA_REG_MASK_IT_EN |
501 (dma ? SHA_REG_MASK_DMA_EN : 0),
502 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
503 }
504
505 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
506 {
507 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
508 }
509
510 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
511 {
512 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
513 SHA_REG_IRQSTATUS_INPUT_RDY);
514 }
515
516 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
517 int final)
518 {
519 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
520 int count, len32, bs32, offset = 0;
521 const u32 *buffer;
522 int mlen;
523 struct sg_mapping_iter mi;
524
525 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
526 ctx->digcnt, length, final);
527
528 dd->pdata->write_ctrl(dd, length, final, 0);
529 dd->pdata->trigger(dd, length);
530
531 /* should be non-zero before next lines to disable clocks later */
532 ctx->digcnt += length;
533 ctx->total -= length;
534
535 if (final)
536 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
537
538 set_bit(FLAGS_CPU, &dd->flags);
539
540 len32 = DIV_ROUND_UP(length, sizeof(u32));
541 bs32 = get_block_size(ctx) / sizeof(u32);
542
543 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
544 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
545
546 mlen = 0;
547
548 while (len32) {
549 if (dd->pdata->poll_irq(dd))
550 return -ETIMEDOUT;
551
552 for (count = 0; count < min(len32, bs32); count++, offset++) {
553 if (!mlen) {
554 sg_miter_next(&mi);
555 mlen = mi.length;
556 if (!mlen) {
557 pr_err("sg miter failure.\n");
558 return -EINVAL;
559 }
560 offset = 0;
561 buffer = mi.addr;
562 }
563 omap_sham_write(dd, SHA_REG_DIN(dd, count),
564 buffer[offset]);
565 mlen -= 4;
566 }
567 len32 -= min(len32, bs32);
568 }
569
570 sg_miter_stop(&mi);
571
572 return -EINPROGRESS;
573 }
574
575 static void omap_sham_dma_callback(void *param)
576 {
577 struct omap_sham_dev *dd = param;
578
579 set_bit(FLAGS_DMA_READY, &dd->flags);
580 tasklet_schedule(&dd->done_task);
581 }
582
583 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
584 int final)
585 {
586 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
587 struct dma_async_tx_descriptor *tx;
588 struct dma_slave_config cfg;
589 int ret;
590
591 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
592 ctx->digcnt, length, final);
593
594 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
595 dev_err(dd->dev, "dma_map_sg error\n");
596 return -EINVAL;
597 }
598
599 memset(&cfg, 0, sizeof(cfg));
600
601 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
602 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
603 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
604
605 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
606 if (ret) {
607 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
608 return ret;
609 }
610
611 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
612 DMA_MEM_TO_DEV,
613 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
614
615 if (!tx) {
616 dev_err(dd->dev, "prep_slave_sg failed\n");
617 return -EINVAL;
618 }
619
620 tx->callback = omap_sham_dma_callback;
621 tx->callback_param = dd;
622
623 dd->pdata->write_ctrl(dd, length, final, 1);
624
625 ctx->digcnt += length;
626 ctx->total -= length;
627
628 if (final)
629 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
630
631 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
632
633 dmaengine_submit(tx);
634 dma_async_issue_pending(dd->dma_lch);
635
636 dd->pdata->trigger(dd, length);
637
638 return -EINPROGRESS;
639 }
640
641 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
642 struct scatterlist *sg, int bs, int new_len)
643 {
644 int n = sg_nents(sg);
645 struct scatterlist *tmp;
646 int offset = ctx->offset;
647
648 if (ctx->bufcnt)
649 n++;
650
651 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
652 if (!ctx->sg)
653 return -ENOMEM;
654
655 sg_init_table(ctx->sg, n);
656
657 tmp = ctx->sg;
658
659 ctx->sg_len = 0;
660
661 if (ctx->bufcnt) {
662 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
663 tmp = sg_next(tmp);
664 ctx->sg_len++;
665 }
666
667 while (sg && new_len) {
668 int len = sg->length - offset;
669
670 if (offset) {
671 offset -= sg->length;
672 if (offset < 0)
673 offset = 0;
674 }
675
676 if (new_len < len)
677 len = new_len;
678
679 if (len > 0) {
680 new_len -= len;
681 sg_set_page(tmp, sg_page(sg), len, sg->offset);
682 if (new_len <= 0)
683 sg_mark_end(tmp);
684 tmp = sg_next(tmp);
685 ctx->sg_len++;
686 }
687
688 sg = sg_next(sg);
689 }
690
691 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
692
693 ctx->bufcnt = 0;
694
695 return 0;
696 }
697
698 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
699 struct scatterlist *sg, int bs, int new_len)
700 {
701 int pages;
702 void *buf;
703 int len;
704
705 len = new_len + ctx->bufcnt;
706
707 pages = get_order(ctx->total);
708
709 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
710 if (!buf) {
711 pr_err("Couldn't allocate pages for unaligned cases.\n");
712 return -ENOMEM;
713 }
714
715 if (ctx->bufcnt)
716 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
717
718 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
719 ctx->total - ctx->bufcnt, 0);
720 sg_init_table(ctx->sgl, 1);
721 sg_set_buf(ctx->sgl, buf, len);
722 ctx->sg = ctx->sgl;
723 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
724 ctx->sg_len = 1;
725 ctx->bufcnt = 0;
726 ctx->offset = 0;
727
728 return 0;
729 }
730
731 static int omap_sham_align_sgs(struct scatterlist *sg,
732 int nbytes, int bs, bool final,
733 struct omap_sham_reqctx *rctx)
734 {
735 int n = 0;
736 bool aligned = true;
737 bool list_ok = true;
738 struct scatterlist *sg_tmp = sg;
739 int new_len;
740 int offset = rctx->offset;
741
742 if (!sg || !sg->length || !nbytes)
743 return 0;
744
745 new_len = nbytes;
746
747 if (offset)
748 list_ok = false;
749
750 if (final)
751 new_len = DIV_ROUND_UP(new_len, bs) * bs;
752 else
753 new_len = (new_len - 1) / bs * bs;
754
755 if (nbytes != new_len)
756 list_ok = false;
757
758 while (nbytes > 0 && sg_tmp) {
759 n++;
760
761 #ifdef CONFIG_ZONE_DMA
762 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
763 aligned = false;
764 break;
765 }
766 #endif
767
768 if (offset < sg_tmp->length) {
769 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
770 aligned = false;
771 break;
772 }
773
774 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
775 aligned = false;
776 break;
777 }
778 }
779
780 if (offset) {
781 offset -= sg_tmp->length;
782 if (offset < 0) {
783 nbytes += offset;
784 offset = 0;
785 }
786 } else {
787 nbytes -= sg_tmp->length;
788 }
789
790 sg_tmp = sg_next(sg_tmp);
791
792 if (nbytes < 0) {
793 list_ok = false;
794 break;
795 }
796 }
797
798 if (!aligned)
799 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
800 else if (!list_ok)
801 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
802
803 rctx->sg_len = n;
804 rctx->sg = sg;
805
806 return 0;
807 }
808
809 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
810 {
811 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
812 int bs;
813 int ret;
814 int nbytes;
815 bool final = rctx->flags & BIT(FLAGS_FINUP);
816 int xmit_len, hash_later;
817
818 bs = get_block_size(rctx);
819
820 if (update)
821 nbytes = req->nbytes;
822 else
823 nbytes = 0;
824
825 rctx->total = nbytes + rctx->bufcnt;
826
827 if (!rctx->total)
828 return 0;
829
830 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
831 int len = bs - rctx->bufcnt % bs;
832
833 if (len > nbytes)
834 len = nbytes;
835 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
836 0, len, 0);
837 rctx->bufcnt += len;
838 nbytes -= len;
839 rctx->offset = len;
840 }
841
842 if (rctx->bufcnt)
843 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
844
845 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
846 if (ret)
847 return ret;
848
849 xmit_len = rctx->total;
850
851 if (!IS_ALIGNED(xmit_len, bs)) {
852 if (final)
853 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
854 else
855 xmit_len = xmit_len / bs * bs;
856 } else if (!final) {
857 xmit_len -= bs;
858 }
859
860 hash_later = rctx->total - xmit_len;
861 if (hash_later < 0)
862 hash_later = 0;
863
864 if (rctx->bufcnt && nbytes) {
865 /* have data from previous operation and current */
866 sg_init_table(rctx->sgl, 2);
867 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
868
869 sg_chain(rctx->sgl, 2, req->src);
870
871 rctx->sg = rctx->sgl;
872
873 rctx->sg_len++;
874 } else if (rctx->bufcnt) {
875 /* have buffered data only */
876 sg_init_table(rctx->sgl, 1);
877 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
878
879 rctx->sg = rctx->sgl;
880
881 rctx->sg_len = 1;
882 }
883
884 if (hash_later) {
885 int offset = 0;
886
887 if (hash_later > req->nbytes) {
888 memcpy(rctx->buffer, rctx->buffer + xmit_len,
889 hash_later - req->nbytes);
890 offset = hash_later - req->nbytes;
891 }
892
893 if (req->nbytes) {
894 scatterwalk_map_and_copy(rctx->buffer + offset,
895 req->src,
896 offset + req->nbytes -
897 hash_later, hash_later, 0);
898 }
899
900 rctx->bufcnt = hash_later;
901 } else {
902 rctx->bufcnt = 0;
903 }
904
905 if (!final)
906 rctx->total = xmit_len;
907
908 return 0;
909 }
910
911 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
912 {
913 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
914
915 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
916
917 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
918
919 return 0;
920 }
921
922 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
923 {
924 struct omap_sham_dev *dd;
925
926 if (ctx->dd)
927 return ctx->dd;
928
929 spin_lock_bh(&sham.lock);
930 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
931 list_move_tail(&dd->list, &sham.dev_list);
932 ctx->dd = dd;
933 spin_unlock_bh(&sham.lock);
934
935 return dd;
936 }
937
938 static int omap_sham_init(struct ahash_request *req)
939 {
940 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
941 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
942 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
943 struct omap_sham_dev *dd;
944 int bs = 0;
945
946 ctx->dd = NULL;
947
948 dd = omap_sham_find_dev(ctx);
949 if (!dd)
950 return -ENODEV;
951
952 ctx->flags = 0;
953
954 dev_dbg(dd->dev, "init: digest size: %d\n",
955 crypto_ahash_digestsize(tfm));
956
957 switch (crypto_ahash_digestsize(tfm)) {
958 case MD5_DIGEST_SIZE:
959 ctx->flags |= FLAGS_MODE_MD5;
960 bs = SHA1_BLOCK_SIZE;
961 break;
962 case SHA1_DIGEST_SIZE:
963 ctx->flags |= FLAGS_MODE_SHA1;
964 bs = SHA1_BLOCK_SIZE;
965 break;
966 case SHA224_DIGEST_SIZE:
967 ctx->flags |= FLAGS_MODE_SHA224;
968 bs = SHA224_BLOCK_SIZE;
969 break;
970 case SHA256_DIGEST_SIZE:
971 ctx->flags |= FLAGS_MODE_SHA256;
972 bs = SHA256_BLOCK_SIZE;
973 break;
974 case SHA384_DIGEST_SIZE:
975 ctx->flags |= FLAGS_MODE_SHA384;
976 bs = SHA384_BLOCK_SIZE;
977 break;
978 case SHA512_DIGEST_SIZE:
979 ctx->flags |= FLAGS_MODE_SHA512;
980 bs = SHA512_BLOCK_SIZE;
981 break;
982 }
983
984 ctx->bufcnt = 0;
985 ctx->digcnt = 0;
986 ctx->total = 0;
987 ctx->offset = 0;
988 ctx->buflen = BUFLEN;
989
990 if (tctx->flags & BIT(FLAGS_HMAC)) {
991 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
992 struct omap_sham_hmac_ctx *bctx = tctx->base;
993
994 memcpy(ctx->buffer, bctx->ipad, bs);
995 ctx->bufcnt = bs;
996 }
997
998 ctx->flags |= BIT(FLAGS_HMAC);
999 }
1000
1001 return 0;
1002
1003 }
1004
1005 static int omap_sham_update_req(struct omap_sham_dev *dd)
1006 {
1007 struct ahash_request *req = dd->req;
1008 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1009 int err;
1010 bool final = ctx->flags & BIT(FLAGS_FINUP);
1011
1012 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1013 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1014
1015 if (ctx->total < get_block_size(ctx) ||
1016 ctx->total < dd->fallback_sz)
1017 ctx->flags |= BIT(FLAGS_CPU);
1018
1019 if (ctx->flags & BIT(FLAGS_CPU))
1020 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1021 else
1022 err = omap_sham_xmit_dma(dd, ctx->total, final);
1023
1024 /* wait for dma completion before can take more data */
1025 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1026
1027 return err;
1028 }
1029
1030 static int omap_sham_final_req(struct omap_sham_dev *dd)
1031 {
1032 struct ahash_request *req = dd->req;
1033 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1034 int err = 0, use_dma = 1;
1035
1036 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1037 /*
1038 * faster to handle last block with cpu or
1039 * use cpu when dma is not present.
1040 */
1041 use_dma = 0;
1042
1043 if (use_dma)
1044 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1045 else
1046 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1047
1048 ctx->bufcnt = 0;
1049
1050 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1051
1052 return err;
1053 }
1054
1055 static int omap_sham_finish_hmac(struct ahash_request *req)
1056 {
1057 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1058 struct omap_sham_hmac_ctx *bctx = tctx->base;
1059 int bs = crypto_shash_blocksize(bctx->shash);
1060 int ds = crypto_shash_digestsize(bctx->shash);
1061 SHASH_DESC_ON_STACK(shash, bctx->shash);
1062
1063 shash->tfm = bctx->shash;
1064 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1065
1066 return crypto_shash_init(shash) ?:
1067 crypto_shash_update(shash, bctx->opad, bs) ?:
1068 crypto_shash_finup(shash, req->result, ds, req->result);
1069 }
1070
1071 static int omap_sham_finish(struct ahash_request *req)
1072 {
1073 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1074 struct omap_sham_dev *dd = ctx->dd;
1075 int err = 0;
1076
1077 if (ctx->digcnt) {
1078 omap_sham_copy_ready_hash(req);
1079 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1080 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1081 err = omap_sham_finish_hmac(req);
1082 }
1083
1084 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1085
1086 return err;
1087 }
1088
1089 static void omap_sham_finish_req(struct ahash_request *req, int err)
1090 {
1091 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1092 struct omap_sham_dev *dd = ctx->dd;
1093
1094 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1095 free_pages((unsigned long)sg_virt(ctx->sg),
1096 get_order(ctx->sg->length + ctx->bufcnt));
1097
1098 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1099 kfree(ctx->sg);
1100
1101 ctx->sg = NULL;
1102
1103 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1104
1105 if (!err) {
1106 dd->pdata->copy_hash(req, 1);
1107 if (test_bit(FLAGS_FINAL, &dd->flags))
1108 err = omap_sham_finish(req);
1109 } else {
1110 ctx->flags |= BIT(FLAGS_ERROR);
1111 }
1112
1113 /* atomic operation is not needed here */
1114 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1115 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1116
1117 pm_runtime_mark_last_busy(dd->dev);
1118 pm_runtime_put_autosuspend(dd->dev);
1119
1120 if (req->base.complete)
1121 req->base.complete(&req->base, err);
1122 }
1123
1124 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1125 struct ahash_request *req)
1126 {
1127 struct crypto_async_request *async_req, *backlog;
1128 struct omap_sham_reqctx *ctx;
1129 unsigned long flags;
1130 int err = 0, ret = 0;
1131
1132 retry:
1133 spin_lock_irqsave(&dd->lock, flags);
1134 if (req)
1135 ret = ahash_enqueue_request(&dd->queue, req);
1136 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1137 spin_unlock_irqrestore(&dd->lock, flags);
1138 return ret;
1139 }
1140 backlog = crypto_get_backlog(&dd->queue);
1141 async_req = crypto_dequeue_request(&dd->queue);
1142 if (async_req)
1143 set_bit(FLAGS_BUSY, &dd->flags);
1144 spin_unlock_irqrestore(&dd->lock, flags);
1145
1146 if (!async_req)
1147 return ret;
1148
1149 if (backlog)
1150 backlog->complete(backlog, -EINPROGRESS);
1151
1152 req = ahash_request_cast(async_req);
1153 dd->req = req;
1154 ctx = ahash_request_ctx(req);
1155
1156 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1157 if (err || !ctx->total)
1158 goto err1;
1159
1160 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1161 ctx->op, req->nbytes);
1162
1163 err = omap_sham_hw_init(dd);
1164 if (err)
1165 goto err1;
1166
1167 if (ctx->digcnt)
1168 /* request has changed - restore hash */
1169 dd->pdata->copy_hash(req, 0);
1170
1171 if (ctx->op == OP_UPDATE) {
1172 err = omap_sham_update_req(dd);
1173 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1174 /* no final() after finup() */
1175 err = omap_sham_final_req(dd);
1176 } else if (ctx->op == OP_FINAL) {
1177 err = omap_sham_final_req(dd);
1178 }
1179 err1:
1180 dev_dbg(dd->dev, "exit, err: %d\n", err);
1181
1182 if (err != -EINPROGRESS) {
1183 /* done_task will not finish it, so do it here */
1184 omap_sham_finish_req(req, err);
1185 req = NULL;
1186
1187 /*
1188 * Execute next request immediately if there is anything
1189 * in queue.
1190 */
1191 goto retry;
1192 }
1193
1194 return ret;
1195 }
1196
1197 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1198 {
1199 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1200 struct omap_sham_dev *dd = ctx->dd;
1201
1202 ctx->op = op;
1203
1204 return omap_sham_handle_queue(dd, req);
1205 }
1206
1207 static int omap_sham_update(struct ahash_request *req)
1208 {
1209 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1210 struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1211
1212 if (!req->nbytes)
1213 return 0;
1214
1215 if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1216 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1217 0, req->nbytes, 0);
1218 ctx->bufcnt += req->nbytes;
1219 return 0;
1220 }
1221
1222 if (dd->polling_mode)
1223 ctx->flags |= BIT(FLAGS_CPU);
1224
1225 return omap_sham_enqueue(req, OP_UPDATE);
1226 }
1227
1228 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1229 const u8 *data, unsigned int len, u8 *out)
1230 {
1231 SHASH_DESC_ON_STACK(shash, tfm);
1232
1233 shash->tfm = tfm;
1234 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1235
1236 return crypto_shash_digest(shash, data, len, out);
1237 }
1238
1239 static int omap_sham_final_shash(struct ahash_request *req)
1240 {
1241 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1242 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1243 int offset = 0;
1244
1245 /*
1246 * If we are running HMAC on limited hardware support, skip
1247 * the ipad in the beginning of the buffer if we are going for
1248 * software fallback algorithm.
1249 */
1250 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1251 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1252 offset = get_block_size(ctx);
1253
1254 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1255 ctx->buffer + offset,
1256 ctx->bufcnt - offset, req->result);
1257 }
1258
1259 static int omap_sham_final(struct ahash_request *req)
1260 {
1261 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1262
1263 ctx->flags |= BIT(FLAGS_FINUP);
1264
1265 if (ctx->flags & BIT(FLAGS_ERROR))
1266 return 0; /* uncompleted hash is not needed */
1267
1268 /*
1269 * OMAP HW accel works only with buffers >= 9.
1270 * HMAC is always >= 9 because ipad == block size.
1271 * If buffersize is less than fallback_sz, we use fallback
1272 * SW encoding, as using DMA + HW in this case doesn't provide
1273 * any benefit.
1274 */
1275 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1276 return omap_sham_final_shash(req);
1277 else if (ctx->bufcnt)
1278 return omap_sham_enqueue(req, OP_FINAL);
1279
1280 /* copy ready hash (+ finalize hmac) */
1281 return omap_sham_finish(req);
1282 }
1283
1284 static int omap_sham_finup(struct ahash_request *req)
1285 {
1286 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1287 int err1, err2;
1288
1289 ctx->flags |= BIT(FLAGS_FINUP);
1290
1291 err1 = omap_sham_update(req);
1292 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1293 return err1;
1294 /*
1295 * final() has to be always called to cleanup resources
1296 * even if udpate() failed, except EINPROGRESS
1297 */
1298 err2 = omap_sham_final(req);
1299
1300 return err1 ?: err2;
1301 }
1302
1303 static int omap_sham_digest(struct ahash_request *req)
1304 {
1305 return omap_sham_init(req) ?: omap_sham_finup(req);
1306 }
1307
1308 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1309 unsigned int keylen)
1310 {
1311 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1312 struct omap_sham_hmac_ctx *bctx = tctx->base;
1313 int bs = crypto_shash_blocksize(bctx->shash);
1314 int ds = crypto_shash_digestsize(bctx->shash);
1315 int err, i;
1316
1317 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1318 if (err)
1319 return err;
1320
1321 if (keylen > bs) {
1322 err = omap_sham_shash_digest(bctx->shash,
1323 crypto_shash_get_flags(bctx->shash),
1324 key, keylen, bctx->ipad);
1325 if (err)
1326 return err;
1327 keylen = ds;
1328 } else {
1329 memcpy(bctx->ipad, key, keylen);
1330 }
1331
1332 memset(bctx->ipad + keylen, 0, bs - keylen);
1333
1334 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1335 memcpy(bctx->opad, bctx->ipad, bs);
1336
1337 for (i = 0; i < bs; i++) {
1338 bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1339 bctx->opad[i] ^= HMAC_OPAD_VALUE;
1340 }
1341 }
1342
1343 return err;
1344 }
1345
1346 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1347 {
1348 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1349 const char *alg_name = crypto_tfm_alg_name(tfm);
1350
1351 /* Allocate a fallback and abort if it failed. */
1352 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1353 CRYPTO_ALG_NEED_FALLBACK);
1354 if (IS_ERR(tctx->fallback)) {
1355 pr_err("omap-sham: fallback driver '%s' "
1356 "could not be loaded.\n", alg_name);
1357 return PTR_ERR(tctx->fallback);
1358 }
1359
1360 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1361 sizeof(struct omap_sham_reqctx) + BUFLEN);
1362
1363 if (alg_base) {
1364 struct omap_sham_hmac_ctx *bctx = tctx->base;
1365 tctx->flags |= BIT(FLAGS_HMAC);
1366 bctx->shash = crypto_alloc_shash(alg_base, 0,
1367 CRYPTO_ALG_NEED_FALLBACK);
1368 if (IS_ERR(bctx->shash)) {
1369 pr_err("omap-sham: base driver '%s' "
1370 "could not be loaded.\n", alg_base);
1371 crypto_free_shash(tctx->fallback);
1372 return PTR_ERR(bctx->shash);
1373 }
1374
1375 }
1376
1377 return 0;
1378 }
1379
1380 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1381 {
1382 return omap_sham_cra_init_alg(tfm, NULL);
1383 }
1384
1385 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1386 {
1387 return omap_sham_cra_init_alg(tfm, "sha1");
1388 }
1389
1390 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1391 {
1392 return omap_sham_cra_init_alg(tfm, "sha224");
1393 }
1394
1395 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1396 {
1397 return omap_sham_cra_init_alg(tfm, "sha256");
1398 }
1399
1400 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1401 {
1402 return omap_sham_cra_init_alg(tfm, "md5");
1403 }
1404
1405 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1406 {
1407 return omap_sham_cra_init_alg(tfm, "sha384");
1408 }
1409
1410 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1411 {
1412 return omap_sham_cra_init_alg(tfm, "sha512");
1413 }
1414
1415 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1416 {
1417 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1418
1419 crypto_free_shash(tctx->fallback);
1420 tctx->fallback = NULL;
1421
1422 if (tctx->flags & BIT(FLAGS_HMAC)) {
1423 struct omap_sham_hmac_ctx *bctx = tctx->base;
1424 crypto_free_shash(bctx->shash);
1425 }
1426 }
1427
1428 static int omap_sham_export(struct ahash_request *req, void *out)
1429 {
1430 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1431
1432 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1433
1434 return 0;
1435 }
1436
1437 static int omap_sham_import(struct ahash_request *req, const void *in)
1438 {
1439 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1440 const struct omap_sham_reqctx *ctx_in = in;
1441
1442 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1443
1444 return 0;
1445 }
1446
1447 static struct ahash_alg algs_sha1_md5[] = {
1448 {
1449 .init = omap_sham_init,
1450 .update = omap_sham_update,
1451 .final = omap_sham_final,
1452 .finup = omap_sham_finup,
1453 .digest = omap_sham_digest,
1454 .halg.digestsize = SHA1_DIGEST_SIZE,
1455 .halg.base = {
1456 .cra_name = "sha1",
1457 .cra_driver_name = "omap-sha1",
1458 .cra_priority = 400,
1459 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1460 CRYPTO_ALG_ASYNC |
1461 CRYPTO_ALG_NEED_FALLBACK,
1462 .cra_blocksize = SHA1_BLOCK_SIZE,
1463 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1464 .cra_alignmask = OMAP_ALIGN_MASK,
1465 .cra_module = THIS_MODULE,
1466 .cra_init = omap_sham_cra_init,
1467 .cra_exit = omap_sham_cra_exit,
1468 }
1469 },
1470 {
1471 .init = omap_sham_init,
1472 .update = omap_sham_update,
1473 .final = omap_sham_final,
1474 .finup = omap_sham_finup,
1475 .digest = omap_sham_digest,
1476 .halg.digestsize = MD5_DIGEST_SIZE,
1477 .halg.base = {
1478 .cra_name = "md5",
1479 .cra_driver_name = "omap-md5",
1480 .cra_priority = 400,
1481 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1482 CRYPTO_ALG_ASYNC |
1483 CRYPTO_ALG_NEED_FALLBACK,
1484 .cra_blocksize = SHA1_BLOCK_SIZE,
1485 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1486 .cra_alignmask = OMAP_ALIGN_MASK,
1487 .cra_module = THIS_MODULE,
1488 .cra_init = omap_sham_cra_init,
1489 .cra_exit = omap_sham_cra_exit,
1490 }
1491 },
1492 {
1493 .init = omap_sham_init,
1494 .update = omap_sham_update,
1495 .final = omap_sham_final,
1496 .finup = omap_sham_finup,
1497 .digest = omap_sham_digest,
1498 .setkey = omap_sham_setkey,
1499 .halg.digestsize = SHA1_DIGEST_SIZE,
1500 .halg.base = {
1501 .cra_name = "hmac(sha1)",
1502 .cra_driver_name = "omap-hmac-sha1",
1503 .cra_priority = 400,
1504 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1505 CRYPTO_ALG_ASYNC |
1506 CRYPTO_ALG_NEED_FALLBACK,
1507 .cra_blocksize = SHA1_BLOCK_SIZE,
1508 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1509 sizeof(struct omap_sham_hmac_ctx),
1510 .cra_alignmask = OMAP_ALIGN_MASK,
1511 .cra_module = THIS_MODULE,
1512 .cra_init = omap_sham_cra_sha1_init,
1513 .cra_exit = omap_sham_cra_exit,
1514 }
1515 },
1516 {
1517 .init = omap_sham_init,
1518 .update = omap_sham_update,
1519 .final = omap_sham_final,
1520 .finup = omap_sham_finup,
1521 .digest = omap_sham_digest,
1522 .setkey = omap_sham_setkey,
1523 .halg.digestsize = MD5_DIGEST_SIZE,
1524 .halg.base = {
1525 .cra_name = "hmac(md5)",
1526 .cra_driver_name = "omap-hmac-md5",
1527 .cra_priority = 400,
1528 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1529 CRYPTO_ALG_ASYNC |
1530 CRYPTO_ALG_NEED_FALLBACK,
1531 .cra_blocksize = SHA1_BLOCK_SIZE,
1532 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1533 sizeof(struct omap_sham_hmac_ctx),
1534 .cra_alignmask = OMAP_ALIGN_MASK,
1535 .cra_module = THIS_MODULE,
1536 .cra_init = omap_sham_cra_md5_init,
1537 .cra_exit = omap_sham_cra_exit,
1538 }
1539 }
1540 };
1541
1542 /* OMAP4 has some algs in addition to what OMAP2 has */
1543 static struct ahash_alg algs_sha224_sha256[] = {
1544 {
1545 .init = omap_sham_init,
1546 .update = omap_sham_update,
1547 .final = omap_sham_final,
1548 .finup = omap_sham_finup,
1549 .digest = omap_sham_digest,
1550 .halg.digestsize = SHA224_DIGEST_SIZE,
1551 .halg.base = {
1552 .cra_name = "sha224",
1553 .cra_driver_name = "omap-sha224",
1554 .cra_priority = 400,
1555 .cra_flags = CRYPTO_ALG_ASYNC |
1556 CRYPTO_ALG_NEED_FALLBACK,
1557 .cra_blocksize = SHA224_BLOCK_SIZE,
1558 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1559 .cra_alignmask = OMAP_ALIGN_MASK,
1560 .cra_module = THIS_MODULE,
1561 .cra_init = omap_sham_cra_init,
1562 .cra_exit = omap_sham_cra_exit,
1563 }
1564 },
1565 {
1566 .init = omap_sham_init,
1567 .update = omap_sham_update,
1568 .final = omap_sham_final,
1569 .finup = omap_sham_finup,
1570 .digest = omap_sham_digest,
1571 .halg.digestsize = SHA256_DIGEST_SIZE,
1572 .halg.base = {
1573 .cra_name = "sha256",
1574 .cra_driver_name = "omap-sha256",
1575 .cra_priority = 400,
1576 .cra_flags = CRYPTO_ALG_ASYNC |
1577 CRYPTO_ALG_NEED_FALLBACK,
1578 .cra_blocksize = SHA256_BLOCK_SIZE,
1579 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1580 .cra_alignmask = OMAP_ALIGN_MASK,
1581 .cra_module = THIS_MODULE,
1582 .cra_init = omap_sham_cra_init,
1583 .cra_exit = omap_sham_cra_exit,
1584 }
1585 },
1586 {
1587 .init = omap_sham_init,
1588 .update = omap_sham_update,
1589 .final = omap_sham_final,
1590 .finup = omap_sham_finup,
1591 .digest = omap_sham_digest,
1592 .setkey = omap_sham_setkey,
1593 .halg.digestsize = SHA224_DIGEST_SIZE,
1594 .halg.base = {
1595 .cra_name = "hmac(sha224)",
1596 .cra_driver_name = "omap-hmac-sha224",
1597 .cra_priority = 400,
1598 .cra_flags = CRYPTO_ALG_ASYNC |
1599 CRYPTO_ALG_NEED_FALLBACK,
1600 .cra_blocksize = SHA224_BLOCK_SIZE,
1601 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1602 sizeof(struct omap_sham_hmac_ctx),
1603 .cra_alignmask = OMAP_ALIGN_MASK,
1604 .cra_module = THIS_MODULE,
1605 .cra_init = omap_sham_cra_sha224_init,
1606 .cra_exit = omap_sham_cra_exit,
1607 }
1608 },
1609 {
1610 .init = omap_sham_init,
1611 .update = omap_sham_update,
1612 .final = omap_sham_final,
1613 .finup = omap_sham_finup,
1614 .digest = omap_sham_digest,
1615 .setkey = omap_sham_setkey,
1616 .halg.digestsize = SHA256_DIGEST_SIZE,
1617 .halg.base = {
1618 .cra_name = "hmac(sha256)",
1619 .cra_driver_name = "omap-hmac-sha256",
1620 .cra_priority = 400,
1621 .cra_flags = CRYPTO_ALG_ASYNC |
1622 CRYPTO_ALG_NEED_FALLBACK,
1623 .cra_blocksize = SHA256_BLOCK_SIZE,
1624 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1625 sizeof(struct omap_sham_hmac_ctx),
1626 .cra_alignmask = OMAP_ALIGN_MASK,
1627 .cra_module = THIS_MODULE,
1628 .cra_init = omap_sham_cra_sha256_init,
1629 .cra_exit = omap_sham_cra_exit,
1630 }
1631 },
1632 };
1633
1634 static struct ahash_alg algs_sha384_sha512[] = {
1635 {
1636 .init = omap_sham_init,
1637 .update = omap_sham_update,
1638 .final = omap_sham_final,
1639 .finup = omap_sham_finup,
1640 .digest = omap_sham_digest,
1641 .halg.digestsize = SHA384_DIGEST_SIZE,
1642 .halg.base = {
1643 .cra_name = "sha384",
1644 .cra_driver_name = "omap-sha384",
1645 .cra_priority = 400,
1646 .cra_flags = CRYPTO_ALG_ASYNC |
1647 CRYPTO_ALG_NEED_FALLBACK,
1648 .cra_blocksize = SHA384_BLOCK_SIZE,
1649 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1650 .cra_alignmask = OMAP_ALIGN_MASK,
1651 .cra_module = THIS_MODULE,
1652 .cra_init = omap_sham_cra_init,
1653 .cra_exit = omap_sham_cra_exit,
1654 }
1655 },
1656 {
1657 .init = omap_sham_init,
1658 .update = omap_sham_update,
1659 .final = omap_sham_final,
1660 .finup = omap_sham_finup,
1661 .digest = omap_sham_digest,
1662 .halg.digestsize = SHA512_DIGEST_SIZE,
1663 .halg.base = {
1664 .cra_name = "sha512",
1665 .cra_driver_name = "omap-sha512",
1666 .cra_priority = 400,
1667 .cra_flags = CRYPTO_ALG_ASYNC |
1668 CRYPTO_ALG_NEED_FALLBACK,
1669 .cra_blocksize = SHA512_BLOCK_SIZE,
1670 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1671 .cra_alignmask = OMAP_ALIGN_MASK,
1672 .cra_module = THIS_MODULE,
1673 .cra_init = omap_sham_cra_init,
1674 .cra_exit = omap_sham_cra_exit,
1675 }
1676 },
1677 {
1678 .init = omap_sham_init,
1679 .update = omap_sham_update,
1680 .final = omap_sham_final,
1681 .finup = omap_sham_finup,
1682 .digest = omap_sham_digest,
1683 .setkey = omap_sham_setkey,
1684 .halg.digestsize = SHA384_DIGEST_SIZE,
1685 .halg.base = {
1686 .cra_name = "hmac(sha384)",
1687 .cra_driver_name = "omap-hmac-sha384",
1688 .cra_priority = 400,
1689 .cra_flags = CRYPTO_ALG_ASYNC |
1690 CRYPTO_ALG_NEED_FALLBACK,
1691 .cra_blocksize = SHA384_BLOCK_SIZE,
1692 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1693 sizeof(struct omap_sham_hmac_ctx),
1694 .cra_alignmask = OMAP_ALIGN_MASK,
1695 .cra_module = THIS_MODULE,
1696 .cra_init = omap_sham_cra_sha384_init,
1697 .cra_exit = omap_sham_cra_exit,
1698 }
1699 },
1700 {
1701 .init = omap_sham_init,
1702 .update = omap_sham_update,
1703 .final = omap_sham_final,
1704 .finup = omap_sham_finup,
1705 .digest = omap_sham_digest,
1706 .setkey = omap_sham_setkey,
1707 .halg.digestsize = SHA512_DIGEST_SIZE,
1708 .halg.base = {
1709 .cra_name = "hmac(sha512)",
1710 .cra_driver_name = "omap-hmac-sha512",
1711 .cra_priority = 400,
1712 .cra_flags = CRYPTO_ALG_ASYNC |
1713 CRYPTO_ALG_NEED_FALLBACK,
1714 .cra_blocksize = SHA512_BLOCK_SIZE,
1715 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1716 sizeof(struct omap_sham_hmac_ctx),
1717 .cra_alignmask = OMAP_ALIGN_MASK,
1718 .cra_module = THIS_MODULE,
1719 .cra_init = omap_sham_cra_sha512_init,
1720 .cra_exit = omap_sham_cra_exit,
1721 }
1722 },
1723 };
1724
1725 static void omap_sham_done_task(unsigned long data)
1726 {
1727 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1728 int err = 0;
1729
1730 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1731 omap_sham_handle_queue(dd, NULL);
1732 return;
1733 }
1734
1735 if (test_bit(FLAGS_CPU, &dd->flags)) {
1736 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1737 goto finish;
1738 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1739 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1740 omap_sham_update_dma_stop(dd);
1741 if (dd->err) {
1742 err = dd->err;
1743 goto finish;
1744 }
1745 }
1746 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1747 /* hash or semi-hash ready */
1748 clear_bit(FLAGS_DMA_READY, &dd->flags);
1749 goto finish;
1750 }
1751 }
1752
1753 return;
1754
1755 finish:
1756 dev_dbg(dd->dev, "update done: err: %d\n", err);
1757 /* finish curent request */
1758 omap_sham_finish_req(dd->req, err);
1759
1760 /* If we are not busy, process next req */
1761 if (!test_bit(FLAGS_BUSY, &dd->flags))
1762 omap_sham_handle_queue(dd, NULL);
1763 }
1764
1765 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1766 {
1767 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1768 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1769 } else {
1770 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1771 tasklet_schedule(&dd->done_task);
1772 }
1773
1774 return IRQ_HANDLED;
1775 }
1776
1777 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1778 {
1779 struct omap_sham_dev *dd = dev_id;
1780
1781 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1782 /* final -> allow device to go to power-saving mode */
1783 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1784
1785 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1786 SHA_REG_CTRL_OUTPUT_READY);
1787 omap_sham_read(dd, SHA_REG_CTRL);
1788
1789 return omap_sham_irq_common(dd);
1790 }
1791
1792 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1793 {
1794 struct omap_sham_dev *dd = dev_id;
1795
1796 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1797
1798 return omap_sham_irq_common(dd);
1799 }
1800
1801 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1802 {
1803 .algs_list = algs_sha1_md5,
1804 .size = ARRAY_SIZE(algs_sha1_md5),
1805 },
1806 };
1807
1808 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1809 .algs_info = omap_sham_algs_info_omap2,
1810 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1811 .flags = BIT(FLAGS_BE32_SHA1),
1812 .digest_size = SHA1_DIGEST_SIZE,
1813 .copy_hash = omap_sham_copy_hash_omap2,
1814 .write_ctrl = omap_sham_write_ctrl_omap2,
1815 .trigger = omap_sham_trigger_omap2,
1816 .poll_irq = omap_sham_poll_irq_omap2,
1817 .intr_hdlr = omap_sham_irq_omap2,
1818 .idigest_ofs = 0x00,
1819 .din_ofs = 0x1c,
1820 .digcnt_ofs = 0x14,
1821 .rev_ofs = 0x5c,
1822 .mask_ofs = 0x60,
1823 .sysstatus_ofs = 0x64,
1824 .major_mask = 0xf0,
1825 .major_shift = 4,
1826 .minor_mask = 0x0f,
1827 .minor_shift = 0,
1828 };
1829
1830 #ifdef CONFIG_OF
1831 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1832 {
1833 .algs_list = algs_sha1_md5,
1834 .size = ARRAY_SIZE(algs_sha1_md5),
1835 },
1836 {
1837 .algs_list = algs_sha224_sha256,
1838 .size = ARRAY_SIZE(algs_sha224_sha256),
1839 },
1840 };
1841
1842 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1843 .algs_info = omap_sham_algs_info_omap4,
1844 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1845 .flags = BIT(FLAGS_AUTO_XOR),
1846 .digest_size = SHA256_DIGEST_SIZE,
1847 .copy_hash = omap_sham_copy_hash_omap4,
1848 .write_ctrl = omap_sham_write_ctrl_omap4,
1849 .trigger = omap_sham_trigger_omap4,
1850 .poll_irq = omap_sham_poll_irq_omap4,
1851 .intr_hdlr = omap_sham_irq_omap4,
1852 .idigest_ofs = 0x020,
1853 .odigest_ofs = 0x0,
1854 .din_ofs = 0x080,
1855 .digcnt_ofs = 0x040,
1856 .rev_ofs = 0x100,
1857 .mask_ofs = 0x110,
1858 .sysstatus_ofs = 0x114,
1859 .mode_ofs = 0x44,
1860 .length_ofs = 0x48,
1861 .major_mask = 0x0700,
1862 .major_shift = 8,
1863 .minor_mask = 0x003f,
1864 .minor_shift = 0,
1865 };
1866
1867 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1868 {
1869 .algs_list = algs_sha1_md5,
1870 .size = ARRAY_SIZE(algs_sha1_md5),
1871 },
1872 {
1873 .algs_list = algs_sha224_sha256,
1874 .size = ARRAY_SIZE(algs_sha224_sha256),
1875 },
1876 {
1877 .algs_list = algs_sha384_sha512,
1878 .size = ARRAY_SIZE(algs_sha384_sha512),
1879 },
1880 };
1881
1882 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1883 .algs_info = omap_sham_algs_info_omap5,
1884 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1885 .flags = BIT(FLAGS_AUTO_XOR),
1886 .digest_size = SHA512_DIGEST_SIZE,
1887 .copy_hash = omap_sham_copy_hash_omap4,
1888 .write_ctrl = omap_sham_write_ctrl_omap4,
1889 .trigger = omap_sham_trigger_omap4,
1890 .poll_irq = omap_sham_poll_irq_omap4,
1891 .intr_hdlr = omap_sham_irq_omap4,
1892 .idigest_ofs = 0x240,
1893 .odigest_ofs = 0x200,
1894 .din_ofs = 0x080,
1895 .digcnt_ofs = 0x280,
1896 .rev_ofs = 0x100,
1897 .mask_ofs = 0x110,
1898 .sysstatus_ofs = 0x114,
1899 .mode_ofs = 0x284,
1900 .length_ofs = 0x288,
1901 .major_mask = 0x0700,
1902 .major_shift = 8,
1903 .minor_mask = 0x003f,
1904 .minor_shift = 0,
1905 };
1906
1907 static const struct of_device_id omap_sham_of_match[] = {
1908 {
1909 .compatible = "ti,omap2-sham",
1910 .data = &omap_sham_pdata_omap2,
1911 },
1912 {
1913 .compatible = "ti,omap3-sham",
1914 .data = &omap_sham_pdata_omap2,
1915 },
1916 {
1917 .compatible = "ti,omap4-sham",
1918 .data = &omap_sham_pdata_omap4,
1919 },
1920 {
1921 .compatible = "ti,omap5-sham",
1922 .data = &omap_sham_pdata_omap5,
1923 },
1924 {},
1925 };
1926 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1927
1928 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1929 struct device *dev, struct resource *res)
1930 {
1931 struct device_node *node = dev->of_node;
1932 int err = 0;
1933
1934 dd->pdata = of_device_get_match_data(dev);
1935 if (!dd->pdata) {
1936 dev_err(dev, "no compatible OF match\n");
1937 err = -EINVAL;
1938 goto err;
1939 }
1940
1941 err = of_address_to_resource(node, 0, res);
1942 if (err < 0) {
1943 dev_err(dev, "can't translate OF node address\n");
1944 err = -EINVAL;
1945 goto err;
1946 }
1947
1948 dd->irq = irq_of_parse_and_map(node, 0);
1949 if (!dd->irq) {
1950 dev_err(dev, "can't translate OF irq value\n");
1951 err = -EINVAL;
1952 goto err;
1953 }
1954
1955 err:
1956 return err;
1957 }
1958 #else
1959 static const struct of_device_id omap_sham_of_match[] = {
1960 {},
1961 };
1962
1963 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1964 struct device *dev, struct resource *res)
1965 {
1966 return -EINVAL;
1967 }
1968 #endif
1969
1970 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1971 struct platform_device *pdev, struct resource *res)
1972 {
1973 struct device *dev = &pdev->dev;
1974 struct resource *r;
1975 int err = 0;
1976
1977 /* Get the base address */
1978 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1979 if (!r) {
1980 dev_err(dev, "no MEM resource info\n");
1981 err = -ENODEV;
1982 goto err;
1983 }
1984 memcpy(res, r, sizeof(*res));
1985
1986 /* Get the IRQ */
1987 dd->irq = platform_get_irq(pdev, 0);
1988 if (dd->irq < 0) {
1989 dev_err(dev, "no IRQ resource info\n");
1990 err = dd->irq;
1991 goto err;
1992 }
1993
1994 /* Only OMAP2/3 can be non-DT */
1995 dd->pdata = &omap_sham_pdata_omap2;
1996
1997 err:
1998 return err;
1999 }
2000
2001 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2002 char *buf)
2003 {
2004 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2005
2006 return sprintf(buf, "%d\n", dd->fallback_sz);
2007 }
2008
2009 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2010 const char *buf, size_t size)
2011 {
2012 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2013 ssize_t status;
2014 long value;
2015
2016 status = kstrtol(buf, 0, &value);
2017 if (status)
2018 return status;
2019
2020 /* HW accelerator only works with buffers > 9 */
2021 if (value < 9) {
2022 dev_err(dev, "minimum fallback size 9\n");
2023 return -EINVAL;
2024 }
2025
2026 dd->fallback_sz = value;
2027
2028 return size;
2029 }
2030
2031 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2032 char *buf)
2033 {
2034 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2035
2036 return sprintf(buf, "%d\n", dd->queue.max_qlen);
2037 }
2038
2039 static ssize_t queue_len_store(struct device *dev,
2040 struct device_attribute *attr, const char *buf,
2041 size_t size)
2042 {
2043 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2044 ssize_t status;
2045 long value;
2046 unsigned long flags;
2047
2048 status = kstrtol(buf, 0, &value);
2049 if (status)
2050 return status;
2051
2052 if (value < 1)
2053 return -EINVAL;
2054
2055 /*
2056 * Changing the queue size in fly is safe, if size becomes smaller
2057 * than current size, it will just not accept new entries until
2058 * it has shrank enough.
2059 */
2060 spin_lock_irqsave(&dd->lock, flags);
2061 dd->queue.max_qlen = value;
2062 spin_unlock_irqrestore(&dd->lock, flags);
2063
2064 return size;
2065 }
2066
2067 static DEVICE_ATTR_RW(queue_len);
2068 static DEVICE_ATTR_RW(fallback);
2069
2070 static struct attribute *omap_sham_attrs[] = {
2071 &dev_attr_queue_len.attr,
2072 &dev_attr_fallback.attr,
2073 NULL,
2074 };
2075
2076 static struct attribute_group omap_sham_attr_group = {
2077 .attrs = omap_sham_attrs,
2078 };
2079
2080 static int omap_sham_probe(struct platform_device *pdev)
2081 {
2082 struct omap_sham_dev *dd;
2083 struct device *dev = &pdev->dev;
2084 struct resource res;
2085 dma_cap_mask_t mask;
2086 int err, i, j;
2087 u32 rev;
2088
2089 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2090 if (dd == NULL) {
2091 dev_err(dev, "unable to alloc data struct.\n");
2092 err = -ENOMEM;
2093 goto data_err;
2094 }
2095 dd->dev = dev;
2096 platform_set_drvdata(pdev, dd);
2097
2098 INIT_LIST_HEAD(&dd->list);
2099 spin_lock_init(&dd->lock);
2100 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2101 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2102
2103 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2104 omap_sham_get_res_pdev(dd, pdev, &res);
2105 if (err)
2106 goto data_err;
2107
2108 dd->io_base = devm_ioremap_resource(dev, &res);
2109 if (IS_ERR(dd->io_base)) {
2110 err = PTR_ERR(dd->io_base);
2111 goto data_err;
2112 }
2113 dd->phys_base = res.start;
2114
2115 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2116 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2117 if (err) {
2118 dev_err(dev, "unable to request irq %d, err = %d\n",
2119 dd->irq, err);
2120 goto data_err;
2121 }
2122
2123 dma_cap_zero(mask);
2124 dma_cap_set(DMA_SLAVE, mask);
2125
2126 dd->dma_lch = dma_request_chan(dev, "rx");
2127 if (IS_ERR(dd->dma_lch)) {
2128 err = PTR_ERR(dd->dma_lch);
2129 if (err == -EPROBE_DEFER)
2130 goto data_err;
2131
2132 dd->polling_mode = 1;
2133 dev_dbg(dev, "using polling mode instead of dma\n");
2134 }
2135
2136 dd->flags |= dd->pdata->flags;
2137 sham.flags |= dd->pdata->flags;
2138
2139 pm_runtime_use_autosuspend(dev);
2140 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2141
2142 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2143
2144 pm_runtime_enable(dev);
2145 pm_runtime_irq_safe(dev);
2146
2147 err = pm_runtime_get_sync(dev);
2148 if (err < 0) {
2149 dev_err(dev, "failed to get sync: %d\n", err);
2150 goto err_pm;
2151 }
2152
2153 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2154 pm_runtime_put_sync(&pdev->dev);
2155
2156 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2157 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2158 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2159
2160 spin_lock(&sham.lock);
2161 list_add_tail(&dd->list, &sham.dev_list);
2162 spin_unlock(&sham.lock);
2163
2164 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2165 if (dd->pdata->algs_info[i].registered)
2166 break;
2167
2168 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2169 struct ahash_alg *alg;
2170
2171 alg = &dd->pdata->algs_info[i].algs_list[j];
2172 alg->export = omap_sham_export;
2173 alg->import = omap_sham_import;
2174 alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2175 BUFLEN;
2176 err = crypto_register_ahash(alg);
2177 if (err)
2178 goto err_algs;
2179
2180 dd->pdata->algs_info[i].registered++;
2181 }
2182 }
2183
2184 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2185 if (err) {
2186 dev_err(dev, "could not create sysfs device attrs\n");
2187 goto err_algs;
2188 }
2189
2190 return 0;
2191
2192 err_algs:
2193 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2194 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2195 crypto_unregister_ahash(
2196 &dd->pdata->algs_info[i].algs_list[j]);
2197 err_pm:
2198 pm_runtime_disable(dev);
2199 if (!dd->polling_mode)
2200 dma_release_channel(dd->dma_lch);
2201 data_err:
2202 dev_err(dev, "initialization failed.\n");
2203
2204 return err;
2205 }
2206
2207 static int omap_sham_remove(struct platform_device *pdev)
2208 {
2209 struct omap_sham_dev *dd;
2210 int i, j;
2211
2212 dd = platform_get_drvdata(pdev);
2213 if (!dd)
2214 return -ENODEV;
2215 spin_lock(&sham.lock);
2216 list_del(&dd->list);
2217 spin_unlock(&sham.lock);
2218 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2219 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2220 crypto_unregister_ahash(
2221 &dd->pdata->algs_info[i].algs_list[j]);
2222 dd->pdata->algs_info[i].registered--;
2223 }
2224 tasklet_kill(&dd->done_task);
2225 pm_runtime_disable(&pdev->dev);
2226
2227 if (!dd->polling_mode)
2228 dma_release_channel(dd->dma_lch);
2229
2230 return 0;
2231 }
2232
2233 #ifdef CONFIG_PM_SLEEP
2234 static int omap_sham_suspend(struct device *dev)
2235 {
2236 pm_runtime_put_sync(dev);
2237 return 0;
2238 }
2239
2240 static int omap_sham_resume(struct device *dev)
2241 {
2242 int err = pm_runtime_get_sync(dev);
2243 if (err < 0) {
2244 dev_err(dev, "failed to get sync: %d\n", err);
2245 return err;
2246 }
2247 return 0;
2248 }
2249 #endif
2250
2251 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2252
2253 static struct platform_driver omap_sham_driver = {
2254 .probe = omap_sham_probe,
2255 .remove = omap_sham_remove,
2256 .driver = {
2257 .name = "omap-sham",
2258 .pm = &omap_sham_pm_ops,
2259 .of_match_table = omap_sham_of_match,
2260 },
2261 };
2262
2263 module_platform_driver(omap_sham_driver);
2264
2265 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2266 MODULE_LICENSE("GPL v2");
2267 MODULE_AUTHOR("Dmitry Kasatkin");
2268 MODULE_ALIAS("platform:omap-sham");
Linux with added FPC-III support