drivers/crypto/talitos.h

   1 /*
   2  * Freescale SEC (talitos) device register and descriptor header defines
   3  *
   4  * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  */
  30
  31 #define TALITOS_TIMEOUT 100000
  32 #define TALITOS1_MAX_DATA_LEN 32768
  33 #define TALITOS2_MAX_DATA_LEN 65535
  34
  35 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  36 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  37 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  38
  39 /* descriptor pointer entry */
  40 struct talitos_ptr {
  41         union {
  42                 struct {                /* SEC2 format */
  43                         __be16 len;     /* length */
  44                         u8 j_extent;    /* jump to sg link table and/or extent*/
  45                         u8 eptr;        /* extended address */
  46                 };
  47                 struct {                        /* SEC1 format */
  48                         __be16 res;
  49                         __be16 len1;    /* length */
  50                 };
  51         };
  52         __be32 ptr;     /* address */
  53 };
  54
  55 /* descriptor */
  56 struct talitos_desc {
  57         __be32 hdr;                     /* header high bits */
  58         union {
  59                 __be32 hdr_lo;          /* header low bits */
  60                 __be32 hdr1;            /* header for SEC1 */
  61         };
  62         struct talitos_ptr ptr[7];      /* ptr/len pair array */
  63         __be32 next_desc;               /* next descriptor (SEC1) */
  64 };
  65
  66 #define TALITOS_DESC_SIZE       (sizeof(struct talitos_desc) - sizeof(__be32))
  67
  68 /*
  69  * talitos_edesc - s/w-extended descriptor
  70  * @src_nents: number of segments in input scatterlist
  71  * @dst_nents: number of segments in output scatterlist
  72  * @icv_ool: whether ICV is out-of-line
  73  * @iv_dma: dma address of iv for checking continuity and link table
  74  * @dma_len: length of dma mapped link_tbl space
  75  * @dma_link_tbl: bus physical address of link_tbl/buf
  76  * @desc: h/w descriptor
  77  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
  78  * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
  79  *
  80  * if decrypting (with authcheck), or either one of src_nents or dst_nents
  81  * is greater than 1, an integrity check value is concatenated to the end
  82  * of link_tbl data
  83  */
  84 struct talitos_edesc {
  85         int src_nents;
  86         int dst_nents;
  87         bool icv_ool;
  88         dma_addr_t iv_dma;
  89         int dma_len;
  90         dma_addr_t dma_link_tbl;
  91         struct talitos_desc desc;
  92         union {
  93                 struct talitos_ptr link_tbl[0];
  94                 u8 buf[0];
  95         };
  96 };
  97
  98 /**
  99  * talitos_request - descriptor submission request
 100  * @desc: descriptor pointer (kernel virtual)
 101  * @dma_desc: descriptor's physical bus address
 102  * @callback: whom to call when descriptor processing is done
 103  * @context: caller context (optional)
 104  */
 105 struct talitos_request {
 106         struct talitos_desc *desc;
 107         dma_addr_t dma_desc;
 108         void (*callback) (struct device *dev, struct talitos_desc *desc,
 109                           void *context, int error);
 110         void *context;
 111 };
 112
 113 /* per-channel fifo management */
 114 struct talitos_channel {
 115         void __iomem *reg;
 116
 117         /* request fifo */
 118         struct talitos_request *fifo;
 119
 120         /* number of requests pending in channel h/w fifo */
 121         atomic_t submit_count ____cacheline_aligned;
 122
 123         /* request submission (head) lock */
 124         spinlock_t head_lock ____cacheline_aligned;
 125         /* index to next free descriptor request */
 126         int head;
 127
 128         /* request release (tail) lock */
 129         spinlock_t tail_lock ____cacheline_aligned;
 130         /* index to next in-progress/done descriptor request */
 131         int tail;
 132 };
 133
 134 struct talitos_private {
 135         struct device *dev;
 136         struct platform_device *ofdev;
 137         void __iomem *reg;
 138         void __iomem *reg_deu;
 139         void __iomem *reg_aesu;
 140         void __iomem *reg_mdeu;
 141         void __iomem *reg_afeu;
 142         void __iomem *reg_rngu;
 143         void __iomem *reg_pkeu;
 144         void __iomem *reg_keu;
 145         void __iomem *reg_crcu;
 146         int irq[2];
 147
 148         /* SEC global registers lock  */
 149         spinlock_t reg_lock ____cacheline_aligned;
 150
 151         /* SEC version geometry (from device tree node) */
 152         unsigned int num_channels;
 153         unsigned int chfifo_len;
 154         unsigned int exec_units;
 155         unsigned int desc_types;
 156
 157         /* SEC Compatibility info */
 158         unsigned long features;
 159
 160         /*
 161          * length of the request fifo
 162          * fifo_len is chfifo_len rounded up to next power of 2
 163          * so we can use bitwise ops to wrap
 164          */
 165         unsigned int fifo_len;
 166
 167         struct talitos_channel *chan;
 168
 169         /* next channel to be assigned next incoming descriptor */
 170         atomic_t last_chan ____cacheline_aligned;
 171
 172         /* request callback tasklet */
 173         struct tasklet_struct done_task[2];
 174
 175         /* list of registered algorithms */
 176         struct list_head alg_list;
 177
 178         /* hwrng device */
 179         struct hwrng rng;
 180         bool rng_registered;
 181 };
 182
 183 extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
 184                           void (*callback)(struct device *dev,
 185                                            struct talitos_desc *desc,
 186                                            void *context, int error),
 187                           void *context);
 188
 189 /* .features flag */
 190 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
 191 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
 192 #define TALITOS_FTR_SHA224_HWINIT 0x00000004
 193 #define TALITOS_FTR_HMAC_OK 0x00000008
 194 #define TALITOS_FTR_SEC1 0x00000010
 195
 196 /*
 197  * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
 198  * defined, we check the features which are set according to the device tree.
 199  * Otherwise, we answer true or false directly
 200  */
 201 static inline bool has_ftr_sec1(struct talitos_private *priv)
 202 {
 203 #if defined(CONFIG_CRYPTO_DEV_TALITOS1) && defined(CONFIG_CRYPTO_DEV_TALITOS2)
 204         return priv->features & TALITOS_FTR_SEC1 ? true : false;
 205 #elif defined(CONFIG_CRYPTO_DEV_TALITOS1)
 206         return true;
 207 #else
 208         return false;
 209 #endif
 210 }
 211
 212 /*
 213  * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
 214  */
 215
 216 #define ISR1_FORMAT(x)                  (((x) << 28) | ((x) << 16))
 217 #define ISR2_FORMAT(x)                  (((x) << 4) | (x))
 218
 219 /* global register offset addresses */
 220 #define TALITOS_MCR                     0x1030  /* master control register */
 221 #define   TALITOS_MCR_RCA0              (1 << 15) /* remap channel 0 */
 222 #define   TALITOS_MCR_RCA1              (1 << 14) /* remap channel 1 */
 223 #define   TALITOS_MCR_RCA2              (1 << 13) /* remap channel 2 */
 224 #define   TALITOS_MCR_RCA3              (1 << 12) /* remap channel 3 */
 225 #define   TALITOS1_MCR_SWR              0x1000000     /* s/w reset */
 226 #define   TALITOS2_MCR_SWR              0x1     /* s/w reset */
 227 #define TALITOS_MCR_LO                  0x1034
 228 #define TALITOS_IMR                     0x1008  /* interrupt mask register */
 229 /* enable channel IRQs */
 230 #define   TALITOS1_IMR_INIT             ISR1_FORMAT(0xf)
 231 #define   TALITOS1_IMR_DONE             ISR1_FORMAT(0x5) /* done IRQs */
 232 /* enable channel IRQs */
 233 #define   TALITOS2_IMR_INIT             (ISR2_FORMAT(0xf) | 0x10000)
 234 #define   TALITOS2_IMR_DONE             ISR1_FORMAT(0x5) /* done IRQs */
 235 #define TALITOS_IMR_LO                  0x100C
 236 #define   TALITOS1_IMR_LO_INIT          0x2000000 /* allow RNGU error IRQs */
 237 #define   TALITOS2_IMR_LO_INIT          0x20000 /* allow RNGU error IRQs */
 238 #define TALITOS_ISR                     0x1010  /* interrupt status register */
 239 #define   TALITOS1_ISR_4CHERR           ISR1_FORMAT(0xa) /* 4 ch errors mask */
 240 #define   TALITOS1_ISR_4CHDONE          ISR1_FORMAT(0x5) /* 4 ch done mask */
 241 #define   TALITOS1_ISR_CH_0_ERR         (2 << 28) /* ch 0 errors mask */
 242 #define   TALITOS1_ISR_CH_0_DONE        (1 << 28) /* ch 0 done mask */
 243 #define   TALITOS1_ISR_TEA_ERR          0x00000040
 244 #define   TALITOS2_ISR_4CHERR           ISR2_FORMAT(0xa) /* 4 ch errors mask */
 245 #define   TALITOS2_ISR_4CHDONE          ISR2_FORMAT(0x5) /* 4 ch done mask */
 246 #define   TALITOS2_ISR_CH_0_ERR         2 /* ch 0 errors mask */
 247 #define   TALITOS2_ISR_CH_0_DONE        1 /* ch 0 done mask */
 248 #define   TALITOS2_ISR_CH_0_2_ERR       ISR2_FORMAT(0x2) /* ch 0, 2 err mask */
 249 #define   TALITOS2_ISR_CH_0_2_DONE      ISR2_FORMAT(0x1) /* ch 0, 2 done mask */
 250 #define   TALITOS2_ISR_CH_1_3_ERR       ISR2_FORMAT(0x8) /* ch 1, 3 err mask */
 251 #define   TALITOS2_ISR_CH_1_3_DONE      ISR2_FORMAT(0x4) /* ch 1, 3 done mask */
 252 #define TALITOS_ISR_LO                  0x1014
 253 #define TALITOS_ICR                     0x1018  /* interrupt clear register */
 254 #define TALITOS_ICR_LO                  0x101C
 255
 256 /* channel register address stride */
 257 #define TALITOS_CH_BASE_OFFSET          0x1000  /* default channel map base */
 258 #define TALITOS1_CH_STRIDE              0x1000
 259 #define TALITOS2_CH_STRIDE              0x100
 260
 261 /* channel configuration register  */
 262 #define TALITOS_CCCR                    0x8
 263 #define   TALITOS2_CCCR_CONT            0x2    /* channel continue on SEC2 */
 264 #define   TALITOS2_CCCR_RESET           0x1    /* channel reset on SEC2 */
 265 #define TALITOS_CCCR_LO                 0xc
 266 #define   TALITOS_CCCR_LO_IWSE          0x80   /* chan. ICCR writeback enab. */
 267 #define   TALITOS_CCCR_LO_EAE           0x20   /* extended address enable */
 268 #define   TALITOS_CCCR_LO_CDWE          0x10   /* chan. done writeback enab. */
 269 #define   TALITOS_CCCR_LO_NE            0x8    /* fetch next descriptor enab. */
 270 #define   TALITOS_CCCR_LO_NT            0x4    /* notification type */
 271 #define   TALITOS_CCCR_LO_CDIE          0x2    /* channel done IRQ enable */
 272 #define   TALITOS1_CCCR_LO_RESET        0x1    /* channel reset on SEC1 */
 273
 274 /* CCPSR: channel pointer status register */
 275 #define TALITOS_CCPSR                   0x10
 276 #define TALITOS_CCPSR_LO                0x14
 277 #define   TALITOS_CCPSR_LO_DOF          0x8000 /* double FF write oflow error */
 278 #define   TALITOS_CCPSR_LO_SOF          0x4000 /* single FF write oflow error */
 279 #define   TALITOS_CCPSR_LO_MDTE         0x2000 /* master data transfer error */
 280 #define   TALITOS_CCPSR_LO_SGDLZ        0x1000 /* s/g data len zero error */
 281 #define   TALITOS_CCPSR_LO_FPZ          0x0800 /* fetch ptr zero error */
 282 #define   TALITOS_CCPSR_LO_IDH          0x0400 /* illegal desc hdr error */
 283 #define   TALITOS_CCPSR_LO_IEU          0x0200 /* invalid EU error */
 284 #define   TALITOS_CCPSR_LO_EU           0x0100 /* EU error detected */
 285 #define   TALITOS_CCPSR_LO_GB           0x0080 /* gather boundary error */
 286 #define   TALITOS_CCPSR_LO_GRL          0x0040 /* gather return/length error */
 287 #define   TALITOS_CCPSR_LO_SB           0x0020 /* scatter boundary error */
 288 #define   TALITOS_CCPSR_LO_SRL          0x0010 /* scatter return/length error */
 289
 290 /* channel fetch fifo register */
 291 #define TALITOS_FF                      0x48
 292 #define TALITOS_FF_LO                   0x4c
 293
 294 /* current descriptor pointer register */
 295 #define TALITOS_CDPR                    0x40
 296 #define TALITOS_CDPR_LO                 0x44
 297
 298 /* descriptor buffer register */
 299 #define TALITOS_DESCBUF                 0x80
 300 #define TALITOS_DESCBUF_LO              0x84
 301
 302 /* gather link table */
 303 #define TALITOS_GATHER                  0xc0
 304 #define TALITOS_GATHER_LO               0xc4
 305
 306 /* scatter link table */
 307 #define TALITOS_SCATTER                 0xe0
 308 #define TALITOS_SCATTER_LO              0xe4
 309
 310 /* execution unit registers base */
 311 #define TALITOS2_DEU                    0x2000
 312 #define TALITOS2_AESU                   0x4000
 313 #define TALITOS2_MDEU                   0x6000
 314 #define TALITOS2_AFEU                   0x8000
 315 #define TALITOS2_RNGU                   0xa000
 316 #define TALITOS2_PKEU                   0xc000
 317 #define TALITOS2_KEU                    0xe000
 318 #define TALITOS2_CRCU                   0xf000
 319
 320 #define TALITOS12_AESU                  0x4000
 321 #define TALITOS12_DEU                   0x5000
 322 #define TALITOS12_MDEU                  0x6000
 323
 324 #define TALITOS10_AFEU                  0x8000
 325 #define TALITOS10_DEU                   0xa000
 326 #define TALITOS10_MDEU                  0xc000
 327 #define TALITOS10_RNGU                  0xe000
 328 #define TALITOS10_PKEU                  0x10000
 329 #define TALITOS10_AESU                  0x12000
 330
 331 /* execution unit interrupt status registers */
 332 #define TALITOS_EUDSR                   0x10    /* data size */
 333 #define TALITOS_EUDSR_LO                0x14
 334 #define TALITOS_EURCR                   0x18 /* reset control*/
 335 #define TALITOS_EURCR_LO                0x1c
 336 #define TALITOS_EUSR                    0x28 /* rng status */
 337 #define TALITOS_EUSR_LO                 0x2c
 338 #define TALITOS_EUISR                   0x30
 339 #define TALITOS_EUISR_LO                0x34
 340 #define TALITOS_EUICR                   0x38 /* int. control */
 341 #define TALITOS_EUICR_LO                0x3c
 342 #define TALITOS_EU_FIFO                 0x800 /* output FIFO */
 343 #define TALITOS_EU_FIFO_LO              0x804 /* output FIFO */
 344 /* DES unit */
 345 #define   TALITOS1_DEUICR_KPE           0x00200000 /* Key Parity Error */
 346 /* message digest unit */
 347 #define   TALITOS_MDEUICR_LO_ICE        0x4000 /* integrity check IRQ enable */
 348 /* random number unit */
 349 #define   TALITOS_RNGUSR_LO_RD          0x1     /* reset done */
 350 #define   TALITOS_RNGUSR_LO_OFL         0xff0000/* output FIFO length */
 351 #define   TALITOS_RNGURCR_LO_SR         0x1     /* software reset */
 352
 353 #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256       0x28
 354 #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512         0x48
 355
 356 /*
 357  * talitos descriptor header (hdr) bits
 358  */
 359
 360 /* written back when done */
 361 #define DESC_HDR_DONE                   cpu_to_be32(0xff000000)
 362 #define DESC_HDR_LO_ICCR1_MASK          cpu_to_be32(0x00180000)
 363 #define DESC_HDR_LO_ICCR1_PASS          cpu_to_be32(0x00080000)
 364 #define DESC_HDR_LO_ICCR1_FAIL          cpu_to_be32(0x00100000)
 365
 366 /* primary execution unit select */
 367 #define DESC_HDR_SEL0_MASK              cpu_to_be32(0xf0000000)
 368 #define DESC_HDR_SEL0_AFEU              cpu_to_be32(0x10000000)
 369 #define DESC_HDR_SEL0_DEU               cpu_to_be32(0x20000000)
 370 #define DESC_HDR_SEL0_MDEUA             cpu_to_be32(0x30000000)
 371 #define DESC_HDR_SEL0_MDEUB             cpu_to_be32(0xb0000000)
 372 #define DESC_HDR_SEL0_RNG               cpu_to_be32(0x40000000)
 373 #define DESC_HDR_SEL0_PKEU              cpu_to_be32(0x50000000)
 374 #define DESC_HDR_SEL0_AESU              cpu_to_be32(0x60000000)
 375 #define DESC_HDR_SEL0_KEU               cpu_to_be32(0x70000000)
 376 #define DESC_HDR_SEL0_CRCU              cpu_to_be32(0x80000000)
 377
 378 /* primary execution unit mode (MODE0) and derivatives */
 379 #define DESC_HDR_MODE0_ENCRYPT          cpu_to_be32(0x00100000)
 380 #define DESC_HDR_MODE0_AESU_CBC         cpu_to_be32(0x00200000)
 381 #define DESC_HDR_MODE0_AESU_CTR         cpu_to_be32(0x00600000)
 382 #define DESC_HDR_MODE0_DEU_CBC          cpu_to_be32(0x00400000)
 383 #define DESC_HDR_MODE0_DEU_3DES         cpu_to_be32(0x00200000)
 384 #define DESC_HDR_MODE0_MDEU_CONT        cpu_to_be32(0x08000000)
 385 #define DESC_HDR_MODE0_MDEU_INIT        cpu_to_be32(0x01000000)
 386 #define DESC_HDR_MODE0_MDEU_HMAC        cpu_to_be32(0x00800000)
 387 #define DESC_HDR_MODE0_MDEU_PAD         cpu_to_be32(0x00400000)
 388 #define DESC_HDR_MODE0_MDEU_SHA224      cpu_to_be32(0x00300000)
 389 #define DESC_HDR_MODE0_MDEU_MD5         cpu_to_be32(0x00200000)
 390 #define DESC_HDR_MODE0_MDEU_SHA256      cpu_to_be32(0x00100000)
 391 #define DESC_HDR_MODE0_MDEU_SHA1        cpu_to_be32(0x00000000)
 392 #define DESC_HDR_MODE0_MDEUB_SHA384     cpu_to_be32(0x00000000)
 393 #define DESC_HDR_MODE0_MDEUB_SHA512     cpu_to_be32(0x00200000)
 394 #define DESC_HDR_MODE0_MDEU_MD5_HMAC    (DESC_HDR_MODE0_MDEU_MD5 | \
 395                                          DESC_HDR_MODE0_MDEU_HMAC)
 396 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
 397                                          DESC_HDR_MODE0_MDEU_HMAC)
 398 #define DESC_HDR_MODE0_MDEU_SHA1_HMAC   (DESC_HDR_MODE0_MDEU_SHA1 | \
 399                                          DESC_HDR_MODE0_MDEU_HMAC)
 400
 401 /* secondary execution unit select (SEL1) */
 402 #define DESC_HDR_SEL1_MASK              cpu_to_be32(0x000f0000)
 403 #define DESC_HDR_SEL1_MDEUA             cpu_to_be32(0x00030000)
 404 #define DESC_HDR_SEL1_MDEUB             cpu_to_be32(0x000b0000)
 405 #define DESC_HDR_SEL1_CRCU              cpu_to_be32(0x00080000)
 406
 407 /* secondary execution unit mode (MODE1) and derivatives */
 408 #define DESC_HDR_MODE1_MDEU_CICV        cpu_to_be32(0x00004000)
 409 #define DESC_HDR_MODE1_MDEU_INIT        cpu_to_be32(0x00001000)
 410 #define DESC_HDR_MODE1_MDEU_HMAC        cpu_to_be32(0x00000800)
 411 #define DESC_HDR_MODE1_MDEU_PAD         cpu_to_be32(0x00000400)
 412 #define DESC_HDR_MODE1_MDEU_SHA224      cpu_to_be32(0x00000300)
 413 #define DESC_HDR_MODE1_MDEU_MD5         cpu_to_be32(0x00000200)
 414 #define DESC_HDR_MODE1_MDEU_SHA256      cpu_to_be32(0x00000100)
 415 #define DESC_HDR_MODE1_MDEU_SHA1        cpu_to_be32(0x00000000)
 416 #define DESC_HDR_MODE1_MDEUB_SHA384     cpu_to_be32(0x00000000)
 417 #define DESC_HDR_MODE1_MDEUB_SHA512     cpu_to_be32(0x00000200)
 418 #define DESC_HDR_MODE1_MDEU_MD5_HMAC    (DESC_HDR_MODE1_MDEU_MD5 | \
 419                                          DESC_HDR_MODE1_MDEU_HMAC)
 420 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
 421                                          DESC_HDR_MODE1_MDEU_HMAC)
 422 #define DESC_HDR_MODE1_MDEU_SHA1_HMAC   (DESC_HDR_MODE1_MDEU_SHA1 | \
 423                                          DESC_HDR_MODE1_MDEU_HMAC)
 424 #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
 425                                          DESC_HDR_MODE1_MDEU_HMAC)
 426 #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC        (DESC_HDR_MODE1_MDEUB_SHA384 | \
 427                                                  DESC_HDR_MODE1_MDEU_HMAC)
 428 #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC        (DESC_HDR_MODE1_MDEUB_SHA512 | \
 429                                                  DESC_HDR_MODE1_MDEU_HMAC)
 430
 431 /* direction of overall data flow (DIR) */
 432 #define DESC_HDR_DIR_INBOUND            cpu_to_be32(0x00000002)
 433
 434 /* request done notification (DN) */
 435 #define DESC_HDR_DONE_NOTIFY            cpu_to_be32(0x00000001)
 436
 437 /* descriptor types */
 438 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP         cpu_to_be32(0 << 3)
 439 #define DESC_HDR_TYPE_IPSEC_ESP                 cpu_to_be32(1 << 3)
 440 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU   cpu_to_be32(2 << 3)
 441 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU        cpu_to_be32(4 << 3)
 442
 443 /* link table extent field bits */
 444 #define DESC_PTR_LNKTBL_JUMP                    0x80
 445 #define DESC_PTR_LNKTBL_RET                     0x02
 446 #define DESC_PTR_LNKTBL_NEXT                    0x01