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Linux 4.19.133
[linux/fpc-iii.git] / drivers / dma / k3dma.c
blobba3c3791f9dc5e6dde0c5a34e39728500119ed25
1 /*
2 * Copyright (c) 2013 - 2015 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9 #include <linux/sched.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmapool.h>
13 #include <linux/dmaengine.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21 #include <linux/of_device.h>
22 #include <linux/of.h>
23 #include <linux/clk.h>
24 #include <linux/of_dma.h>
25
26 #include "virt-dma.h"
27
28 #define DRIVER_NAME "k3-dma"
29 #define DMA_MAX_SIZE 0x1ffc
30 #define DMA_CYCLIC_MAX_PERIOD 0x1000
31 #define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
32
33 #define INT_STAT 0x00
34 #define INT_TC1 0x04
35 #define INT_TC2 0x08
36 #define INT_ERR1 0x0c
37 #define INT_ERR2 0x10
38 #define INT_TC1_MASK 0x18
39 #define INT_TC2_MASK 0x1c
40 #define INT_ERR1_MASK 0x20
41 #define INT_ERR2_MASK 0x24
42 #define INT_TC1_RAW 0x600
43 #define INT_TC2_RAW 0x608
44 #define INT_ERR1_RAW 0x610
45 #define INT_ERR2_RAW 0x618
46 #define CH_PRI 0x688
47 #define CH_STAT 0x690
48 #define CX_CUR_CNT 0x704
49 #define CX_LLI 0x800
50 #define CX_CNT1 0x80c
51 #define CX_CNT0 0x810
52 #define CX_SRC 0x814
53 #define CX_DST 0x818
54 #define CX_CFG 0x81c
55 #define AXI_CFG 0x820
56 #define AXI_CFG_DEFAULT 0x201201
57
58 #define CX_LLI_CHAIN_EN 0x2
59 #define CX_CFG_EN 0x1
60 #define CX_CFG_NODEIRQ BIT(1)
61 #define CX_CFG_MEM2PER (0x1 << 2)
62 #define CX_CFG_PER2MEM (0x2 << 2)
63 #define CX_CFG_SRCINCR (0x1 << 31)
64 #define CX_CFG_DSTINCR (0x1 << 30)
65
66 struct k3_desc_hw {
67 u32 lli;
68 u32 reserved[3];
69 u32 count;
70 u32 saddr;
71 u32 daddr;
72 u32 config;
73 } __aligned(32);
74
75 struct k3_dma_desc_sw {
76 struct virt_dma_desc vd;
77 dma_addr_t desc_hw_lli;
78 size_t desc_num;
79 size_t size;
80 struct k3_desc_hw *desc_hw;
81 };
82
83 struct k3_dma_phy;
84
85 struct k3_dma_chan {
86 u32 ccfg;
87 struct virt_dma_chan vc;
88 struct k3_dma_phy *phy;
89 struct list_head node;
90 enum dma_transfer_direction dir;
91 dma_addr_t dev_addr;
92 enum dma_status status;
93 bool cyclic;
94 };
95
96 struct k3_dma_phy {
97 u32 idx;
98 void __iomem *base;
99 struct k3_dma_chan *vchan;
100 struct k3_dma_desc_sw *ds_run;
101 struct k3_dma_desc_sw *ds_done;
102 };
103
104 struct k3_dma_dev {
105 struct dma_device slave;
106 void __iomem *base;
107 struct tasklet_struct task;
108 spinlock_t lock;
109 struct list_head chan_pending;
110 struct k3_dma_phy *phy;
111 struct k3_dma_chan *chans;
112 struct clk *clk;
113 struct dma_pool *pool;
114 u32 dma_channels;
115 u32 dma_requests;
116 unsigned int irq;
117 };
118
119 #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
120
121 static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
122 {
123 return container_of(chan, struct k3_dma_chan, vc.chan);
124 }
125
126 static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
127 {
128 u32 val = 0;
129
130 if (on) {
131 val = readl_relaxed(phy->base + CX_CFG);
132 val |= CX_CFG_EN;
133 writel_relaxed(val, phy->base + CX_CFG);
134 } else {
135 val = readl_relaxed(phy->base + CX_CFG);
136 val &= ~CX_CFG_EN;
137 writel_relaxed(val, phy->base + CX_CFG);
138 }
139 }
140
141 static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
142 {
143 u32 val = 0;
144
145 k3_dma_pause_dma(phy, false);
146
147 val = 0x1 << phy->idx;
148 writel_relaxed(val, d->base + INT_TC1_RAW);
149 writel_relaxed(val, d->base + INT_TC2_RAW);
150 writel_relaxed(val, d->base + INT_ERR1_RAW);
151 writel_relaxed(val, d->base + INT_ERR2_RAW);
152 }
153
154 static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
155 {
156 writel_relaxed(hw->lli, phy->base + CX_LLI);
157 writel_relaxed(hw->count, phy->base + CX_CNT0);
158 writel_relaxed(hw->saddr, phy->base + CX_SRC);
159 writel_relaxed(hw->daddr, phy->base + CX_DST);
160 writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
161 writel_relaxed(hw->config, phy->base + CX_CFG);
162 }
163
164 static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
165 {
166 u32 cnt = 0;
167
168 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
169 cnt &= 0xffff;
170 return cnt;
171 }
172
173 static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
174 {
175 return readl_relaxed(phy->base + CX_LLI);
176 }
177
178 static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
179 {
180 return readl_relaxed(d->base + CH_STAT);
181 }
182
183 static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
184 {
185 if (on) {
186 /* set same priority */
187 writel_relaxed(0x0, d->base + CH_PRI);
188
189 /* unmask irq */
190 writel_relaxed(0xffff, d->base + INT_TC1_MASK);
191 writel_relaxed(0xffff, d->base + INT_TC2_MASK);
192 writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
193 writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
194 } else {
195 /* mask irq */
196 writel_relaxed(0x0, d->base + INT_TC1_MASK);
197 writel_relaxed(0x0, d->base + INT_TC2_MASK);
198 writel_relaxed(0x0, d->base + INT_ERR1_MASK);
199 writel_relaxed(0x0, d->base + INT_ERR2_MASK);
200 }
201 }
202
203 static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
204 {
205 struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
206 struct k3_dma_phy *p;
207 struct k3_dma_chan *c;
208 u32 stat = readl_relaxed(d->base + INT_STAT);
209 u32 tc1 = readl_relaxed(d->base + INT_TC1);
210 u32 tc2 = readl_relaxed(d->base + INT_TC2);
211 u32 err1 = readl_relaxed(d->base + INT_ERR1);
212 u32 err2 = readl_relaxed(d->base + INT_ERR2);
213 u32 i, irq_chan = 0;
214
215 while (stat) {
216 i = __ffs(stat);
217 stat &= ~BIT(i);
218 if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) {
219 unsigned long flags;
220
221 p = &d->phy[i];
222 c = p->vchan;
223 if (c && (tc1 & BIT(i))) {
224 spin_lock_irqsave(&c->vc.lock, flags);
225 if (p->ds_run != NULL) {
226 vchan_cookie_complete(&p->ds_run->vd);
227 p->ds_done = p->ds_run;
228 p->ds_run = NULL;
229 }
230 spin_unlock_irqrestore(&c->vc.lock, flags);
231 }
232 if (c && (tc2 & BIT(i))) {
233 spin_lock_irqsave(&c->vc.lock, flags);
234 if (p->ds_run != NULL)
235 vchan_cyclic_callback(&p->ds_run->vd);
236 spin_unlock_irqrestore(&c->vc.lock, flags);
237 }
238 irq_chan |= BIT(i);
239 }
240 if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
241 dev_warn(d->slave.dev, "DMA ERR\n");
242 }
243
244 writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
245 writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
246 writel_relaxed(err1, d->base + INT_ERR1_RAW);
247 writel_relaxed(err2, d->base + INT_ERR2_RAW);
248
249 if (irq_chan)
250 tasklet_schedule(&d->task);
251
252 if (irq_chan || err1 || err2)
253 return IRQ_HANDLED;
254
255 return IRQ_NONE;
256 }
257
258 static int k3_dma_start_txd(struct k3_dma_chan *c)
259 {
260 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
261 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
262
263 if (!c->phy)
264 return -EAGAIN;
265
266 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
267 return -EAGAIN;
268
269 /* Avoid losing track of ds_run if a transaction is in flight */
270 if (c->phy->ds_run)
271 return -EAGAIN;
272
273 if (vd) {
274 struct k3_dma_desc_sw *ds =
275 container_of(vd, struct k3_dma_desc_sw, vd);
276 /*
277 * fetch and remove request from vc->desc_issued
278 * so vc->desc_issued only contains desc pending
279 */
280 list_del(&ds->vd.node);
281
282 c->phy->ds_run = ds;
283 c->phy->ds_done = NULL;
284 /* start dma */
285 k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
286 return 0;
287 }
288 c->phy->ds_run = NULL;
289 c->phy->ds_done = NULL;
290 return -EAGAIN;
291 }
292
293 static void k3_dma_tasklet(unsigned long arg)
294 {
295 struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
296 struct k3_dma_phy *p;
297 struct k3_dma_chan *c, *cn;
298 unsigned pch, pch_alloc = 0;
299
300 /* check new dma request of running channel in vc->desc_issued */
301 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
302 spin_lock_irq(&c->vc.lock);
303 p = c->phy;
304 if (p && p->ds_done) {
305 if (k3_dma_start_txd(c)) {
306 /* No current txd associated with this channel */
307 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
308 /* Mark this channel free */
309 c->phy = NULL;
310 p->vchan = NULL;
311 }
312 }
313 spin_unlock_irq(&c->vc.lock);
314 }
315
316 /* check new channel request in d->chan_pending */
317 spin_lock_irq(&d->lock);
318 for (pch = 0; pch < d->dma_channels; pch++) {
319 p = &d->phy[pch];
320
321 if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
322 c = list_first_entry(&d->chan_pending,
323 struct k3_dma_chan, node);
324 /* remove from d->chan_pending */
325 list_del_init(&c->node);
326 pch_alloc |= 1 << pch;
327 /* Mark this channel allocated */
328 p->vchan = c;
329 c->phy = p;
330 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
331 }
332 }
333 spin_unlock_irq(&d->lock);
334
335 for (pch = 0; pch < d->dma_channels; pch++) {
336 if (pch_alloc & (1 << pch)) {
337 p = &d->phy[pch];
338 c = p->vchan;
339 if (c) {
340 spin_lock_irq(&c->vc.lock);
341 k3_dma_start_txd(c);
342 spin_unlock_irq(&c->vc.lock);
343 }
344 }
345 }
346 }
347
348 static void k3_dma_free_chan_resources(struct dma_chan *chan)
349 {
350 struct k3_dma_chan *c = to_k3_chan(chan);
351 struct k3_dma_dev *d = to_k3_dma(chan->device);
352 unsigned long flags;
353
354 spin_lock_irqsave(&d->lock, flags);
355 list_del_init(&c->node);
356 spin_unlock_irqrestore(&d->lock, flags);
357
358 vchan_free_chan_resources(&c->vc);
359 c->ccfg = 0;
360 }
361
362 static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
363 dma_cookie_t cookie, struct dma_tx_state *state)
364 {
365 struct k3_dma_chan *c = to_k3_chan(chan);
366 struct k3_dma_dev *d = to_k3_dma(chan->device);
367 struct k3_dma_phy *p;
368 struct virt_dma_desc *vd;
369 unsigned long flags;
370 enum dma_status ret;
371 size_t bytes = 0;
372
373 ret = dma_cookie_status(&c->vc.chan, cookie, state);
374 if (ret == DMA_COMPLETE)
375 return ret;
376
377 spin_lock_irqsave(&c->vc.lock, flags);
378 p = c->phy;
379 ret = c->status;
380
381 /*
382 * If the cookie is on our issue queue, then the residue is
383 * its total size.
384 */
385 vd = vchan_find_desc(&c->vc, cookie);
386 if (vd && !c->cyclic) {
387 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
388 } else if ((!p) || (!p->ds_run)) {
389 bytes = 0;
390 } else {
391 struct k3_dma_desc_sw *ds = p->ds_run;
392 u32 clli = 0, index = 0;
393
394 bytes = k3_dma_get_curr_cnt(d, p);
395 clli = k3_dma_get_curr_lli(p);
396 index = ((clli - ds->desc_hw_lli) /
397 sizeof(struct k3_desc_hw)) + 1;
398 for (; index < ds->desc_num; index++) {
399 bytes += ds->desc_hw[index].count;
400 /* end of lli */
401 if (!ds->desc_hw[index].lli)
402 break;
403 }
404 }
405 spin_unlock_irqrestore(&c->vc.lock, flags);
406 dma_set_residue(state, bytes);
407 return ret;
408 }
409
410 static void k3_dma_issue_pending(struct dma_chan *chan)
411 {
412 struct k3_dma_chan *c = to_k3_chan(chan);
413 struct k3_dma_dev *d = to_k3_dma(chan->device);
414 unsigned long flags;
415
416 spin_lock_irqsave(&c->vc.lock, flags);
417 /* add request to vc->desc_issued */
418 if (vchan_issue_pending(&c->vc)) {
419 spin_lock(&d->lock);
420 if (!c->phy) {
421 if (list_empty(&c->node)) {
422 /* if new channel, add chan_pending */
423 list_add_tail(&c->node, &d->chan_pending);
424 /* check in tasklet */
425 tasklet_schedule(&d->task);
426 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
427 }
428 }
429 spin_unlock(&d->lock);
430 } else
431 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
432 spin_unlock_irqrestore(&c->vc.lock, flags);
433 }
434
435 static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
436 dma_addr_t src, size_t len, u32 num, u32 ccfg)
437 {
438 if (num != ds->desc_num - 1)
439 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
440 sizeof(struct k3_desc_hw);
441
442 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
443 ds->desc_hw[num].count = len;
444 ds->desc_hw[num].saddr = src;
445 ds->desc_hw[num].daddr = dst;
446 ds->desc_hw[num].config = ccfg;
447 }
448
449 static struct k3_dma_desc_sw *k3_dma_alloc_desc_resource(int num,
450 struct dma_chan *chan)
451 {
452 struct k3_dma_chan *c = to_k3_chan(chan);
453 struct k3_dma_desc_sw *ds;
454 struct k3_dma_dev *d = to_k3_dma(chan->device);
455 int lli_limit = LLI_BLOCK_SIZE / sizeof(struct k3_desc_hw);
456
457 if (num > lli_limit) {
458 dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n",
459 &c->vc, num, lli_limit);
460 return NULL;
461 }
462
463 ds = kzalloc(sizeof(*ds), GFP_NOWAIT);
464 if (!ds)
465 return NULL;
466
467 ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli);
468 if (!ds->desc_hw) {
469 dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc);
470 kfree(ds);
471 return NULL;
472 }
473 ds->desc_num = num;
474 return ds;
475 }
476
477 static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
478 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
479 size_t len, unsigned long flags)
480 {
481 struct k3_dma_chan *c = to_k3_chan(chan);
482 struct k3_dma_desc_sw *ds;
483 size_t copy = 0;
484 int num = 0;
485
486 if (!len)
487 return NULL;
488
489 num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
490
491 ds = k3_dma_alloc_desc_resource(num, chan);
492 if (!ds)
493 return NULL;
494
495 c->cyclic = 0;
496 ds->size = len;
497 num = 0;
498
499 if (!c->ccfg) {
500 /* default is memtomem, without calling device_config */
501 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
502 c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
503 c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
504 }
505
506 do {
507 copy = min_t(size_t, len, DMA_MAX_SIZE);
508 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
509
510 if (c->dir == DMA_MEM_TO_DEV) {
511 src += copy;
512 } else if (c->dir == DMA_DEV_TO_MEM) {
513 dst += copy;
514 } else {
515 src += copy;
516 dst += copy;
517 }
518 len -= copy;
519 } while (len);
520
521 ds->desc_hw[num-1].lli = 0; /* end of link */
522 return vchan_tx_prep(&c->vc, &ds->vd, flags);
523 }
524
525 static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
526 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
527 enum dma_transfer_direction dir, unsigned long flags, void *context)
528 {
529 struct k3_dma_chan *c = to_k3_chan(chan);
530 struct k3_dma_desc_sw *ds;
531 size_t len, avail, total = 0;
532 struct scatterlist *sg;
533 dma_addr_t addr, src = 0, dst = 0;
534 int num = sglen, i;
535
536 if (sgl == NULL)
537 return NULL;
538
539 c->cyclic = 0;
540
541 for_each_sg(sgl, sg, sglen, i) {
542 avail = sg_dma_len(sg);
543 if (avail > DMA_MAX_SIZE)
544 num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
545 }
546
547 ds = k3_dma_alloc_desc_resource(num, chan);
548 if (!ds)
549 return NULL;
550 num = 0;
551
552 for_each_sg(sgl, sg, sglen, i) {
553 addr = sg_dma_address(sg);
554 avail = sg_dma_len(sg);
555 total += avail;
556
557 do {
558 len = min_t(size_t, avail, DMA_MAX_SIZE);
559
560 if (dir == DMA_MEM_TO_DEV) {
561 src = addr;
562 dst = c->dev_addr;
563 } else if (dir == DMA_DEV_TO_MEM) {
564 src = c->dev_addr;
565 dst = addr;
566 }
567
568 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
569
570 addr += len;
571 avail -= len;
572 } while (avail);
573 }
574
575 ds->desc_hw[num-1].lli = 0; /* end of link */
576 ds->size = total;
577 return vchan_tx_prep(&c->vc, &ds->vd, flags);
578 }
579
580 static struct dma_async_tx_descriptor *
581 k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
582 size_t buf_len, size_t period_len,
583 enum dma_transfer_direction dir,
584 unsigned long flags)
585 {
586 struct k3_dma_chan *c = to_k3_chan(chan);
587 struct k3_dma_desc_sw *ds;
588 size_t len, avail, total = 0;
589 dma_addr_t addr, src = 0, dst = 0;
590 int num = 1, since = 0;
591 size_t modulo = DMA_CYCLIC_MAX_PERIOD;
592 u32 en_tc2 = 0;
593
594 dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n",
595 __func__, &buf_addr, &to_k3_chan(chan)->dev_addr,
596 buf_len, period_len, (int)dir);
597
598 avail = buf_len;
599 if (avail > modulo)
600 num += DIV_ROUND_UP(avail, modulo) - 1;
601
602 ds = k3_dma_alloc_desc_resource(num, chan);
603 if (!ds)
604 return NULL;
605
606 c->cyclic = 1;
607 addr = buf_addr;
608 avail = buf_len;
609 total = avail;
610 num = 0;
611
612 if (period_len < modulo)
613 modulo = period_len;
614
615 do {
616 len = min_t(size_t, avail, modulo);
617
618 if (dir == DMA_MEM_TO_DEV) {
619 src = addr;
620 dst = c->dev_addr;
621 } else if (dir == DMA_DEV_TO_MEM) {
622 src = c->dev_addr;
623 dst = addr;
624 }
625 since += len;
626 if (since >= period_len) {
627 /* descriptor asks for TC2 interrupt on completion */
628 en_tc2 = CX_CFG_NODEIRQ;
629 since -= period_len;
630 } else
631 en_tc2 = 0;
632
633 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2);
634
635 addr += len;
636 avail -= len;
637 } while (avail);
638
639 /* "Cyclic" == end of link points back to start of link */
640 ds->desc_hw[num - 1].lli |= ds->desc_hw_lli;
641
642 ds->size = total;
643
644 return vchan_tx_prep(&c->vc, &ds->vd, flags);
645 }
646
647 static int k3_dma_config(struct dma_chan *chan,
648 struct dma_slave_config *cfg)
649 {
650 struct k3_dma_chan *c = to_k3_chan(chan);
651 u32 maxburst = 0, val = 0;
652 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
653
654 if (cfg == NULL)
655 return -EINVAL;
656 c->dir = cfg->direction;
657 if (c->dir == DMA_DEV_TO_MEM) {
658 c->ccfg = CX_CFG_DSTINCR;
659 c->dev_addr = cfg->src_addr;
660 maxburst = cfg->src_maxburst;
661 width = cfg->src_addr_width;
662 } else if (c->dir == DMA_MEM_TO_DEV) {
663 c->ccfg = CX_CFG_SRCINCR;
664 c->dev_addr = cfg->dst_addr;
665 maxburst = cfg->dst_maxburst;
666 width = cfg->dst_addr_width;
667 }
668 switch (width) {
669 case DMA_SLAVE_BUSWIDTH_1_BYTE:
670 case DMA_SLAVE_BUSWIDTH_2_BYTES:
671 case DMA_SLAVE_BUSWIDTH_4_BYTES:
672 case DMA_SLAVE_BUSWIDTH_8_BYTES:
673 val = __ffs(width);
674 break;
675 default:
676 val = 3;
677 break;
678 }
679 c->ccfg |= (val << 12) | (val << 16);
680
681 if ((maxburst == 0) || (maxburst > 16))
682 val = 15;
683 else
684 val = maxburst - 1;
685 c->ccfg |= (val << 20) | (val << 24);
686 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
687
688 /* specific request line */
689 c->ccfg |= c->vc.chan.chan_id << 4;
690
691 return 0;
692 }
693
694 static void k3_dma_free_desc(struct virt_dma_desc *vd)
695 {
696 struct k3_dma_desc_sw *ds =
697 container_of(vd, struct k3_dma_desc_sw, vd);
698 struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device);
699
700 dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli);
701 kfree(ds);
702 }
703
704 static int k3_dma_terminate_all(struct dma_chan *chan)
705 {
706 struct k3_dma_chan *c = to_k3_chan(chan);
707 struct k3_dma_dev *d = to_k3_dma(chan->device);
708 struct k3_dma_phy *p = c->phy;
709 unsigned long flags;
710 LIST_HEAD(head);
711
712 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
713
714 /* Prevent this channel being scheduled */
715 spin_lock(&d->lock);
716 list_del_init(&c->node);
717 spin_unlock(&d->lock);
718
719 /* Clear the tx descriptor lists */
720 spin_lock_irqsave(&c->vc.lock, flags);
721 vchan_get_all_descriptors(&c->vc, &head);
722 if (p) {
723 /* vchan is assigned to a pchan - stop the channel */
724 k3_dma_terminate_chan(p, d);
725 c->phy = NULL;
726 p->vchan = NULL;
727 if (p->ds_run) {
728 vchan_terminate_vdesc(&p->ds_run->vd);
729 p->ds_run = NULL;
730 }
731 p->ds_done = NULL;
732 }
733 spin_unlock_irqrestore(&c->vc.lock, flags);
734 vchan_dma_desc_free_list(&c->vc, &head);
735
736 return 0;
737 }
738
739 static void k3_dma_synchronize(struct dma_chan *chan)
740 {
741 struct k3_dma_chan *c = to_k3_chan(chan);
742
743 vchan_synchronize(&c->vc);
744 }
745
746 static int k3_dma_transfer_pause(struct dma_chan *chan)
747 {
748 struct k3_dma_chan *c = to_k3_chan(chan);
749 struct k3_dma_dev *d = to_k3_dma(chan->device);
750 struct k3_dma_phy *p = c->phy;
751
752 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
753 if (c->status == DMA_IN_PROGRESS) {
754 c->status = DMA_PAUSED;
755 if (p) {
756 k3_dma_pause_dma(p, false);
757 } else {
758 spin_lock(&d->lock);
759 list_del_init(&c->node);
760 spin_unlock(&d->lock);
761 }
762 }
763
764 return 0;
765 }
766
767 static int k3_dma_transfer_resume(struct dma_chan *chan)
768 {
769 struct k3_dma_chan *c = to_k3_chan(chan);
770 struct k3_dma_dev *d = to_k3_dma(chan->device);
771 struct k3_dma_phy *p = c->phy;
772 unsigned long flags;
773
774 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
775 spin_lock_irqsave(&c->vc.lock, flags);
776 if (c->status == DMA_PAUSED) {
777 c->status = DMA_IN_PROGRESS;
778 if (p) {
779 k3_dma_pause_dma(p, true);
780 } else if (!list_empty(&c->vc.desc_issued)) {
781 spin_lock(&d->lock);
782 list_add_tail(&c->node, &d->chan_pending);
783 spin_unlock(&d->lock);
784 }
785 }
786 spin_unlock_irqrestore(&c->vc.lock, flags);
787
788 return 0;
789 }
790
791 static const struct of_device_id k3_pdma_dt_ids[] = {
792 { .compatible = "hisilicon,k3-dma-1.0", },
793 {}
794 };
795 MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
796
797 static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
798 struct of_dma *ofdma)
799 {
800 struct k3_dma_dev *d = ofdma->of_dma_data;
801 unsigned int request = dma_spec->args[0];
802
803 if (request >= d->dma_requests)
804 return NULL;
805
806 return dma_get_slave_channel(&(d->chans[request].vc.chan));
807 }
808
809 static int k3_dma_probe(struct platform_device *op)
810 {
811 struct k3_dma_dev *d;
812 const struct of_device_id *of_id;
813 struct resource *iores;
814 int i, ret, irq = 0;
815
816 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
817 if (!iores)
818 return -EINVAL;
819
820 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
821 if (!d)
822 return -ENOMEM;
823
824 d->base = devm_ioremap_resource(&op->dev, iores);
825 if (IS_ERR(d->base))
826 return PTR_ERR(d->base);
827
828 of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
829 if (of_id) {
830 of_property_read_u32((&op->dev)->of_node,
831 "dma-channels", &d->dma_channels);
832 of_property_read_u32((&op->dev)->of_node,
833 "dma-requests", &d->dma_requests);
834 }
835
836 d->clk = devm_clk_get(&op->dev, NULL);
837 if (IS_ERR(d->clk)) {
838 dev_err(&op->dev, "no dma clk\n");
839 return PTR_ERR(d->clk);
840 }
841
842 irq = platform_get_irq(op, 0);
843 ret = devm_request_irq(&op->dev, irq,
844 k3_dma_int_handler, 0, DRIVER_NAME, d);
845 if (ret)
846 return ret;
847
848 d->irq = irq;
849
850 /* A DMA memory pool for LLIs, align on 32-byte boundary */
851 d->pool = dmam_pool_create(DRIVER_NAME, &op->dev,
852 LLI_BLOCK_SIZE, 32, 0);
853 if (!d->pool)
854 return -ENOMEM;
855
856 /* init phy channel */
857 d->phy = devm_kcalloc(&op->dev,
858 d->dma_channels, sizeof(struct k3_dma_phy), GFP_KERNEL);
859 if (d->phy == NULL)
860 return -ENOMEM;
861
862 for (i = 0; i < d->dma_channels; i++) {
863 struct k3_dma_phy *p = &d->phy[i];
864
865 p->idx = i;
866 p->base = d->base + i * 0x40;
867 }
868
869 INIT_LIST_HEAD(&d->slave.channels);
870 dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
871 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
872 dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
873 d->slave.dev = &op->dev;
874 d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
875 d->slave.device_tx_status = k3_dma_tx_status;
876 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
877 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
878 d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic;
879 d->slave.device_issue_pending = k3_dma_issue_pending;
880 d->slave.device_config = k3_dma_config;
881 d->slave.device_pause = k3_dma_transfer_pause;
882 d->slave.device_resume = k3_dma_transfer_resume;
883 d->slave.device_terminate_all = k3_dma_terminate_all;
884 d->slave.device_synchronize = k3_dma_synchronize;
885 d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES;
886
887 /* init virtual channel */
888 d->chans = devm_kcalloc(&op->dev,
889 d->dma_requests, sizeof(struct k3_dma_chan), GFP_KERNEL);
890 if (d->chans == NULL)
891 return -ENOMEM;
892
893 for (i = 0; i < d->dma_requests; i++) {
894 struct k3_dma_chan *c = &d->chans[i];
895
896 c->status = DMA_IN_PROGRESS;
897 INIT_LIST_HEAD(&c->node);
898 c->vc.desc_free = k3_dma_free_desc;
899 vchan_init(&c->vc, &d->slave);
900 }
901
902 /* Enable clock before accessing registers */
903 ret = clk_prepare_enable(d->clk);
904 if (ret < 0) {
905 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
906 return ret;
907 }
908
909 k3_dma_enable_dma(d, true);
910
911 ret = dma_async_device_register(&d->slave);
912 if (ret)
913 goto dma_async_register_fail;
914
915 ret = of_dma_controller_register((&op->dev)->of_node,
916 k3_of_dma_simple_xlate, d);
917 if (ret)
918 goto of_dma_register_fail;
919
920 spin_lock_init(&d->lock);
921 INIT_LIST_HEAD(&d->chan_pending);
922 tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
923 platform_set_drvdata(op, d);
924 dev_info(&op->dev, "initialized\n");
925
926 return 0;
927
928 of_dma_register_fail:
929 dma_async_device_unregister(&d->slave);
930 dma_async_register_fail:
931 clk_disable_unprepare(d->clk);
932 return ret;
933 }
934
935 static int k3_dma_remove(struct platform_device *op)
936 {
937 struct k3_dma_chan *c, *cn;
938 struct k3_dma_dev *d = platform_get_drvdata(op);
939
940 dma_async_device_unregister(&d->slave);
941 of_dma_controller_free((&op->dev)->of_node);
942
943 devm_free_irq(&op->dev, d->irq, d);
944
945 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
946 list_del(&c->vc.chan.device_node);
947 tasklet_kill(&c->vc.task);
948 }
949 tasklet_kill(&d->task);
950 clk_disable_unprepare(d->clk);
951 return 0;
952 }
953
954 #ifdef CONFIG_PM_SLEEP
955 static int k3_dma_suspend_dev(struct device *dev)
956 {
957 struct k3_dma_dev *d = dev_get_drvdata(dev);
958 u32 stat = 0;
959
960 stat = k3_dma_get_chan_stat(d);
961 if (stat) {
962 dev_warn(d->slave.dev,
963 "chan %d is running fail to suspend\n", stat);
964 return -1;
965 }
966 k3_dma_enable_dma(d, false);
967 clk_disable_unprepare(d->clk);
968 return 0;
969 }
970
971 static int k3_dma_resume_dev(struct device *dev)
972 {
973 struct k3_dma_dev *d = dev_get_drvdata(dev);
974 int ret = 0;
975
976 ret = clk_prepare_enable(d->clk);
977 if (ret < 0) {
978 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
979 return ret;
980 }
981 k3_dma_enable_dma(d, true);
982 return 0;
983 }
984 #endif
985
986 static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev);
987
988 static struct platform_driver k3_pdma_driver = {
989 .driver = {
990 .name = DRIVER_NAME,
991 .pm = &k3_dma_pmops,
992 .of_match_table = k3_pdma_dt_ids,
993 },
994 .probe = k3_dma_probe,
995 .remove = k3_dma_remove,
996 };
997
998 module_platform_driver(k3_pdma_driver);
999
1000 MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
1001 MODULE_ALIAS("platform:k3dma");
1002 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support