?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / dma / pxa_dma.c
blobb31c28b67ad3ec6aef3babf5402defaac504f680
1 /*
2 * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/err.h>
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/interrupt.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/platform_data/mmp_dma.h>
20 #include <linux/dmapool.h>
21 #include <linux/of_device.h>
22 #include <linux/of_dma.h>
23 #include <linux/of.h>
24 #include <linux/wait.h>
25 #include <linux/dma/pxa-dma.h>
26
27 #include "dmaengine.h"
28 #include "virt-dma.h"
29
30 #define DCSR(n) (0x0000 + ((n) << 2))
31 #define DALGN(n) 0x00a0
32 #define DINT 0x00f0
33 #define DDADR(n) (0x0200 + ((n) << 4))
34 #define DSADR(n) (0x0204 + ((n) << 4))
35 #define DTADR(n) (0x0208 + ((n) << 4))
36 #define DCMD(n) (0x020c + ((n) << 4))
37
38 #define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */
39 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
40 #define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */
41 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
42 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
43 #define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */
44 #define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */
45 #define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */
46
47 #define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */
48 #define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */
49 #define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
50 #define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
51 #define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
52 #define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
53 #define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */
54
55 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */
56 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
57
58 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
59 #define DDADR_STOP BIT(0) /* Stop (read / write) */
60
61 #define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */
62 #define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */
63 #define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */
64 #define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */
65 #define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */
66 #define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */
67 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
68 #define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */
69 #define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */
70 #define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */
71 #define PXA_DCMD_WIDTH1 (1 << 14) /* 1 byte width */
72 #define PXA_DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
73 #define PXA_DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
74 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
75
76 #define PDMA_ALIGNMENT 3
77 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
78
79 struct pxad_desc_hw {
80 u32 ddadr; /* Points to the next descriptor + flags */
81 u32 dsadr; /* DSADR value for the current transfer */
82 u32 dtadr; /* DTADR value for the current transfer */
83 u32 dcmd; /* DCMD value for the current transfer */
84 } __aligned(16);
85
86 struct pxad_desc_sw {
87 struct virt_dma_desc vd; /* Virtual descriptor */
88 int nb_desc; /* Number of hw. descriptors */
89 size_t len; /* Number of bytes xfered */
90 dma_addr_t first; /* First descriptor's addr */
91
92 /* At least one descriptor has an src/dst address not multiple of 8 */
93 bool misaligned;
94 bool cyclic;
95 struct dma_pool *desc_pool; /* Channel's used allocator */
96
97 struct pxad_desc_hw *hw_desc[]; /* DMA coherent descriptors */
98 };
99
100 struct pxad_phy {
101 int idx;
102 void __iomem *base;
103 struct pxad_chan *vchan;
104 };
105
106 struct pxad_chan {
107 struct virt_dma_chan vc; /* Virtual channel */
108 u32 drcmr; /* Requestor of the channel */
109 enum pxad_chan_prio prio; /* Required priority of phy */
110 /*
111 * At least one desc_sw in submitted or issued transfers on this channel
112 * has one address such as: addr % 8 != 0. This implies the DALGN
113 * setting on the phy.
114 */
115 bool misaligned;
116 struct dma_slave_config cfg; /* Runtime config */
117
118 /* protected by vc->lock */
119 struct pxad_phy *phy;
120 struct dma_pool *desc_pool; /* Descriptors pool */
121 dma_cookie_t bus_error;
122
123 wait_queue_head_t wq_state;
124 };
125
126 struct pxad_device {
127 struct dma_device slave;
128 int nr_chans;
129 int nr_requestors;
130 void __iomem *base;
131 struct pxad_phy *phys;
132 spinlock_t phy_lock; /* Phy association */
133 #ifdef CONFIG_DEBUG_FS
134 struct dentry *dbgfs_root;
135 struct dentry *dbgfs_state;
136 struct dentry **dbgfs_chan;
137 #endif
138 };
139
140 #define tx_to_pxad_desc(tx) \
141 container_of(tx, struct pxad_desc_sw, async_tx)
142 #define to_pxad_chan(dchan) \
143 container_of(dchan, struct pxad_chan, vc.chan)
144 #define to_pxad_dev(dmadev) \
145 container_of(dmadev, struct pxad_device, slave)
146 #define to_pxad_sw_desc(_vd) \
147 container_of((_vd), struct pxad_desc_sw, vd)
148
149 #define _phy_readl_relaxed(phy, _reg) \
150 readl_relaxed((phy)->base + _reg((phy)->idx))
151 #define phy_readl_relaxed(phy, _reg) \
152 ({ \
153 u32 _v; \
154 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \
155 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
156 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \
157 _v); \
158 _v; \
159 })
160 #define phy_writel(phy, val, _reg) \
161 do { \
162 writel((val), (phy)->base + _reg((phy)->idx)); \
163 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
164 "%s(): writel(0x%08x, %s)\n", \
165 __func__, (u32)(val), #_reg); \
166 } while (0)
167 #define phy_writel_relaxed(phy, val, _reg) \
168 do { \
169 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \
170 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
171 "%s(): writel_relaxed(0x%08x, %s)\n", \
172 __func__, (u32)(val), #_reg); \
173 } while (0)
174
175 static unsigned int pxad_drcmr(unsigned int line)
176 {
177 if (line < 64)
178 return 0x100 + line * 4;
179 return 0x1000 + line * 4;
180 }
181
182 bool pxad_filter_fn(struct dma_chan *chan, void *param);
183
184 /*
185 * Debug fs
186 */
187 #ifdef CONFIG_DEBUG_FS
188 #include <linux/debugfs.h>
189 #include <linux/uaccess.h>
190 #include <linux/seq_file.h>
191
192 static int dbg_show_requester_chan(struct seq_file *s, void *p)
193 {
194 struct pxad_phy *phy = s->private;
195 int i;
196 u32 drcmr;
197
198 seq_printf(s, "DMA channel %d requester :\n", phy->idx);
199 for (i = 0; i < 70; i++) {
200 drcmr = readl_relaxed(phy->base + pxad_drcmr(i));
201 if ((drcmr & DRCMR_CHLNUM) == phy->idx)
202 seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,
203 !!(drcmr & DRCMR_MAPVLD));
204 }
205 return 0;
206 }
207
208 static inline int dbg_burst_from_dcmd(u32 dcmd)
209 {
210 int burst = (dcmd >> 16) & 0x3;
211
212 return burst ? 4 << burst : 0;
213 }
214
215 static int is_phys_valid(unsigned long addr)
216 {
217 return pfn_valid(__phys_to_pfn(addr));
218 }
219
220 #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "")
221 #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "")
222
223 static int dbg_show_descriptors(struct seq_file *s, void *p)
224 {
225 struct pxad_phy *phy = s->private;
226 int i, max_show = 20, burst, width;
227 u32 dcmd;
228 unsigned long phys_desc, ddadr;
229 struct pxad_desc_hw *desc;
230
231 phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR);
232
233 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);
234 seq_printf(s, "[%03d] First descriptor unknown\n", 0);
235 for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
236 desc = phys_to_virt(phys_desc);
237 dcmd = desc->dcmd;
238 burst = dbg_burst_from_dcmd(dcmd);
239 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
240
241 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
242 i, phys_desc, desc);
243 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
244 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
245 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
246 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
247 dcmd,
248 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
249 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
250 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
251 PXA_DCMD_STR(ENDIAN), burst, width,
252 dcmd & PXA_DCMD_LENGTH);
253 phys_desc = desc->ddadr;
254 }
255 if (i == max_show)
256 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
257 i, phys_desc);
258 else
259 seq_printf(s, "[%03d] Desc at %08lx is %s\n",
260 i, phys_desc, phys_desc == DDADR_STOP ?
261 "DDADR_STOP" : "invalid");
262
263 return 0;
264 }
265
266 static int dbg_show_chan_state(struct seq_file *s, void *p)
267 {
268 struct pxad_phy *phy = s->private;
269 u32 dcsr, dcmd;
270 int burst, width;
271 static const char * const str_prio[] = {
272 "high", "normal", "low", "invalid"
273 };
274
275 dcsr = _phy_readl_relaxed(phy, DCSR);
276 dcmd = _phy_readl_relaxed(phy, DCMD);
277 burst = dbg_burst_from_dcmd(dcmd);
278 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
279
280 seq_printf(s, "DMA channel %d\n", phy->idx);
281 seq_printf(s, "\tPriority : %s\n",
282 str_prio[(phy->idx & 0xf) / 4]);
283 seq_printf(s, "\tUnaligned transfer bit: %s\n",
284 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
285 "yes" : "no");
286 seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
287 dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
288 PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),
289 PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN),
290 PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST),
291 PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR),
292 PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE),
293 PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR),
294 PXA_DCSR_STR(BUSERR));
295
296 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
297 dcmd,
298 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
299 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
300 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
301 PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH);
302 seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR));
303 seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR));
304 seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR));
305
306 return 0;
307 }
308
309 static int dbg_show_state(struct seq_file *s, void *p)
310 {
311 struct pxad_device *pdev = s->private;
312
313 /* basic device status */
314 seq_puts(s, "DMA engine status\n");
315 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);
316
317 return 0;
318 }
319
320 #define DBGFS_FUNC_DECL(name) \
321 static int dbg_open_##name(struct inode *inode, struct file *file) \
322 { \
323 return single_open(file, dbg_show_##name, inode->i_private); \
324 } \
325 static const struct file_operations dbg_fops_##name = { \
326 .open = dbg_open_##name, \
327 .llseek = seq_lseek, \
328 .read = seq_read, \
329 .release = single_release, \
330 }
331
332 DBGFS_FUNC_DECL(state);
333 DBGFS_FUNC_DECL(chan_state);
334 DBGFS_FUNC_DECL(descriptors);
335 DBGFS_FUNC_DECL(requester_chan);
336
337 static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev,
338 int ch, struct dentry *chandir)
339 {
340 char chan_name[11];
341 struct dentry *chan, *chan_state = NULL, *chan_descr = NULL;
342 struct dentry *chan_reqs = NULL;
343 void *dt;
344
345 scnprintf(chan_name, sizeof(chan_name), "%d", ch);
346 chan = debugfs_create_dir(chan_name, chandir);
347 dt = (void *)&pdev->phys[ch];
348
349 if (chan)
350 chan_state = debugfs_create_file("state", 0400, chan, dt,
351 &dbg_fops_chan_state);
352 if (chan_state)
353 chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
354 &dbg_fops_descriptors);
355 if (chan_descr)
356 chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
357 &dbg_fops_requester_chan);
358 if (!chan_reqs)
359 goto err_state;
360
361 return chan;
362
363 err_state:
364 debugfs_remove_recursive(chan);
365 return NULL;
366 }
367
368 static void pxad_init_debugfs(struct pxad_device *pdev)
369 {
370 int i;
371 struct dentry *chandir;
372
373 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);
374 if (IS_ERR(pdev->dbgfs_root) || !pdev->dbgfs_root)
375 goto err_root;
376
377 pdev->dbgfs_state = debugfs_create_file("state", 0400, pdev->dbgfs_root,
378 pdev, &dbg_fops_state);
379 if (!pdev->dbgfs_state)
380 goto err_state;
381
382 pdev->dbgfs_chan =
383 kmalloc_array(pdev->nr_chans, sizeof(*pdev->dbgfs_state),
384 GFP_KERNEL);
385 if (!pdev->dbgfs_chan)
386 goto err_alloc;
387
388 chandir = debugfs_create_dir("channels", pdev->dbgfs_root);
389 if (!chandir)
390 goto err_chandir;
391
392 for (i = 0; i < pdev->nr_chans; i++) {
393 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);
394 if (!pdev->dbgfs_chan[i])
395 goto err_chans;
396 }
397
398 return;
399 err_chans:
400 err_chandir:
401 kfree(pdev->dbgfs_chan);
402 err_alloc:
403 err_state:
404 debugfs_remove_recursive(pdev->dbgfs_root);
405 err_root:
406 pr_err("pxad: debugfs is not available\n");
407 }
408
409 static void pxad_cleanup_debugfs(struct pxad_device *pdev)
410 {
411 debugfs_remove_recursive(pdev->dbgfs_root);
412 }
413 #else
414 static inline void pxad_init_debugfs(struct pxad_device *pdev) {}
415 static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {}
416 #endif
417
418 static struct pxad_phy *lookup_phy(struct pxad_chan *pchan)
419 {
420 int prio, i;
421 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device);
422 struct pxad_phy *phy, *found = NULL;
423 unsigned long flags;
424
425 /*
426 * dma channel priorities
427 * ch 0 - 3, 16 - 19 <--> (0)
428 * ch 4 - 7, 20 - 23 <--> (1)
429 * ch 8 - 11, 24 - 27 <--> (2)
430 * ch 12 - 15, 28 - 31 <--> (3)
431 */
432
433 spin_lock_irqsave(&pdev->phy_lock, flags);
434 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) {
435 for (i = 0; i < pdev->nr_chans; i++) {
436 if (prio != (i & 0xf) >> 2)
437 continue;
438 phy = &pdev->phys[i];
439 if (!phy->vchan) {
440 phy->vchan = pchan;
441 found = phy;
442 goto out_unlock;
443 }
444 }
445 }
446
447 out_unlock:
448 spin_unlock_irqrestore(&pdev->phy_lock, flags);
449 dev_dbg(&pchan->vc.chan.dev->device,
450 "%s(): phy=%p(%d)\n", __func__, found,
451 found ? found->idx : -1);
452
453 return found;
454 }
455
456 static void pxad_free_phy(struct pxad_chan *chan)
457 {
458 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
459 unsigned long flags;
460 u32 reg;
461
462 dev_dbg(&chan->vc.chan.dev->device,
463 "%s(): freeing\n", __func__);
464 if (!chan->phy)
465 return;
466
467 /* clear the channel mapping in DRCMR */
468 if (chan->drcmr <= pdev->nr_requestors) {
469 reg = pxad_drcmr(chan->drcmr);
470 writel_relaxed(0, chan->phy->base + reg);
471 }
472
473 spin_lock_irqsave(&pdev->phy_lock, flags);
474 chan->phy->vchan = NULL;
475 chan->phy = NULL;
476 spin_unlock_irqrestore(&pdev->phy_lock, flags);
477 }
478
479 static bool is_chan_running(struct pxad_chan *chan)
480 {
481 u32 dcsr;
482 struct pxad_phy *phy = chan->phy;
483
484 if (!phy)
485 return false;
486 dcsr = phy_readl_relaxed(phy, DCSR);
487 return dcsr & PXA_DCSR_RUN;
488 }
489
490 static bool is_running_chan_misaligned(struct pxad_chan *chan)
491 {
492 u32 dalgn;
493
494 BUG_ON(!chan->phy);
495 dalgn = phy_readl_relaxed(chan->phy, DALGN);
496 return dalgn & (BIT(chan->phy->idx));
497 }
498
499 static void phy_enable(struct pxad_phy *phy, bool misaligned)
500 {
501 struct pxad_device *pdev;
502 u32 reg, dalgn;
503
504 if (!phy->vchan)
505 return;
506
507 dev_dbg(&phy->vchan->vc.chan.dev->device,
508 "%s(); phy=%p(%d) misaligned=%d\n", __func__,
509 phy, phy->idx, misaligned);
510
511 pdev = to_pxad_dev(phy->vchan->vc.chan.device);
512 if (phy->vchan->drcmr <= pdev->nr_requestors) {
513 reg = pxad_drcmr(phy->vchan->drcmr);
514 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
515 }
516
517 dalgn = phy_readl_relaxed(phy, DALGN);
518 if (misaligned)
519 dalgn |= BIT(phy->idx);
520 else
521 dalgn &= ~BIT(phy->idx);
522 phy_writel_relaxed(phy, dalgn, DALGN);
523
524 phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR |
525 PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR);
526 }
527
528 static void phy_disable(struct pxad_phy *phy)
529 {
530 u32 dcsr;
531
532 if (!phy)
533 return;
534
535 dcsr = phy_readl_relaxed(phy, DCSR);
536 dev_dbg(&phy->vchan->vc.chan.dev->device,
537 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx);
538 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR);
539 }
540
541 static void pxad_launch_chan(struct pxad_chan *chan,
542 struct pxad_desc_sw *desc)
543 {
544 dev_dbg(&chan->vc.chan.dev->device,
545 "%s(): desc=%p\n", __func__, desc);
546 if (!chan->phy) {
547 chan->phy = lookup_phy(chan);
548 if (!chan->phy) {
549 dev_dbg(&chan->vc.chan.dev->device,
550 "%s(): no free dma channel\n", __func__);
551 return;
552 }
553 }
554 chan->bus_error = 0;
555
556 /*
557 * Program the descriptor's address into the DMA controller,
558 * then start the DMA transaction
559 */
560 phy_writel(chan->phy, desc->first, DDADR);
561 phy_enable(chan->phy, chan->misaligned);
562 wake_up(&chan->wq_state);
563 }
564
565 static void set_updater_desc(struct pxad_desc_sw *sw_desc,
566 unsigned long flags)
567 {
568 struct pxad_desc_hw *updater =
569 sw_desc->hw_desc[sw_desc->nb_desc - 1];
570 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr;
571
572 updater->ddadr = DDADR_STOP;
573 updater->dsadr = dma;
574 updater->dtadr = dma + 8;
575 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 |
576 (PXA_DCMD_LENGTH & sizeof(u32));
577 if (flags & DMA_PREP_INTERRUPT)
578 updater->dcmd |= PXA_DCMD_ENDIRQEN;
579 if (sw_desc->cyclic)
580 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first;
581 }
582
583 static bool is_desc_completed(struct virt_dma_desc *vd)
584 {
585 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
586 struct pxad_desc_hw *updater =
587 sw_desc->hw_desc[sw_desc->nb_desc - 1];
588
589 return updater->dtadr != (updater->dsadr + 8);
590 }
591
592 static void pxad_desc_chain(struct virt_dma_desc *vd1,
593 struct virt_dma_desc *vd2)
594 {
595 struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1);
596 struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2);
597 dma_addr_t dma_to_chain;
598
599 dma_to_chain = desc2->first;
600 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain;
601 }
602
603 static bool pxad_try_hotchain(struct virt_dma_chan *vc,
604 struct virt_dma_desc *vd)
605 {
606 struct virt_dma_desc *vd_last_issued = NULL;
607 struct pxad_chan *chan = to_pxad_chan(&vc->chan);
608
609 /*
610 * Attempt to hot chain the tx if the phy is still running. This is
611 * considered successful only if either the channel is still running
612 * after the chaining, or if the chained transfer is completed after
613 * having been hot chained.
614 * A change of alignment is not allowed, and forbids hotchaining.
615 */
616 if (is_chan_running(chan)) {
617 BUG_ON(list_empty(&vc->desc_issued));
618
619 if (!is_running_chan_misaligned(chan) &&
620 to_pxad_sw_desc(vd)->misaligned)
621 return false;
622
623 vd_last_issued = list_entry(vc->desc_issued.prev,
624 struct virt_dma_desc, node);
625 pxad_desc_chain(vd_last_issued, vd);
626 if (is_chan_running(chan) || is_desc_completed(vd))
627 return true;
628 }
629
630 return false;
631 }
632
633 static unsigned int clear_chan_irq(struct pxad_phy *phy)
634 {
635 u32 dcsr;
636 u32 dint = readl(phy->base + DINT);
637
638 if (!(dint & BIT(phy->idx)))
639 return PXA_DCSR_RUN;
640
641 /* clear irq */
642 dcsr = phy_readl_relaxed(phy, DCSR);
643 phy_writel(phy, dcsr, DCSR);
644 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan))
645 dev_warn(&phy->vchan->vc.chan.dev->device,
646 "%s(chan=%p): PXA_DCSR_BUSERR\n",
647 __func__, &phy->vchan);
648
649 return dcsr & ~PXA_DCSR_RUN;
650 }
651
652 static irqreturn_t pxad_chan_handler(int irq, void *dev_id)
653 {
654 struct pxad_phy *phy = dev_id;
655 struct pxad_chan *chan = phy->vchan;
656 struct virt_dma_desc *vd, *tmp;
657 unsigned int dcsr;
658 unsigned long flags;
659 bool vd_completed;
660 dma_cookie_t last_started = 0;
661
662 BUG_ON(!chan);
663
664 dcsr = clear_chan_irq(phy);
665 if (dcsr & PXA_DCSR_RUN)
666 return IRQ_NONE;
667
668 spin_lock_irqsave(&chan->vc.lock, flags);
669 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) {
670 vd_completed = is_desc_completed(vd);
671 dev_dbg(&chan->vc.chan.dev->device,
672 "%s(): checking txd %p[%x]: completed=%d dcsr=0x%x\n",
673 __func__, vd, vd->tx.cookie, vd_completed,
674 dcsr);
675 last_started = vd->tx.cookie;
676 if (to_pxad_sw_desc(vd)->cyclic) {
677 vchan_cyclic_callback(vd);
678 break;
679 }
680 if (vd_completed) {
681 list_del(&vd->node);
682 vchan_cookie_complete(vd);
683 } else {
684 break;
685 }
686 }
687
688 if (dcsr & PXA_DCSR_BUSERR) {
689 chan->bus_error = last_started;
690 phy_disable(phy);
691 }
692
693 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) {
694 dev_dbg(&chan->vc.chan.dev->device,
695 "%s(): channel stopped, submitted_empty=%d issued_empty=%d",
696 __func__,
697 list_empty(&chan->vc.desc_submitted),
698 list_empty(&chan->vc.desc_issued));
699 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR);
700
701 if (list_empty(&chan->vc.desc_issued)) {
702 chan->misaligned =
703 !list_empty(&chan->vc.desc_submitted);
704 } else {
705 vd = list_first_entry(&chan->vc.desc_issued,
706 struct virt_dma_desc, node);
707 pxad_launch_chan(chan, to_pxad_sw_desc(vd));
708 }
709 }
710 spin_unlock_irqrestore(&chan->vc.lock, flags);
711 wake_up(&chan->wq_state);
712
713 return IRQ_HANDLED;
714 }
715
716 static irqreturn_t pxad_int_handler(int irq, void *dev_id)
717 {
718 struct pxad_device *pdev = dev_id;
719 struct pxad_phy *phy;
720 u32 dint = readl(pdev->base + DINT);
721 int i, ret = IRQ_NONE;
722
723 while (dint) {
724 i = __ffs(dint);
725 dint &= (dint - 1);
726 phy = &pdev->phys[i];
727 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED)
728 ret = IRQ_HANDLED;
729 }
730
731 return ret;
732 }
733
734 static int pxad_alloc_chan_resources(struct dma_chan *dchan)
735 {
736 struct pxad_chan *chan = to_pxad_chan(dchan);
737 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
738
739 if (chan->desc_pool)
740 return 1;
741
742 chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
743 pdev->slave.dev,
744 sizeof(struct pxad_desc_hw),
745 __alignof__(struct pxad_desc_hw),
746 0);
747 if (!chan->desc_pool) {
748 dev_err(&chan->vc.chan.dev->device,
749 "%s(): unable to allocate descriptor pool\n",
750 __func__);
751 return -ENOMEM;
752 }
753
754 return 1;
755 }
756
757 static void pxad_free_chan_resources(struct dma_chan *dchan)
758 {
759 struct pxad_chan *chan = to_pxad_chan(dchan);
760
761 vchan_free_chan_resources(&chan->vc);
762 dma_pool_destroy(chan->desc_pool);
763 chan->desc_pool = NULL;
764
765 chan->drcmr = U32_MAX;
766 chan->prio = PXAD_PRIO_LOWEST;
767 }
768
769 static void pxad_free_desc(struct virt_dma_desc *vd)
770 {
771 int i;
772 dma_addr_t dma;
773 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
774
775 BUG_ON(sw_desc->nb_desc == 0);
776 for (i = sw_desc->nb_desc - 1; i >= 0; i--) {
777 if (i > 0)
778 dma = sw_desc->hw_desc[i - 1]->ddadr;
779 else
780 dma = sw_desc->first;
781 dma_pool_free(sw_desc->desc_pool,
782 sw_desc->hw_desc[i], dma);
783 }
784 sw_desc->nb_desc = 0;
785 kfree(sw_desc);
786 }
787
788 static struct pxad_desc_sw *
789 pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc)
790 {
791 struct pxad_desc_sw *sw_desc;
792 dma_addr_t dma;
793 int i;
794
795 sw_desc = kzalloc(sizeof(*sw_desc) +
796 nb_hw_desc * sizeof(struct pxad_desc_hw *),
797 GFP_NOWAIT);
798 if (!sw_desc)
799 return NULL;
800 sw_desc->desc_pool = chan->desc_pool;
801
802 for (i = 0; i < nb_hw_desc; i++) {
803 sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool,
804 GFP_NOWAIT, &dma);
805 if (!sw_desc->hw_desc[i]) {
806 dev_err(&chan->vc.chan.dev->device,
807 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n",
808 __func__, i, sw_desc->desc_pool);
809 goto err;
810 }
811
812 if (i == 0)
813 sw_desc->first = dma;
814 else
815 sw_desc->hw_desc[i - 1]->ddadr = dma;
816 sw_desc->nb_desc++;
817 }
818
819 return sw_desc;
820 err:
821 pxad_free_desc(&sw_desc->vd);
822 return NULL;
823 }
824
825 static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx)
826 {
827 struct virt_dma_chan *vc = to_virt_chan(tx->chan);
828 struct pxad_chan *chan = to_pxad_chan(&vc->chan);
829 struct virt_dma_desc *vd_chained = NULL,
830 *vd = container_of(tx, struct virt_dma_desc, tx);
831 dma_cookie_t cookie;
832 unsigned long flags;
833
834 set_updater_desc(to_pxad_sw_desc(vd), tx->flags);
835
836 spin_lock_irqsave(&vc->lock, flags);
837 cookie = dma_cookie_assign(tx);
838
839 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) {
840 list_move_tail(&vd->node, &vc->desc_issued);
841 dev_dbg(&chan->vc.chan.dev->device,
842 "%s(): txd %p[%x]: submitted (hot linked)\n",
843 __func__, vd, cookie);
844 goto out;
845 }
846
847 /*
848 * Fallback to placing the tx in the submitted queue
849 */
850 if (!list_empty(&vc->desc_submitted)) {
851 vd_chained = list_entry(vc->desc_submitted.prev,
852 struct virt_dma_desc, node);
853 /*
854 * Only chain the descriptors if no new misalignment is
855 * introduced. If a new misalignment is chained, let the channel
856 * stop, and be relaunched in misalign mode from the irq
857 * handler.
858 */
859 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned)
860 pxad_desc_chain(vd_chained, vd);
861 else
862 vd_chained = NULL;
863 }
864 dev_dbg(&chan->vc.chan.dev->device,
865 "%s(): txd %p[%x]: submitted (%s linked)\n",
866 __func__, vd, cookie, vd_chained ? "cold" : "not");
867 list_move_tail(&vd->node, &vc->desc_submitted);
868 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned;
869
870 out:
871 spin_unlock_irqrestore(&vc->lock, flags);
872 return cookie;
873 }
874
875 static void pxad_issue_pending(struct dma_chan *dchan)
876 {
877 struct pxad_chan *chan = to_pxad_chan(dchan);
878 struct virt_dma_desc *vd_first;
879 unsigned long flags;
880
881 spin_lock_irqsave(&chan->vc.lock, flags);
882 if (list_empty(&chan->vc.desc_submitted))
883 goto out;
884
885 vd_first = list_first_entry(&chan->vc.desc_submitted,
886 struct virt_dma_desc, node);
887 dev_dbg(&chan->vc.chan.dev->device,
888 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie);
889
890 vchan_issue_pending(&chan->vc);
891 if (!pxad_try_hotchain(&chan->vc, vd_first))
892 pxad_launch_chan(chan, to_pxad_sw_desc(vd_first));
893 out:
894 spin_unlock_irqrestore(&chan->vc.lock, flags);
895 }
896
897 static inline struct dma_async_tx_descriptor *
898 pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd,
899 unsigned long tx_flags)
900 {
901 struct dma_async_tx_descriptor *tx;
902 struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc);
903
904 INIT_LIST_HEAD(&vd->node);
905 tx = vchan_tx_prep(vc, vd, tx_flags);
906 tx->tx_submit = pxad_tx_submit;
907 dev_dbg(&chan->vc.chan.dev->device,
908 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__,
909 vc, vd, vd->tx.cookie,
910 tx_flags);
911
912 return tx;
913 }
914
915 static void pxad_get_config(struct pxad_chan *chan,
916 enum dma_transfer_direction dir,
917 u32 *dcmd, u32 *dev_src, u32 *dev_dst)
918 {
919 u32 maxburst = 0, dev_addr = 0;
920 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
921 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
922
923 *dcmd = 0;
924 if (dir == DMA_DEV_TO_MEM) {
925 maxburst = chan->cfg.src_maxburst;
926 width = chan->cfg.src_addr_width;
927 dev_addr = chan->cfg.src_addr;
928 *dev_src = dev_addr;
929 *dcmd |= PXA_DCMD_INCTRGADDR;
930 if (chan->drcmr <= pdev->nr_requestors)
931 *dcmd |= PXA_DCMD_FLOWSRC;
932 }
933 if (dir == DMA_MEM_TO_DEV) {
934 maxburst = chan->cfg.dst_maxburst;
935 width = chan->cfg.dst_addr_width;
936 dev_addr = chan->cfg.dst_addr;
937 *dev_dst = dev_addr;
938 *dcmd |= PXA_DCMD_INCSRCADDR;
939 if (chan->drcmr <= pdev->nr_requestors)
940 *dcmd |= PXA_DCMD_FLOWTRG;
941 }
942 if (dir == DMA_MEM_TO_MEM)
943 *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR |
944 PXA_DCMD_INCSRCADDR;
945
946 dev_dbg(&chan->vc.chan.dev->device,
947 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n",
948 __func__, dev_addr, maxburst, width, dir);
949
950 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
951 *dcmd |= PXA_DCMD_WIDTH1;
952 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
953 *dcmd |= PXA_DCMD_WIDTH2;
954 else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
955 *dcmd |= PXA_DCMD_WIDTH4;
956
957 if (maxburst == 8)
958 *dcmd |= PXA_DCMD_BURST8;
959 else if (maxburst == 16)
960 *dcmd |= PXA_DCMD_BURST16;
961 else if (maxburst == 32)
962 *dcmd |= PXA_DCMD_BURST32;
963
964 /* FIXME: drivers should be ported over to use the filter
965 * function. Once that's done, the following two lines can
966 * be removed.
967 */
968 if (chan->cfg.slave_id)
969 chan->drcmr = chan->cfg.slave_id;
970 }
971
972 static struct dma_async_tx_descriptor *
973 pxad_prep_memcpy(struct dma_chan *dchan,
974 dma_addr_t dma_dst, dma_addr_t dma_src,
975 size_t len, unsigned long flags)
976 {
977 struct pxad_chan *chan = to_pxad_chan(dchan);
978 struct pxad_desc_sw *sw_desc;
979 struct pxad_desc_hw *hw_desc;
980 u32 dcmd;
981 unsigned int i, nb_desc = 0;
982 size_t copy;
983
984 if (!dchan || !len)
985 return NULL;
986
987 dev_dbg(&chan->vc.chan.dev->device,
988 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n",
989 __func__, (unsigned long)dma_dst, (unsigned long)dma_src,
990 len, flags);
991 pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL);
992
993 nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES);
994 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
995 if (!sw_desc)
996 return NULL;
997 sw_desc->len = len;
998
999 if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) ||
1000 !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT))
1001 sw_desc->misaligned = true;
1002
1003 i = 0;
1004 do {
1005 hw_desc = sw_desc->hw_desc[i++];
1006 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
1007 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy);
1008 hw_desc->dsadr = dma_src;
1009 hw_desc->dtadr = dma_dst;
1010 len -= copy;
1011 dma_src += copy;
1012 dma_dst += copy;
1013 } while (len);
1014 set_updater_desc(sw_desc, flags);
1015
1016 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1017 }
1018
1019 static struct dma_async_tx_descriptor *
1020 pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
1021 unsigned int sg_len, enum dma_transfer_direction dir,
1022 unsigned long flags, void *context)
1023 {
1024 struct pxad_chan *chan = to_pxad_chan(dchan);
1025 struct pxad_desc_sw *sw_desc;
1026 size_t len, avail;
1027 struct scatterlist *sg;
1028 dma_addr_t dma;
1029 u32 dcmd, dsadr = 0, dtadr = 0;
1030 unsigned int nb_desc = 0, i, j = 0;
1031
1032 if ((sgl == NULL) || (sg_len == 0))
1033 return NULL;
1034
1035 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1036 dev_dbg(&chan->vc.chan.dev->device,
1037 "%s(): dir=%d flags=%lx\n", __func__, dir, flags);
1038
1039 for_each_sg(sgl, sg, sg_len, i)
1040 nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES);
1041 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1042 if (!sw_desc)
1043 return NULL;
1044
1045 for_each_sg(sgl, sg, sg_len, i) {
1046 dma = sg_dma_address(sg);
1047 avail = sg_dma_len(sg);
1048 sw_desc->len += avail;
1049
1050 do {
1051 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
1052 if (dma & 0x7)
1053 sw_desc->misaligned = true;
1054
1055 sw_desc->hw_desc[j]->dcmd =
1056 dcmd | (PXA_DCMD_LENGTH & len);
1057 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;
1058 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma;
1059
1060 dma += len;
1061 avail -= len;
1062 } while (avail);
1063 }
1064 set_updater_desc(sw_desc, flags);
1065
1066 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1067 }
1068
1069 static struct dma_async_tx_descriptor *
1070 pxad_prep_dma_cyclic(struct dma_chan *dchan,
1071 dma_addr_t buf_addr, size_t len, size_t period_len,
1072 enum dma_transfer_direction dir, unsigned long flags)
1073 {
1074 struct pxad_chan *chan = to_pxad_chan(dchan);
1075 struct pxad_desc_sw *sw_desc;
1076 struct pxad_desc_hw **phw_desc;
1077 dma_addr_t dma;
1078 u32 dcmd, dsadr = 0, dtadr = 0;
1079 unsigned int nb_desc = 0;
1080
1081 if (!dchan || !len || !period_len)
1082 return NULL;
1083 if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) {
1084 dev_err(&chan->vc.chan.dev->device,
1085 "Unsupported direction for cyclic DMA\n");
1086 return NULL;
1087 }
1088 /* the buffer length must be a multiple of period_len */
1089 if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES ||
1090 !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT))
1091 return NULL;
1092
1093 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1094 dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len);
1095 dev_dbg(&chan->vc.chan.dev->device,
1096 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n",
1097 __func__, (unsigned long)buf_addr, len, period_len, dir, flags);
1098
1099 nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES);
1100 nb_desc *= DIV_ROUND_UP(len, period_len);
1101 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1102 if (!sw_desc)
1103 return NULL;
1104 sw_desc->cyclic = true;
1105 sw_desc->len = len;
1106
1107 phw_desc = sw_desc->hw_desc;
1108 dma = buf_addr;
1109 do {
1110 phw_desc[0]->dsadr = dsadr ? dsadr : dma;
1111 phw_desc[0]->dtadr = dtadr ? dtadr : dma;
1112 phw_desc[0]->dcmd = dcmd;
1113 phw_desc++;
1114 dma += period_len;
1115 len -= period_len;
1116 } while (len);
1117 set_updater_desc(sw_desc, flags);
1118
1119 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1120 }
1121
1122 static int pxad_config(struct dma_chan *dchan,
1123 struct dma_slave_config *cfg)
1124 {
1125 struct pxad_chan *chan = to_pxad_chan(dchan);
1126
1127 if (!dchan)
1128 return -EINVAL;
1129
1130 chan->cfg = *cfg;
1131 return 0;
1132 }
1133
1134 static int pxad_terminate_all(struct dma_chan *dchan)
1135 {
1136 struct pxad_chan *chan = to_pxad_chan(dchan);
1137 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
1138 struct virt_dma_desc *vd = NULL;
1139 unsigned long flags;
1140 struct pxad_phy *phy;
1141 LIST_HEAD(head);
1142
1143 dev_dbg(&chan->vc.chan.dev->device,
1144 "%s(): vchan %p: terminate all\n", __func__, &chan->vc);
1145
1146 spin_lock_irqsave(&chan->vc.lock, flags);
1147 vchan_get_all_descriptors(&chan->vc, &head);
1148
1149 list_for_each_entry(vd, &head, node) {
1150 dev_dbg(&chan->vc.chan.dev->device,
1151 "%s(): cancelling txd %p[%x] (completed=%d)", __func__,
1152 vd, vd->tx.cookie, is_desc_completed(vd));
1153 }
1154
1155 phy = chan->phy;
1156 if (phy) {
1157 phy_disable(chan->phy);
1158 pxad_free_phy(chan);
1159 chan->phy = NULL;
1160 spin_lock(&pdev->phy_lock);
1161 phy->vchan = NULL;
1162 spin_unlock(&pdev->phy_lock);
1163 }
1164 spin_unlock_irqrestore(&chan->vc.lock, flags);
1165 vchan_dma_desc_free_list(&chan->vc, &head);
1166
1167 return 0;
1168 }
1169
1170 static unsigned int pxad_residue(struct pxad_chan *chan,
1171 dma_cookie_t cookie)
1172 {
1173 struct virt_dma_desc *vd = NULL;
1174 struct pxad_desc_sw *sw_desc = NULL;
1175 struct pxad_desc_hw *hw_desc = NULL;
1176 u32 curr, start, len, end, residue = 0;
1177 unsigned long flags;
1178 bool passed = false;
1179 int i;
1180
1181 /*
1182 * If the channel does not have a phy pointer anymore, it has already
1183 * been completed. Therefore, its residue is 0.
1184 */
1185 if (!chan->phy)
1186 return 0;
1187
1188 spin_lock_irqsave(&chan->vc.lock, flags);
1189
1190 vd = vchan_find_desc(&chan->vc, cookie);
1191 if (!vd)
1192 goto out;
1193
1194 sw_desc = to_pxad_sw_desc(vd);
1195 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1196 curr = phy_readl_relaxed(chan->phy, DSADR);
1197 else
1198 curr = phy_readl_relaxed(chan->phy, DTADR);
1199
1200 /*
1201 * curr has to be actually read before checking descriptor
1202 * completion, so that a curr inside a status updater
1203 * descriptor implies the following test returns true, and
1204 * preventing reordering of curr load and the test.
1205 */
1206 rmb();
1207 if (is_desc_completed(vd))
1208 goto out;
1209
1210 for (i = 0; i < sw_desc->nb_desc - 1; i++) {
1211 hw_desc = sw_desc->hw_desc[i];
1212 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1213 start = hw_desc->dsadr;
1214 else
1215 start = hw_desc->dtadr;
1216 len = hw_desc->dcmd & PXA_DCMD_LENGTH;
1217 end = start + len;
1218
1219 /*
1220 * 'passed' will be latched once we found the descriptor
1221 * which lies inside the boundaries of the curr
1222 * pointer. All descriptors that occur in the list
1223 * _after_ we found that partially handled descriptor
1224 * are still to be processed and are hence added to the
1225 * residual bytes counter.
1226 */
1227
1228 if (passed) {
1229 residue += len;
1230 } else if (curr >= start && curr <= end) {
1231 residue += end - curr;
1232 passed = true;
1233 }
1234 }
1235 if (!passed)
1236 residue = sw_desc->len;
1237
1238 out:
1239 spin_unlock_irqrestore(&chan->vc.lock, flags);
1240 dev_dbg(&chan->vc.chan.dev->device,
1241 "%s(): txd %p[%x] sw_desc=%p: %d\n",
1242 __func__, vd, cookie, sw_desc, residue);
1243 return residue;
1244 }
1245
1246 static enum dma_status pxad_tx_status(struct dma_chan *dchan,
1247 dma_cookie_t cookie,
1248 struct dma_tx_state *txstate)
1249 {
1250 struct pxad_chan *chan = to_pxad_chan(dchan);
1251 enum dma_status ret;
1252
1253 if (cookie == chan->bus_error)
1254 return DMA_ERROR;
1255
1256 ret = dma_cookie_status(dchan, cookie, txstate);
1257 if (likely(txstate && (ret != DMA_ERROR)))
1258 dma_set_residue(txstate, pxad_residue(chan, cookie));
1259
1260 return ret;
1261 }
1262
1263 static void pxad_synchronize(struct dma_chan *dchan)
1264 {
1265 struct pxad_chan *chan = to_pxad_chan(dchan);
1266
1267 wait_event(chan->wq_state, !is_chan_running(chan));
1268 vchan_synchronize(&chan->vc);
1269 }
1270
1271 static void pxad_free_channels(struct dma_device *dmadev)
1272 {
1273 struct pxad_chan *c, *cn;
1274
1275 list_for_each_entry_safe(c, cn, &dmadev->channels,
1276 vc.chan.device_node) {
1277 list_del(&c->vc.chan.device_node);
1278 tasklet_kill(&c->vc.task);
1279 }
1280 }
1281
1282 static int pxad_remove(struct platform_device *op)
1283 {
1284 struct pxad_device *pdev = platform_get_drvdata(op);
1285
1286 pxad_cleanup_debugfs(pdev);
1287 pxad_free_channels(&pdev->slave);
1288 dma_async_device_unregister(&pdev->slave);
1289 return 0;
1290 }
1291
1292 static int pxad_init_phys(struct platform_device *op,
1293 struct pxad_device *pdev,
1294 unsigned int nb_phy_chans)
1295 {
1296 int irq0, irq, nr_irq = 0, i, ret;
1297 struct pxad_phy *phy;
1298
1299 irq0 = platform_get_irq(op, 0);
1300 if (irq0 < 0)
1301 return irq0;
1302
1303 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans,
1304 sizeof(pdev->phys[0]), GFP_KERNEL);
1305 if (!pdev->phys)
1306 return -ENOMEM;
1307
1308 for (i = 0; i < nb_phy_chans; i++)
1309 if (platform_get_irq(op, i) > 0)
1310 nr_irq++;
1311
1312 for (i = 0; i < nb_phy_chans; i++) {
1313 phy = &pdev->phys[i];
1314 phy->base = pdev->base;
1315 phy->idx = i;
1316 irq = platform_get_irq(op, i);
1317 if ((nr_irq > 1) && (irq > 0))
1318 ret = devm_request_irq(&op->dev, irq,
1319 pxad_chan_handler,
1320 IRQF_SHARED, "pxa-dma", phy);
1321 if ((nr_irq == 1) && (i == 0))
1322 ret = devm_request_irq(&op->dev, irq0,
1323 pxad_int_handler,
1324 IRQF_SHARED, "pxa-dma", pdev);
1325 if (ret) {
1326 dev_err(pdev->slave.dev,
1327 "%s(): can't request irq %d:%d\n", __func__,
1328 irq, ret);
1329 return ret;
1330 }
1331 }
1332
1333 return 0;
1334 }
1335
1336 static const struct of_device_id pxad_dt_ids[] = {
1337 { .compatible = "marvell,pdma-1.0", },
1338 {}
1339 };
1340 MODULE_DEVICE_TABLE(of, pxad_dt_ids);
1341
1342 static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec,
1343 struct of_dma *ofdma)
1344 {
1345 struct pxad_device *d = ofdma->of_dma_data;
1346 struct dma_chan *chan;
1347
1348 chan = dma_get_any_slave_channel(&d->slave);
1349 if (!chan)
1350 return NULL;
1351
1352 to_pxad_chan(chan)->drcmr = dma_spec->args[0];
1353 to_pxad_chan(chan)->prio = dma_spec->args[1];
1354
1355 return chan;
1356 }
1357
1358 static int pxad_init_dmadev(struct platform_device *op,
1359 struct pxad_device *pdev,
1360 unsigned int nr_phy_chans,
1361 unsigned int nr_requestors)
1362 {
1363 int ret;
1364 unsigned int i;
1365 struct pxad_chan *c;
1366
1367 pdev->nr_chans = nr_phy_chans;
1368 pdev->nr_requestors = nr_requestors;
1369 INIT_LIST_HEAD(&pdev->slave.channels);
1370 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources;
1371 pdev->slave.device_free_chan_resources = pxad_free_chan_resources;
1372 pdev->slave.device_tx_status = pxad_tx_status;
1373 pdev->slave.device_issue_pending = pxad_issue_pending;
1374 pdev->slave.device_config = pxad_config;
1375 pdev->slave.device_synchronize = pxad_synchronize;
1376 pdev->slave.device_terminate_all = pxad_terminate_all;
1377
1378 if (op->dev.coherent_dma_mask)
1379 dma_set_mask(&op->dev, op->dev.coherent_dma_mask);
1380 else
1381 dma_set_mask(&op->dev, DMA_BIT_MASK(32));
1382
1383 ret = pxad_init_phys(op, pdev, nr_phy_chans);
1384 if (ret)
1385 return ret;
1386
1387 for (i = 0; i < nr_phy_chans; i++) {
1388 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL);
1389 if (!c)
1390 return -ENOMEM;
1391
1392 c->drcmr = U32_MAX;
1393 c->prio = PXAD_PRIO_LOWEST;
1394 c->vc.desc_free = pxad_free_desc;
1395 vchan_init(&c->vc, &pdev->slave);
1396 init_waitqueue_head(&c->wq_state);
1397 }
1398
1399 return dma_async_device_register(&pdev->slave);
1400 }
1401
1402 static int pxad_probe(struct platform_device *op)
1403 {
1404 struct pxad_device *pdev;
1405 const struct of_device_id *of_id;
1406 const struct dma_slave_map *slave_map = NULL;
1407 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1408 struct resource *iores;
1409 int ret, dma_channels = 0, nb_requestors = 0, slave_map_cnt = 0;
1410 const enum dma_slave_buswidth widths =
1411 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
1412 DMA_SLAVE_BUSWIDTH_4_BYTES;
1413
1414 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
1415 if (!pdev)
1416 return -ENOMEM;
1417
1418 spin_lock_init(&pdev->phy_lock);
1419
1420 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1421 pdev->base = devm_ioremap_resource(&op->dev, iores);
1422 if (IS_ERR(pdev->base))
1423 return PTR_ERR(pdev->base);
1424
1425 of_id = of_match_device(pxad_dt_ids, &op->dev);
1426 if (of_id) {
1427 of_property_read_u32(op->dev.of_node, "#dma-channels",
1428 &dma_channels);
1429 ret = of_property_read_u32(op->dev.of_node, "#dma-requests",
1430 &nb_requestors);
1431 if (ret) {
1432 dev_warn(pdev->slave.dev,
1433 "#dma-requests set to default 32 as missing in OF: %d",
1434 ret);
1435 nb_requestors = 32;
1436 };
1437 } else if (pdata && pdata->dma_channels) {
1438 dma_channels = pdata->dma_channels;
1439 nb_requestors = pdata->nb_requestors;
1440 slave_map = pdata->slave_map;
1441 slave_map_cnt = pdata->slave_map_cnt;
1442 } else {
1443 dma_channels = 32; /* default 32 channel */
1444 }
1445
1446 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask);
1447 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask);
1448 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask);
1449 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask);
1450 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy;
1451 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg;
1452 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic;
1453 pdev->slave.filter.map = slave_map;
1454 pdev->slave.filter.mapcnt = slave_map_cnt;
1455 pdev->slave.filter.fn = pxad_filter_fn;
1456
1457 pdev->slave.copy_align = PDMA_ALIGNMENT;
1458 pdev->slave.src_addr_widths = widths;
1459 pdev->slave.dst_addr_widths = widths;
1460 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1461 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1462 pdev->slave.descriptor_reuse = true;
1463
1464 pdev->slave.dev = &op->dev;
1465 ret = pxad_init_dmadev(op, pdev, dma_channels, nb_requestors);
1466 if (ret) {
1467 dev_err(pdev->slave.dev, "unable to register\n");
1468 return ret;
1469 }
1470
1471 if (op->dev.of_node) {
1472 /* Device-tree DMA controller registration */
1473 ret = of_dma_controller_register(op->dev.of_node,
1474 pxad_dma_xlate, pdev);
1475 if (ret < 0) {
1476 dev_err(pdev->slave.dev,
1477 "of_dma_controller_register failed\n");
1478 return ret;
1479 }
1480 }
1481
1482 platform_set_drvdata(op, pdev);
1483 pxad_init_debugfs(pdev);
1484 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n",
1485 dma_channels, nb_requestors);
1486 return 0;
1487 }
1488
1489 static const struct platform_device_id pxad_id_table[] = {
1490 { "pxa-dma", },
1491 { },
1492 };
1493
1494 static struct platform_driver pxad_driver = {
1495 .driver = {
1496 .name = "pxa-dma",
1497 .of_match_table = pxad_dt_ids,
1498 },
1499 .id_table = pxad_id_table,
1500 .probe = pxad_probe,
1501 .remove = pxad_remove,
1502 };
1503
1504 bool pxad_filter_fn(struct dma_chan *chan, void *param)
1505 {
1506 struct pxad_chan *c = to_pxad_chan(chan);
1507 struct pxad_param *p = param;
1508
1509 if (chan->device->dev->driver != &pxad_driver.driver)
1510 return false;
1511
1512 c->drcmr = p->drcmr;
1513 c->prio = p->prio;
1514
1515 return true;
1516 }
1517 EXPORT_SYMBOL_GPL(pxad_filter_fn);
1518
1519 module_platform_driver(pxad_driver);
1520
1521 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");
1522 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
1523 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support