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Linux 4.19.133
[linux/fpc-iii.git] / drivers / dma / sprd-dma.c
blob9e8ce56a83d8a65e4e9410ddbbea32edd38388ab
1 /*
2 * Copyright (C) 2017 Spreadtrum Communications Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <linux/clk.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/dma/sprd-dma.h>
10 #include <linux/errno.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_dma.h>
18 #include <linux/of_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/slab.h>
21
22 #include "virt-dma.h"
23
24 #define SPRD_DMA_CHN_REG_OFFSET 0x1000
25 #define SPRD_DMA_CHN_REG_LENGTH 0x40
26 #define SPRD_DMA_MEMCPY_MIN_SIZE 64
27
28 /* DMA global registers definition */
29 #define SPRD_DMA_GLB_PAUSE 0x0
30 #define SPRD_DMA_GLB_FRAG_WAIT 0x4
31 #define SPRD_DMA_GLB_REQ_PEND0_EN 0x8
32 #define SPRD_DMA_GLB_REQ_PEND1_EN 0xc
33 #define SPRD_DMA_GLB_INT_RAW_STS 0x10
34 #define SPRD_DMA_GLB_INT_MSK_STS 0x14
35 #define SPRD_DMA_GLB_REQ_STS 0x18
36 #define SPRD_DMA_GLB_CHN_EN_STS 0x1c
37 #define SPRD_DMA_GLB_DEBUG_STS 0x20
38 #define SPRD_DMA_GLB_ARB_SEL_STS 0x24
39 #define SPRD_DMA_GLB_REQ_UID(uid) (0x4 * ((uid) - 1))
40 #define SPRD_DMA_GLB_REQ_UID_OFFSET 0x2000
41
42 /* DMA channel registers definition */
43 #define SPRD_DMA_CHN_PAUSE 0x0
44 #define SPRD_DMA_CHN_REQ 0x4
45 #define SPRD_DMA_CHN_CFG 0x8
46 #define SPRD_DMA_CHN_INTC 0xc
47 #define SPRD_DMA_CHN_SRC_ADDR 0x10
48 #define SPRD_DMA_CHN_DES_ADDR 0x14
49 #define SPRD_DMA_CHN_FRG_LEN 0x18
50 #define SPRD_DMA_CHN_BLK_LEN 0x1c
51 #define SPRD_DMA_CHN_TRSC_LEN 0x20
52 #define SPRD_DMA_CHN_TRSF_STEP 0x24
53 #define SPRD_DMA_CHN_WARP_PTR 0x28
54 #define SPRD_DMA_CHN_WARP_TO 0x2c
55 #define SPRD_DMA_CHN_LLIST_PTR 0x30
56 #define SPRD_DMA_CHN_FRAG_STEP 0x34
57 #define SPRD_DMA_CHN_SRC_BLK_STEP 0x38
58 #define SPRD_DMA_CHN_DES_BLK_STEP 0x3c
59
60 /* SPRD_DMA_CHN_INTC register definition */
61 #define SPRD_DMA_INT_MASK GENMASK(4, 0)
62 #define SPRD_DMA_INT_CLR_OFFSET 24
63 #define SPRD_DMA_FRAG_INT_EN BIT(0)
64 #define SPRD_DMA_BLK_INT_EN BIT(1)
65 #define SPRD_DMA_TRANS_INT_EN BIT(2)
66 #define SPRD_DMA_LIST_INT_EN BIT(3)
67 #define SPRD_DMA_CFG_ERR_INT_EN BIT(4)
68
69 /* SPRD_DMA_CHN_CFG register definition */
70 #define SPRD_DMA_CHN_EN BIT(0)
71 #define SPRD_DMA_WAIT_BDONE_OFFSET 24
72 #define SPRD_DMA_DONOT_WAIT_BDONE 1
73
74 /* SPRD_DMA_CHN_REQ register definition */
75 #define SPRD_DMA_REQ_EN BIT(0)
76
77 /* SPRD_DMA_CHN_PAUSE register definition */
78 #define SPRD_DMA_PAUSE_EN BIT(0)
79 #define SPRD_DMA_PAUSE_STS BIT(2)
80 #define SPRD_DMA_PAUSE_CNT 0x2000
81
82 /* DMA_CHN_WARP_* register definition */
83 #define SPRD_DMA_HIGH_ADDR_MASK GENMASK(31, 28)
84 #define SPRD_DMA_LOW_ADDR_MASK GENMASK(31, 0)
85 #define SPRD_DMA_HIGH_ADDR_OFFSET 4
86
87 /* SPRD_DMA_CHN_INTC register definition */
88 #define SPRD_DMA_FRAG_INT_STS BIT(16)
89 #define SPRD_DMA_BLK_INT_STS BIT(17)
90 #define SPRD_DMA_TRSC_INT_STS BIT(18)
91 #define SPRD_DMA_LIST_INT_STS BIT(19)
92 #define SPRD_DMA_CFGERR_INT_STS BIT(20)
93 #define SPRD_DMA_CHN_INT_STS \
94 (SPRD_DMA_FRAG_INT_STS | SPRD_DMA_BLK_INT_STS | \
95 SPRD_DMA_TRSC_INT_STS | SPRD_DMA_LIST_INT_STS | \
96 SPRD_DMA_CFGERR_INT_STS)
97
98 /* SPRD_DMA_CHN_FRG_LEN register definition */
99 #define SPRD_DMA_SRC_DATAWIDTH_OFFSET 30
100 #define SPRD_DMA_DES_DATAWIDTH_OFFSET 28
101 #define SPRD_DMA_SWT_MODE_OFFSET 26
102 #define SPRD_DMA_REQ_MODE_OFFSET 24
103 #define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0)
104 #define SPRD_DMA_FIX_SEL_OFFSET 21
105 #define SPRD_DMA_FIX_EN_OFFSET 20
106 #define SPRD_DMA_LLIST_END_OFFSET 19
107 #define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0)
108
109 /* SPRD_DMA_CHN_BLK_LEN register definition */
110 #define SPRD_DMA_BLK_LEN_MASK GENMASK(16, 0)
111
112 /* SPRD_DMA_CHN_TRSC_LEN register definition */
113 #define SPRD_DMA_TRSC_LEN_MASK GENMASK(27, 0)
114
115 /* SPRD_DMA_CHN_TRSF_STEP register definition */
116 #define SPRD_DMA_DEST_TRSF_STEP_OFFSET 16
117 #define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0
118 #define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0)
119
120 /* define the DMA transfer step type */
121 #define SPRD_DMA_NONE_STEP 0
122 #define SPRD_DMA_BYTE_STEP 1
123 #define SPRD_DMA_SHORT_STEP 2
124 #define SPRD_DMA_WORD_STEP 4
125 #define SPRD_DMA_DWORD_STEP 8
126
127 #define SPRD_DMA_SOFTWARE_UID 0
128
129 /* dma data width values */
130 enum sprd_dma_datawidth {
131 SPRD_DMA_DATAWIDTH_1_BYTE,
132 SPRD_DMA_DATAWIDTH_2_BYTES,
133 SPRD_DMA_DATAWIDTH_4_BYTES,
134 SPRD_DMA_DATAWIDTH_8_BYTES,
135 };
136
137 /* dma channel hardware configuration */
138 struct sprd_dma_chn_hw {
139 u32 pause;
140 u32 req;
141 u32 cfg;
142 u32 intc;
143 u32 src_addr;
144 u32 des_addr;
145 u32 frg_len;
146 u32 blk_len;
147 u32 trsc_len;
148 u32 trsf_step;
149 u32 wrap_ptr;
150 u32 wrap_to;
151 u32 llist_ptr;
152 u32 frg_step;
153 u32 src_blk_step;
154 u32 des_blk_step;
155 };
156
157 /* dma request description */
158 struct sprd_dma_desc {
159 struct virt_dma_desc vd;
160 struct sprd_dma_chn_hw chn_hw;
161 };
162
163 /* dma channel description */
164 struct sprd_dma_chn {
165 struct virt_dma_chan vc;
166 void __iomem *chn_base;
167 struct dma_slave_config slave_cfg;
168 u32 chn_num;
169 u32 dev_id;
170 struct sprd_dma_desc *cur_desc;
171 };
172
173 /* SPRD dma device */
174 struct sprd_dma_dev {
175 struct dma_device dma_dev;
176 void __iomem *glb_base;
177 struct clk *clk;
178 struct clk *ashb_clk;
179 int irq;
180 u32 total_chns;
181 struct sprd_dma_chn channels[0];
182 };
183
184 static void sprd_dma_free_desc(struct virt_dma_desc *vd);
185 static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param);
186 static struct of_dma_filter_info sprd_dma_info = {
187 .filter_fn = sprd_dma_filter_fn,
188 };
189
190 static inline struct sprd_dma_chn *to_sprd_dma_chan(struct dma_chan *c)
191 {
192 return container_of(c, struct sprd_dma_chn, vc.chan);
193 }
194
195 static inline struct sprd_dma_dev *to_sprd_dma_dev(struct dma_chan *c)
196 {
197 struct sprd_dma_chn *schan = to_sprd_dma_chan(c);
198
199 return container_of(schan, struct sprd_dma_dev, channels[c->chan_id]);
200 }
201
202 static inline struct sprd_dma_desc *to_sprd_dma_desc(struct virt_dma_desc *vd)
203 {
204 return container_of(vd, struct sprd_dma_desc, vd);
205 }
206
207 static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg,
208 u32 mask, u32 val)
209 {
210 u32 orig = readl(schan->chn_base + reg);
211 u32 tmp;
212
213 tmp = (orig & ~mask) | val;
214 writel(tmp, schan->chn_base + reg);
215 }
216
217 static int sprd_dma_enable(struct sprd_dma_dev *sdev)
218 {
219 int ret;
220
221 ret = clk_prepare_enable(sdev->clk);
222 if (ret)
223 return ret;
224
225 /*
226 * The ashb_clk is optional and only for AGCP DMA controller, so we
227 * need add one condition to check if the ashb_clk need enable.
228 */
229 if (!IS_ERR(sdev->ashb_clk))
230 ret = clk_prepare_enable(sdev->ashb_clk);
231
232 return ret;
233 }
234
235 static void sprd_dma_disable(struct sprd_dma_dev *sdev)
236 {
237 clk_disable_unprepare(sdev->clk);
238
239 /*
240 * Need to check if we need disable the optional ashb_clk for AGCP DMA.
241 */
242 if (!IS_ERR(sdev->ashb_clk))
243 clk_disable_unprepare(sdev->ashb_clk);
244 }
245
246 static void sprd_dma_set_uid(struct sprd_dma_chn *schan)
247 {
248 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
249 u32 dev_id = schan->dev_id;
250
251 if (dev_id != SPRD_DMA_SOFTWARE_UID) {
252 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
253 SPRD_DMA_GLB_REQ_UID(dev_id);
254
255 writel(schan->chn_num + 1, sdev->glb_base + uid_offset);
256 }
257 }
258
259 static void sprd_dma_unset_uid(struct sprd_dma_chn *schan)
260 {
261 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
262 u32 dev_id = schan->dev_id;
263
264 if (dev_id != SPRD_DMA_SOFTWARE_UID) {
265 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET +
266 SPRD_DMA_GLB_REQ_UID(dev_id);
267
268 writel(0, sdev->glb_base + uid_offset);
269 }
270 }
271
272 static void sprd_dma_clear_int(struct sprd_dma_chn *schan)
273 {
274 sprd_dma_chn_update(schan, SPRD_DMA_CHN_INTC,
275 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET,
276 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET);
277 }
278
279 static void sprd_dma_enable_chn(struct sprd_dma_chn *schan)
280 {
281 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN,
282 SPRD_DMA_CHN_EN);
283 }
284
285 static void sprd_dma_disable_chn(struct sprd_dma_chn *schan)
286 {
287 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN, 0);
288 }
289
290 static void sprd_dma_soft_request(struct sprd_dma_chn *schan)
291 {
292 sprd_dma_chn_update(schan, SPRD_DMA_CHN_REQ, SPRD_DMA_REQ_EN,
293 SPRD_DMA_REQ_EN);
294 }
295
296 static void sprd_dma_pause_resume(struct sprd_dma_chn *schan, bool enable)
297 {
298 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
299 u32 pause, timeout = SPRD_DMA_PAUSE_CNT;
300
301 if (enable) {
302 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
303 SPRD_DMA_PAUSE_EN, SPRD_DMA_PAUSE_EN);
304
305 do {
306 pause = readl(schan->chn_base + SPRD_DMA_CHN_PAUSE);
307 if (pause & SPRD_DMA_PAUSE_STS)
308 break;
309
310 cpu_relax();
311 } while (--timeout > 0);
312
313 if (!timeout)
314 dev_warn(sdev->dma_dev.dev,
315 "pause dma controller timeout\n");
316 } else {
317 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE,
318 SPRD_DMA_PAUSE_EN, 0);
319 }
320 }
321
322 static void sprd_dma_stop_and_disable(struct sprd_dma_chn *schan)
323 {
324 u32 cfg = readl(schan->chn_base + SPRD_DMA_CHN_CFG);
325
326 if (!(cfg & SPRD_DMA_CHN_EN))
327 return;
328
329 sprd_dma_pause_resume(schan, true);
330 sprd_dma_disable_chn(schan);
331 }
332
333 static unsigned long sprd_dma_get_dst_addr(struct sprd_dma_chn *schan)
334 {
335 unsigned long addr, addr_high;
336
337 addr = readl(schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
338 addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_TO) &
339 SPRD_DMA_HIGH_ADDR_MASK;
340
341 return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET);
342 }
343
344 static enum sprd_dma_int_type sprd_dma_get_int_type(struct sprd_dma_chn *schan)
345 {
346 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
347 u32 intc_sts = readl(schan->chn_base + SPRD_DMA_CHN_INTC) &
348 SPRD_DMA_CHN_INT_STS;
349
350 switch (intc_sts) {
351 case SPRD_DMA_CFGERR_INT_STS:
352 return SPRD_DMA_CFGERR_INT;
353
354 case SPRD_DMA_LIST_INT_STS:
355 return SPRD_DMA_LIST_INT;
356
357 case SPRD_DMA_TRSC_INT_STS:
358 return SPRD_DMA_TRANS_INT;
359
360 case SPRD_DMA_BLK_INT_STS:
361 return SPRD_DMA_BLK_INT;
362
363 case SPRD_DMA_FRAG_INT_STS:
364 return SPRD_DMA_FRAG_INT;
365
366 default:
367 dev_warn(sdev->dma_dev.dev, "incorrect dma interrupt type\n");
368 return SPRD_DMA_NO_INT;
369 }
370 }
371
372 static enum sprd_dma_req_mode sprd_dma_get_req_type(struct sprd_dma_chn *schan)
373 {
374 u32 frag_reg = readl(schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
375
376 return (frag_reg >> SPRD_DMA_REQ_MODE_OFFSET) & SPRD_DMA_REQ_MODE_MASK;
377 }
378
379 static void sprd_dma_set_chn_config(struct sprd_dma_chn *schan,
380 struct sprd_dma_desc *sdesc)
381 {
382 struct sprd_dma_chn_hw *cfg = &sdesc->chn_hw;
383
384 writel(cfg->pause, schan->chn_base + SPRD_DMA_CHN_PAUSE);
385 writel(cfg->cfg, schan->chn_base + SPRD_DMA_CHN_CFG);
386 writel(cfg->intc, schan->chn_base + SPRD_DMA_CHN_INTC);
387 writel(cfg->src_addr, schan->chn_base + SPRD_DMA_CHN_SRC_ADDR);
388 writel(cfg->des_addr, schan->chn_base + SPRD_DMA_CHN_DES_ADDR);
389 writel(cfg->frg_len, schan->chn_base + SPRD_DMA_CHN_FRG_LEN);
390 writel(cfg->blk_len, schan->chn_base + SPRD_DMA_CHN_BLK_LEN);
391 writel(cfg->trsc_len, schan->chn_base + SPRD_DMA_CHN_TRSC_LEN);
392 writel(cfg->trsf_step, schan->chn_base + SPRD_DMA_CHN_TRSF_STEP);
393 writel(cfg->wrap_ptr, schan->chn_base + SPRD_DMA_CHN_WARP_PTR);
394 writel(cfg->wrap_to, schan->chn_base + SPRD_DMA_CHN_WARP_TO);
395 writel(cfg->llist_ptr, schan->chn_base + SPRD_DMA_CHN_LLIST_PTR);
396 writel(cfg->frg_step, schan->chn_base + SPRD_DMA_CHN_FRAG_STEP);
397 writel(cfg->src_blk_step, schan->chn_base + SPRD_DMA_CHN_SRC_BLK_STEP);
398 writel(cfg->des_blk_step, schan->chn_base + SPRD_DMA_CHN_DES_BLK_STEP);
399 writel(cfg->req, schan->chn_base + SPRD_DMA_CHN_REQ);
400 }
401
402 static void sprd_dma_start(struct sprd_dma_chn *schan)
403 {
404 struct virt_dma_desc *vd = vchan_next_desc(&schan->vc);
405
406 if (!vd)
407 return;
408
409 list_del(&vd->node);
410 schan->cur_desc = to_sprd_dma_desc(vd);
411
412 /*
413 * Copy the DMA configuration from DMA descriptor to this hardware
414 * channel.
415 */
416 sprd_dma_set_chn_config(schan, schan->cur_desc);
417 sprd_dma_set_uid(schan);
418 sprd_dma_enable_chn(schan);
419
420 if (schan->dev_id == SPRD_DMA_SOFTWARE_UID)
421 sprd_dma_soft_request(schan);
422 }
423
424 static void sprd_dma_stop(struct sprd_dma_chn *schan)
425 {
426 sprd_dma_stop_and_disable(schan);
427 sprd_dma_unset_uid(schan);
428 sprd_dma_clear_int(schan);
429 }
430
431 static bool sprd_dma_check_trans_done(struct sprd_dma_desc *sdesc,
432 enum sprd_dma_int_type int_type,
433 enum sprd_dma_req_mode req_mode)
434 {
435 if (int_type == SPRD_DMA_NO_INT)
436 return false;
437
438 if (int_type >= req_mode + 1)
439 return true;
440 else
441 return false;
442 }
443
444 static irqreturn_t dma_irq_handle(int irq, void *dev_id)
445 {
446 struct sprd_dma_dev *sdev = (struct sprd_dma_dev *)dev_id;
447 u32 irq_status = readl(sdev->glb_base + SPRD_DMA_GLB_INT_MSK_STS);
448 struct sprd_dma_chn *schan;
449 struct sprd_dma_desc *sdesc;
450 enum sprd_dma_req_mode req_type;
451 enum sprd_dma_int_type int_type;
452 bool trans_done = false;
453 u32 i;
454
455 while (irq_status) {
456 i = __ffs(irq_status);
457 irq_status &= (irq_status - 1);
458 schan = &sdev->channels[i];
459
460 spin_lock(&schan->vc.lock);
461 int_type = sprd_dma_get_int_type(schan);
462 req_type = sprd_dma_get_req_type(schan);
463 sprd_dma_clear_int(schan);
464
465 sdesc = schan->cur_desc;
466
467 /* Check if the dma request descriptor is done. */
468 trans_done = sprd_dma_check_trans_done(sdesc, int_type,
469 req_type);
470 if (trans_done == true) {
471 vchan_cookie_complete(&sdesc->vd);
472 schan->cur_desc = NULL;
473 sprd_dma_start(schan);
474 }
475 spin_unlock(&schan->vc.lock);
476 }
477
478 return IRQ_HANDLED;
479 }
480
481 static int sprd_dma_alloc_chan_resources(struct dma_chan *chan)
482 {
483 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
484 int ret;
485
486 ret = pm_runtime_get_sync(chan->device->dev);
487 if (ret < 0)
488 return ret;
489
490 schan->dev_id = SPRD_DMA_SOFTWARE_UID;
491 return 0;
492 }
493
494 static void sprd_dma_free_chan_resources(struct dma_chan *chan)
495 {
496 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
497 struct virt_dma_desc *cur_vd = NULL;
498 unsigned long flags;
499
500 spin_lock_irqsave(&schan->vc.lock, flags);
501 if (schan->cur_desc)
502 cur_vd = &schan->cur_desc->vd;
503
504 sprd_dma_stop(schan);
505 spin_unlock_irqrestore(&schan->vc.lock, flags);
506
507 if (cur_vd)
508 sprd_dma_free_desc(cur_vd);
509
510 vchan_free_chan_resources(&schan->vc);
511 pm_runtime_put(chan->device->dev);
512 }
513
514 static enum dma_status sprd_dma_tx_status(struct dma_chan *chan,
515 dma_cookie_t cookie,
516 struct dma_tx_state *txstate)
517 {
518 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
519 struct virt_dma_desc *vd;
520 unsigned long flags;
521 enum dma_status ret;
522 u32 pos;
523
524 ret = dma_cookie_status(chan, cookie, txstate);
525 if (ret == DMA_COMPLETE || !txstate)
526 return ret;
527
528 spin_lock_irqsave(&schan->vc.lock, flags);
529 vd = vchan_find_desc(&schan->vc, cookie);
530 if (vd) {
531 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
532 struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
533
534 if (hw->trsc_len > 0)
535 pos = hw->trsc_len;
536 else if (hw->blk_len > 0)
537 pos = hw->blk_len;
538 else if (hw->frg_len > 0)
539 pos = hw->frg_len;
540 else
541 pos = 0;
542 } else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) {
543 pos = sprd_dma_get_dst_addr(schan);
544 } else {
545 pos = 0;
546 }
547 spin_unlock_irqrestore(&schan->vc.lock, flags);
548
549 dma_set_residue(txstate, pos);
550 return ret;
551 }
552
553 static void sprd_dma_issue_pending(struct dma_chan *chan)
554 {
555 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
556 unsigned long flags;
557
558 spin_lock_irqsave(&schan->vc.lock, flags);
559 if (vchan_issue_pending(&schan->vc) && !schan->cur_desc)
560 sprd_dma_start(schan);
561 spin_unlock_irqrestore(&schan->vc.lock, flags);
562 }
563
564 static int sprd_dma_get_datawidth(enum dma_slave_buswidth buswidth)
565 {
566 switch (buswidth) {
567 case DMA_SLAVE_BUSWIDTH_1_BYTE:
568 case DMA_SLAVE_BUSWIDTH_2_BYTES:
569 case DMA_SLAVE_BUSWIDTH_4_BYTES:
570 case DMA_SLAVE_BUSWIDTH_8_BYTES:
571 return ffs(buswidth) - 1;
572
573 default:
574 return -EINVAL;
575 }
576 }
577
578 static int sprd_dma_get_step(enum dma_slave_buswidth buswidth)
579 {
580 switch (buswidth) {
581 case DMA_SLAVE_BUSWIDTH_1_BYTE:
582 case DMA_SLAVE_BUSWIDTH_2_BYTES:
583 case DMA_SLAVE_BUSWIDTH_4_BYTES:
584 case DMA_SLAVE_BUSWIDTH_8_BYTES:
585 return buswidth;
586
587 default:
588 return -EINVAL;
589 }
590 }
591
592 static int sprd_dma_fill_desc(struct dma_chan *chan,
593 struct sprd_dma_desc *sdesc,
594 dma_addr_t src, dma_addr_t dst, u32 len,
595 enum dma_transfer_direction dir,
596 unsigned long flags,
597 struct dma_slave_config *slave_cfg)
598 {
599 struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan);
600 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
601 struct sprd_dma_chn_hw *hw = &sdesc->chn_hw;
602 u32 req_mode = (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK;
603 u32 int_mode = flags & SPRD_DMA_INT_MASK;
604 int src_datawidth, dst_datawidth, src_step, dst_step;
605 u32 temp, fix_mode = 0, fix_en = 0;
606
607 if (dir == DMA_MEM_TO_DEV) {
608 src_step = sprd_dma_get_step(slave_cfg->src_addr_width);
609 if (src_step < 0) {
610 dev_err(sdev->dma_dev.dev, "invalid source step\n");
611 return src_step;
612 }
613 dst_step = SPRD_DMA_NONE_STEP;
614 } else {
615 dst_step = sprd_dma_get_step(slave_cfg->dst_addr_width);
616 if (dst_step < 0) {
617 dev_err(sdev->dma_dev.dev, "invalid destination step\n");
618 return dst_step;
619 }
620 src_step = SPRD_DMA_NONE_STEP;
621 }
622
623 src_datawidth = sprd_dma_get_datawidth(slave_cfg->src_addr_width);
624 if (src_datawidth < 0) {
625 dev_err(sdev->dma_dev.dev, "invalid source datawidth\n");
626 return src_datawidth;
627 }
628
629 dst_datawidth = sprd_dma_get_datawidth(slave_cfg->dst_addr_width);
630 if (dst_datawidth < 0) {
631 dev_err(sdev->dma_dev.dev, "invalid destination datawidth\n");
632 return dst_datawidth;
633 }
634
635 if (slave_cfg->slave_id)
636 schan->dev_id = slave_cfg->slave_id;
637
638 hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
639
640 /*
641 * wrap_ptr and wrap_to will save the high 4 bits source address and
642 * destination address.
643 */
644 hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK;
645 hw->wrap_to = (dst >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK;
646 hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK;
647 hw->des_addr = dst & SPRD_DMA_LOW_ADDR_MASK;
648
649 /*
650 * If the src step and dst step both are 0 or both are not 0, that means
651 * we can not enable the fix mode. If one is 0 and another one is not,
652 * we can enable the fix mode.
653 */
654 if ((src_step != 0 && dst_step != 0) || (src_step | dst_step) == 0) {
655 fix_en = 0;
656 } else {
657 fix_en = 1;
658 if (src_step)
659 fix_mode = 1;
660 else
661 fix_mode = 0;
662 }
663
664 hw->intc = int_mode | SPRD_DMA_CFG_ERR_INT_EN;
665
666 temp = src_datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET;
667 temp |= dst_datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET;
668 temp |= req_mode << SPRD_DMA_REQ_MODE_OFFSET;
669 temp |= fix_mode << SPRD_DMA_FIX_SEL_OFFSET;
670 temp |= fix_en << SPRD_DMA_FIX_EN_OFFSET;
671 temp |= slave_cfg->src_maxburst & SPRD_DMA_FRG_LEN_MASK;
672 hw->frg_len = temp;
673
674 hw->blk_len = slave_cfg->src_maxburst & SPRD_DMA_BLK_LEN_MASK;
675 hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK;
676
677 temp = (dst_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET;
678 temp |= (src_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET;
679 hw->trsf_step = temp;
680
681 hw->frg_step = 0;
682 hw->src_blk_step = 0;
683 hw->des_blk_step = 0;
684 return 0;
685 }
686
687 static struct dma_async_tx_descriptor *
688 sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
689 size_t len, unsigned long flags)
690 {
691 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
692 struct sprd_dma_desc *sdesc;
693 struct sprd_dma_chn_hw *hw;
694 enum sprd_dma_datawidth datawidth;
695 u32 step, temp;
696
697 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
698 if (!sdesc)
699 return NULL;
700
701 hw = &sdesc->chn_hw;
702
703 hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET;
704 hw->intc = SPRD_DMA_TRANS_INT | SPRD_DMA_CFG_ERR_INT_EN;
705 hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK;
706 hw->des_addr = dest & SPRD_DMA_LOW_ADDR_MASK;
707 hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) &
708 SPRD_DMA_HIGH_ADDR_MASK;
709 hw->wrap_to = (dest >> SPRD_DMA_HIGH_ADDR_OFFSET) &
710 SPRD_DMA_HIGH_ADDR_MASK;
711
712 if (IS_ALIGNED(len, 8)) {
713 datawidth = SPRD_DMA_DATAWIDTH_8_BYTES;
714 step = SPRD_DMA_DWORD_STEP;
715 } else if (IS_ALIGNED(len, 4)) {
716 datawidth = SPRD_DMA_DATAWIDTH_4_BYTES;
717 step = SPRD_DMA_WORD_STEP;
718 } else if (IS_ALIGNED(len, 2)) {
719 datawidth = SPRD_DMA_DATAWIDTH_2_BYTES;
720 step = SPRD_DMA_SHORT_STEP;
721 } else {
722 datawidth = SPRD_DMA_DATAWIDTH_1_BYTE;
723 step = SPRD_DMA_BYTE_STEP;
724 }
725
726 temp = datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET;
727 temp |= datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET;
728 temp |= SPRD_DMA_TRANS_REQ << SPRD_DMA_REQ_MODE_OFFSET;
729 temp |= len & SPRD_DMA_FRG_LEN_MASK;
730 hw->frg_len = temp;
731
732 hw->blk_len = len & SPRD_DMA_BLK_LEN_MASK;
733 hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK;
734
735 temp = (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET;
736 temp |= (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET;
737 hw->trsf_step = temp;
738
739 return vchan_tx_prep(&schan->vc, &sdesc->vd, flags);
740 }
741
742 static struct dma_async_tx_descriptor *
743 sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
744 unsigned int sglen, enum dma_transfer_direction dir,
745 unsigned long flags, void *context)
746 {
747 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
748 struct dma_slave_config *slave_cfg = &schan->slave_cfg;
749 dma_addr_t src = 0, dst = 0;
750 struct sprd_dma_desc *sdesc;
751 struct scatterlist *sg;
752 u32 len = 0;
753 int ret, i;
754
755 /* TODO: now we only support one sg for each DMA configuration. */
756 if (!is_slave_direction(dir) || sglen > 1)
757 return NULL;
758
759 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT);
760 if (!sdesc)
761 return NULL;
762
763 for_each_sg(sgl, sg, sglen, i) {
764 len = sg_dma_len(sg);
765
766 if (dir == DMA_MEM_TO_DEV) {
767 src = sg_dma_address(sg);
768 dst = slave_cfg->dst_addr;
769 } else {
770 src = slave_cfg->src_addr;
771 dst = sg_dma_address(sg);
772 }
773 }
774
775 ret = sprd_dma_fill_desc(chan, sdesc, src, dst, len, dir, flags,
776 slave_cfg);
777 if (ret) {
778 kfree(sdesc);
779 return NULL;
780 }
781
782 return vchan_tx_prep(&schan->vc, &sdesc->vd, flags);
783 }
784
785 static int sprd_dma_slave_config(struct dma_chan *chan,
786 struct dma_slave_config *config)
787 {
788 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
789 struct dma_slave_config *slave_cfg = &schan->slave_cfg;
790
791 if (!is_slave_direction(config->direction))
792 return -EINVAL;
793
794 memcpy(slave_cfg, config, sizeof(*config));
795 return 0;
796 }
797
798 static int sprd_dma_pause(struct dma_chan *chan)
799 {
800 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
801 unsigned long flags;
802
803 spin_lock_irqsave(&schan->vc.lock, flags);
804 sprd_dma_pause_resume(schan, true);
805 spin_unlock_irqrestore(&schan->vc.lock, flags);
806
807 return 0;
808 }
809
810 static int sprd_dma_resume(struct dma_chan *chan)
811 {
812 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
813 unsigned long flags;
814
815 spin_lock_irqsave(&schan->vc.lock, flags);
816 sprd_dma_pause_resume(schan, false);
817 spin_unlock_irqrestore(&schan->vc.lock, flags);
818
819 return 0;
820 }
821
822 static int sprd_dma_terminate_all(struct dma_chan *chan)
823 {
824 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
825 struct virt_dma_desc *cur_vd = NULL;
826 unsigned long flags;
827 LIST_HEAD(head);
828
829 spin_lock_irqsave(&schan->vc.lock, flags);
830 if (schan->cur_desc)
831 cur_vd = &schan->cur_desc->vd;
832
833 sprd_dma_stop(schan);
834
835 vchan_get_all_descriptors(&schan->vc, &head);
836 spin_unlock_irqrestore(&schan->vc.lock, flags);
837
838 if (cur_vd)
839 sprd_dma_free_desc(cur_vd);
840
841 vchan_dma_desc_free_list(&schan->vc, &head);
842 return 0;
843 }
844
845 static void sprd_dma_free_desc(struct virt_dma_desc *vd)
846 {
847 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd);
848
849 kfree(sdesc);
850 }
851
852 static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param)
853 {
854 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan);
855 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan);
856 u32 req = *(u32 *)param;
857
858 if (req < sdev->total_chns)
859 return req == schan->chn_num + 1;
860 else
861 return false;
862 }
863
864 static int sprd_dma_probe(struct platform_device *pdev)
865 {
866 struct device_node *np = pdev->dev.of_node;
867 struct sprd_dma_dev *sdev;
868 struct sprd_dma_chn *dma_chn;
869 struct resource *res;
870 u32 chn_count;
871 int ret, i;
872
873 ret = device_property_read_u32(&pdev->dev, "#dma-channels", &chn_count);
874 if (ret) {
875 dev_err(&pdev->dev, "get dma channels count failed\n");
876 return ret;
877 }
878
879 sdev = devm_kzalloc(&pdev->dev,
880 struct_size(sdev, channels, chn_count),
881 GFP_KERNEL);
882 if (!sdev)
883 return -ENOMEM;
884
885 sdev->clk = devm_clk_get(&pdev->dev, "enable");
886 if (IS_ERR(sdev->clk)) {
887 dev_err(&pdev->dev, "get enable clock failed\n");
888 return PTR_ERR(sdev->clk);
889 }
890
891 /* ashb clock is optional for AGCP DMA */
892 sdev->ashb_clk = devm_clk_get(&pdev->dev, "ashb_eb");
893 if (IS_ERR(sdev->ashb_clk))
894 dev_warn(&pdev->dev, "no optional ashb eb clock\n");
895
896 /*
897 * We have three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
898 * DMA controller, it can or do not request the irq, which will save
899 * system power without resuming system by DMA interrupts if AGCP DMA
900 * does not request the irq. Thus the DMA interrupts property should
901 * be optional.
902 */
903 sdev->irq = platform_get_irq(pdev, 0);
904 if (sdev->irq > 0) {
905 ret = devm_request_irq(&pdev->dev, sdev->irq, dma_irq_handle,
906 0, "sprd_dma", (void *)sdev);
907 if (ret < 0) {
908 dev_err(&pdev->dev, "request dma irq failed\n");
909 return ret;
910 }
911 } else {
912 dev_warn(&pdev->dev, "no interrupts for the dma controller\n");
913 }
914
915 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
916 sdev->glb_base = devm_ioremap_resource(&pdev->dev, res);
917 if (IS_ERR(sdev->glb_base))
918 return PTR_ERR(sdev->glb_base);
919
920 dma_cap_set(DMA_MEMCPY, sdev->dma_dev.cap_mask);
921 sdev->total_chns = chn_count;
922 sdev->dma_dev.chancnt = chn_count;
923 INIT_LIST_HEAD(&sdev->dma_dev.channels);
924 INIT_LIST_HEAD(&sdev->dma_dev.global_node);
925 sdev->dma_dev.dev = &pdev->dev;
926 sdev->dma_dev.device_alloc_chan_resources = sprd_dma_alloc_chan_resources;
927 sdev->dma_dev.device_free_chan_resources = sprd_dma_free_chan_resources;
928 sdev->dma_dev.device_tx_status = sprd_dma_tx_status;
929 sdev->dma_dev.device_issue_pending = sprd_dma_issue_pending;
930 sdev->dma_dev.device_prep_dma_memcpy = sprd_dma_prep_dma_memcpy;
931 sdev->dma_dev.device_prep_slave_sg = sprd_dma_prep_slave_sg;
932 sdev->dma_dev.device_config = sprd_dma_slave_config;
933 sdev->dma_dev.device_pause = sprd_dma_pause;
934 sdev->dma_dev.device_resume = sprd_dma_resume;
935 sdev->dma_dev.device_terminate_all = sprd_dma_terminate_all;
936
937 for (i = 0; i < chn_count; i++) {
938 dma_chn = &sdev->channels[i];
939 dma_chn->chn_num = i;
940 dma_chn->cur_desc = NULL;
941 /* get each channel's registers base address. */
942 dma_chn->chn_base = sdev->glb_base + SPRD_DMA_CHN_REG_OFFSET +
943 SPRD_DMA_CHN_REG_LENGTH * i;
944
945 dma_chn->vc.desc_free = sprd_dma_free_desc;
946 vchan_init(&dma_chn->vc, &sdev->dma_dev);
947 }
948
949 platform_set_drvdata(pdev, sdev);
950 ret = sprd_dma_enable(sdev);
951 if (ret)
952 return ret;
953
954 pm_runtime_set_active(&pdev->dev);
955 pm_runtime_enable(&pdev->dev);
956
957 ret = pm_runtime_get_sync(&pdev->dev);
958 if (ret < 0)
959 goto err_rpm;
960
961 ret = dma_async_device_register(&sdev->dma_dev);
962 if (ret < 0) {
963 dev_err(&pdev->dev, "register dma device failed:%d\n", ret);
964 goto err_register;
965 }
966
967 sprd_dma_info.dma_cap = sdev->dma_dev.cap_mask;
968 ret = of_dma_controller_register(np, of_dma_simple_xlate,
969 &sprd_dma_info);
970 if (ret)
971 goto err_of_register;
972
973 pm_runtime_put(&pdev->dev);
974 return 0;
975
976 err_of_register:
977 dma_async_device_unregister(&sdev->dma_dev);
978 err_register:
979 pm_runtime_put_noidle(&pdev->dev);
980 pm_runtime_disable(&pdev->dev);
981 err_rpm:
982 sprd_dma_disable(sdev);
983 return ret;
984 }
985
986 static int sprd_dma_remove(struct platform_device *pdev)
987 {
988 struct sprd_dma_dev *sdev = platform_get_drvdata(pdev);
989 struct sprd_dma_chn *c, *cn;
990 int ret;
991
992 ret = pm_runtime_get_sync(&pdev->dev);
993 if (ret < 0)
994 return ret;
995
996 /* explicitly free the irq */
997 if (sdev->irq > 0)
998 devm_free_irq(&pdev->dev, sdev->irq, sdev);
999
1000 list_for_each_entry_safe(c, cn, &sdev->dma_dev.channels,
1001 vc.chan.device_node) {
1002 list_del(&c->vc.chan.device_node);
1003 tasklet_kill(&c->vc.task);
1004 }
1005
1006 of_dma_controller_free(pdev->dev.of_node);
1007 dma_async_device_unregister(&sdev->dma_dev);
1008 sprd_dma_disable(sdev);
1009
1010 pm_runtime_put_noidle(&pdev->dev);
1011 pm_runtime_disable(&pdev->dev);
1012 return 0;
1013 }
1014
1015 static const struct of_device_id sprd_dma_match[] = {
1016 { .compatible = "sprd,sc9860-dma", },
1017 {},
1018 };
1019
1020 static int __maybe_unused sprd_dma_runtime_suspend(struct device *dev)
1021 {
1022 struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
1023
1024 sprd_dma_disable(sdev);
1025 return 0;
1026 }
1027
1028 static int __maybe_unused sprd_dma_runtime_resume(struct device *dev)
1029 {
1030 struct sprd_dma_dev *sdev = dev_get_drvdata(dev);
1031 int ret;
1032
1033 ret = sprd_dma_enable(sdev);
1034 if (ret)
1035 dev_err(sdev->dma_dev.dev, "enable dma failed\n");
1036
1037 return ret;
1038 }
1039
1040 static const struct dev_pm_ops sprd_dma_pm_ops = {
1041 SET_RUNTIME_PM_OPS(sprd_dma_runtime_suspend,
1042 sprd_dma_runtime_resume,
1043 NULL)
1044 };
1045
1046 static struct platform_driver sprd_dma_driver = {
1047 .probe = sprd_dma_probe,
1048 .remove = sprd_dma_remove,
1049 .driver = {
1050 .name = "sprd-dma",
1051 .of_match_table = sprd_dma_match,
1052 .pm = &sprd_dma_pm_ops,
1053 },
1054 };
1055 module_platform_driver(sprd_dma_driver);
1056
1057 MODULE_LICENSE("GPL v2");
1058 MODULE_DESCRIPTION("DMA driver for Spreadtrum");
1059 MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
1060 MODULE_ALIAS("platform:sprd-dma");
Linux with added FPC-III support