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Linux 4.19.133
[linux/fpc-iii.git] / drivers / dma / tegra20-apb-dma.c
blob15481aeaeecd17b56646b2222db84e53296fa296
1 /*
2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
3 *
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/reset.h>
37 #include <linux/slab.h>
38
39 #include "dmaengine.h"
40
41 #define TEGRA_APBDMA_GENERAL 0x0
42 #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
43
44 #define TEGRA_APBDMA_CONTROL 0x010
45 #define TEGRA_APBDMA_IRQ_MASK 0x01c
46 #define TEGRA_APBDMA_IRQ_MASK_SET 0x020
47
48 /* CSR register */
49 #define TEGRA_APBDMA_CHAN_CSR 0x00
50 #define TEGRA_APBDMA_CSR_ENB BIT(31)
51 #define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
52 #define TEGRA_APBDMA_CSR_HOLD BIT(29)
53 #define TEGRA_APBDMA_CSR_DIR BIT(28)
54 #define TEGRA_APBDMA_CSR_ONCE BIT(27)
55 #define TEGRA_APBDMA_CSR_FLOW BIT(21)
56 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
57 #define TEGRA_APBDMA_CSR_REQ_SEL_MASK 0x1F
58 #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
59
60 /* STATUS register */
61 #define TEGRA_APBDMA_CHAN_STATUS 0x004
62 #define TEGRA_APBDMA_STATUS_BUSY BIT(31)
63 #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
64 #define TEGRA_APBDMA_STATUS_HALT BIT(29)
65 #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
66 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
67 #define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
68
69 #define TEGRA_APBDMA_CHAN_CSRE 0x00C
70 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
71
72 /* AHB memory address */
73 #define TEGRA_APBDMA_CHAN_AHBPTR 0x010
74
75 /* AHB sequence register */
76 #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
77 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
82 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
83 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
84 #define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
85 #define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
86 #define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
87 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
88 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
89 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
90
91 /* APB address */
92 #define TEGRA_APBDMA_CHAN_APBPTR 0x018
93
94 /* APB sequence register */
95 #define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
100 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
101 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
102 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
103
104 /* Tegra148 specific registers */
105 #define TEGRA_APBDMA_CHAN_WCOUNT 0x20
106
107 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24
108
109 /*
110 * If any burst is in flight and DMA paused then this is the time to complete
111 * on-flight burst and update DMA status register.
112 */
113 #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
114
115 /* Channel base address offset from APBDMA base address */
116 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
117
118 #define TEGRA_APBDMA_SLAVE_ID_INVALID (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1)
119
120 struct tegra_dma;
121
122 /*
123 * tegra_dma_chip_data Tegra chip specific DMA data
124 * @nr_channels: Number of channels available in the controller.
125 * @channel_reg_size: Channel register size/stride.
126 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
127 * @support_channel_pause: Support channel wise pause of dma.
128 * @support_separate_wcount_reg: Support separate word count register.
129 */
130 struct tegra_dma_chip_data {
131 int nr_channels;
132 int channel_reg_size;
133 int max_dma_count;
134 bool support_channel_pause;
135 bool support_separate_wcount_reg;
136 };
137
138 /* DMA channel registers */
139 struct tegra_dma_channel_regs {
140 unsigned long csr;
141 unsigned long ahb_ptr;
142 unsigned long apb_ptr;
143 unsigned long ahb_seq;
144 unsigned long apb_seq;
145 unsigned long wcount;
146 };
147
148 /*
149 * tegra_dma_sg_req: Dma request details to configure hardware. This
150 * contains the details for one transfer to configure DMA hw.
151 * The client's request for data transfer can be broken into multiple
152 * sub-transfer as per requester details and hw support.
153 * This sub transfer get added in the list of transfer and point to Tegra
154 * DMA descriptor which manages the transfer details.
155 */
156 struct tegra_dma_sg_req {
157 struct tegra_dma_channel_regs ch_regs;
158 int req_len;
159 bool configured;
160 bool last_sg;
161 struct list_head node;
162 struct tegra_dma_desc *dma_desc;
163 };
164
165 /*
166 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
167 * This descriptor keep track of transfer status, callbacks and request
168 * counts etc.
169 */
170 struct tegra_dma_desc {
171 struct dma_async_tx_descriptor txd;
172 int bytes_requested;
173 int bytes_transferred;
174 enum dma_status dma_status;
175 struct list_head node;
176 struct list_head tx_list;
177 struct list_head cb_node;
178 int cb_count;
179 };
180
181 struct tegra_dma_channel;
182
183 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
184 bool to_terminate);
185
186 /* tegra_dma_channel: Channel specific information */
187 struct tegra_dma_channel {
188 struct dma_chan dma_chan;
189 char name[30];
190 bool config_init;
191 int id;
192 int irq;
193 void __iomem *chan_addr;
194 spinlock_t lock;
195 bool busy;
196 struct tegra_dma *tdma;
197 bool cyclic;
198
199 /* Different lists for managing the requests */
200 struct list_head free_sg_req;
201 struct list_head pending_sg_req;
202 struct list_head free_dma_desc;
203 struct list_head cb_desc;
204
205 /* ISR handler and tasklet for bottom half of isr handling */
206 dma_isr_handler isr_handler;
207 struct tasklet_struct tasklet;
208
209 /* Channel-slave specific configuration */
210 unsigned int slave_id;
211 struct dma_slave_config dma_sconfig;
212 struct tegra_dma_channel_regs channel_reg;
213 };
214
215 /* tegra_dma: Tegra DMA specific information */
216 struct tegra_dma {
217 struct dma_device dma_dev;
218 struct device *dev;
219 struct clk *dma_clk;
220 struct reset_control *rst;
221 spinlock_t global_lock;
222 void __iomem *base_addr;
223 const struct tegra_dma_chip_data *chip_data;
224
225 /*
226 * Counter for managing global pausing of the DMA controller.
227 * Only applicable for devices that don't support individual
228 * channel pausing.
229 */
230 u32 global_pause_count;
231
232 /* Some register need to be cache before suspend */
233 u32 reg_gen;
234
235 /* Last member of the structure */
236 struct tegra_dma_channel channels[0];
237 };
238
239 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
240 {
241 writel(val, tdma->base_addr + reg);
242 }
243
244 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
245 {
246 return readl(tdma->base_addr + reg);
247 }
248
249 static inline void tdc_write(struct tegra_dma_channel *tdc,
250 u32 reg, u32 val)
251 {
252 writel(val, tdc->chan_addr + reg);
253 }
254
255 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
256 {
257 return readl(tdc->chan_addr + reg);
258 }
259
260 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
261 {
262 return container_of(dc, struct tegra_dma_channel, dma_chan);
263 }
264
265 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
266 struct dma_async_tx_descriptor *td)
267 {
268 return container_of(td, struct tegra_dma_desc, txd);
269 }
270
271 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
272 {
273 return &tdc->dma_chan.dev->device;
274 }
275
276 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
277 static int tegra_dma_runtime_suspend(struct device *dev);
278 static int tegra_dma_runtime_resume(struct device *dev);
279
280 /* Get DMA desc from free list, if not there then allocate it. */
281 static struct tegra_dma_desc *tegra_dma_desc_get(
282 struct tegra_dma_channel *tdc)
283 {
284 struct tegra_dma_desc *dma_desc;
285 unsigned long flags;
286
287 spin_lock_irqsave(&tdc->lock, flags);
288
289 /* Do not allocate if desc are waiting for ack */
290 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
291 if (async_tx_test_ack(&dma_desc->txd) && !dma_desc->cb_count) {
292 list_del(&dma_desc->node);
293 spin_unlock_irqrestore(&tdc->lock, flags);
294 dma_desc->txd.flags = 0;
295 return dma_desc;
296 }
297 }
298
299 spin_unlock_irqrestore(&tdc->lock, flags);
300
301 /* Allocate DMA desc */
302 dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
303 if (!dma_desc)
304 return NULL;
305
306 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
307 dma_desc->txd.tx_submit = tegra_dma_tx_submit;
308 dma_desc->txd.flags = 0;
309 return dma_desc;
310 }
311
312 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
313 struct tegra_dma_desc *dma_desc)
314 {
315 unsigned long flags;
316
317 spin_lock_irqsave(&tdc->lock, flags);
318 if (!list_empty(&dma_desc->tx_list))
319 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
320 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
321 spin_unlock_irqrestore(&tdc->lock, flags);
322 }
323
324 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
325 struct tegra_dma_channel *tdc)
326 {
327 struct tegra_dma_sg_req *sg_req = NULL;
328 unsigned long flags;
329
330 spin_lock_irqsave(&tdc->lock, flags);
331 if (!list_empty(&tdc->free_sg_req)) {
332 sg_req = list_first_entry(&tdc->free_sg_req,
333 typeof(*sg_req), node);
334 list_del(&sg_req->node);
335 spin_unlock_irqrestore(&tdc->lock, flags);
336 return sg_req;
337 }
338 spin_unlock_irqrestore(&tdc->lock, flags);
339
340 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
341
342 return sg_req;
343 }
344
345 static int tegra_dma_slave_config(struct dma_chan *dc,
346 struct dma_slave_config *sconfig)
347 {
348 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
349
350 if (!list_empty(&tdc->pending_sg_req)) {
351 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
352 return -EBUSY;
353 }
354
355 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
356 if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
357 sconfig->device_fc) {
358 if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
359 return -EINVAL;
360 tdc->slave_id = sconfig->slave_id;
361 }
362 tdc->config_init = true;
363 return 0;
364 }
365
366 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
367 bool wait_for_burst_complete)
368 {
369 struct tegra_dma *tdma = tdc->tdma;
370
371 spin_lock(&tdma->global_lock);
372
373 if (tdc->tdma->global_pause_count == 0) {
374 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
375 if (wait_for_burst_complete)
376 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
377 }
378
379 tdc->tdma->global_pause_count++;
380
381 spin_unlock(&tdma->global_lock);
382 }
383
384 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
385 {
386 struct tegra_dma *tdma = tdc->tdma;
387
388 spin_lock(&tdma->global_lock);
389
390 if (WARN_ON(tdc->tdma->global_pause_count == 0))
391 goto out;
392
393 if (--tdc->tdma->global_pause_count == 0)
394 tdma_write(tdma, TEGRA_APBDMA_GENERAL,
395 TEGRA_APBDMA_GENERAL_ENABLE);
396
397 out:
398 spin_unlock(&tdma->global_lock);
399 }
400
401 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
402 bool wait_for_burst_complete)
403 {
404 struct tegra_dma *tdma = tdc->tdma;
405
406 if (tdma->chip_data->support_channel_pause) {
407 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
408 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
409 if (wait_for_burst_complete)
410 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
411 } else {
412 tegra_dma_global_pause(tdc, wait_for_burst_complete);
413 }
414 }
415
416 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
417 {
418 struct tegra_dma *tdma = tdc->tdma;
419
420 if (tdma->chip_data->support_channel_pause) {
421 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
422 } else {
423 tegra_dma_global_resume(tdc);
424 }
425 }
426
427 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
428 {
429 u32 csr;
430 u32 status;
431
432 /* Disable interrupts */
433 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
434 csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
435 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
436
437 /* Disable DMA */
438 csr &= ~TEGRA_APBDMA_CSR_ENB;
439 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
440
441 /* Clear interrupt status if it is there */
442 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
443 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
444 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
445 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
446 }
447 tdc->busy = false;
448 }
449
450 static void tegra_dma_start(struct tegra_dma_channel *tdc,
451 struct tegra_dma_sg_req *sg_req)
452 {
453 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
454
455 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
456 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
457 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
458 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
459 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
460 if (tdc->tdma->chip_data->support_separate_wcount_reg)
461 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
462
463 /* Start DMA */
464 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
465 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
466 }
467
468 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
469 struct tegra_dma_sg_req *nsg_req)
470 {
471 unsigned long status;
472
473 /*
474 * The DMA controller reloads the new configuration for next transfer
475 * after last burst of current transfer completes.
476 * If there is no IEC status then this makes sure that last burst
477 * has not be completed. There may be case that last burst is on
478 * flight and so it can complete but because DMA is paused, it
479 * will not generates interrupt as well as not reload the new
480 * configuration.
481 * If there is already IEC status then interrupt handler need to
482 * load new configuration.
483 */
484 tegra_dma_pause(tdc, false);
485 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
486
487 /*
488 * If interrupt is pending then do nothing as the ISR will handle
489 * the programing for new request.
490 */
491 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
492 dev_err(tdc2dev(tdc),
493 "Skipping new configuration as interrupt is pending\n");
494 tegra_dma_resume(tdc);
495 return;
496 }
497
498 /* Safe to program new configuration */
499 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
500 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
501 if (tdc->tdma->chip_data->support_separate_wcount_reg)
502 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
503 nsg_req->ch_regs.wcount);
504 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
505 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
506 nsg_req->configured = true;
507
508 tegra_dma_resume(tdc);
509 }
510
511 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
512 {
513 struct tegra_dma_sg_req *sg_req;
514
515 if (list_empty(&tdc->pending_sg_req))
516 return;
517
518 sg_req = list_first_entry(&tdc->pending_sg_req,
519 typeof(*sg_req), node);
520 tegra_dma_start(tdc, sg_req);
521 sg_req->configured = true;
522 tdc->busy = true;
523 }
524
525 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
526 {
527 struct tegra_dma_sg_req *hsgreq;
528 struct tegra_dma_sg_req *hnsgreq;
529
530 if (list_empty(&tdc->pending_sg_req))
531 return;
532
533 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
534 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
535 hnsgreq = list_first_entry(&hsgreq->node,
536 typeof(*hnsgreq), node);
537 tegra_dma_configure_for_next(tdc, hnsgreq);
538 }
539 }
540
541 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
542 struct tegra_dma_sg_req *sg_req, unsigned long status)
543 {
544 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
545 }
546
547 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
548 {
549 struct tegra_dma_sg_req *sgreq;
550 struct tegra_dma_desc *dma_desc;
551
552 while (!list_empty(&tdc->pending_sg_req)) {
553 sgreq = list_first_entry(&tdc->pending_sg_req,
554 typeof(*sgreq), node);
555 list_move_tail(&sgreq->node, &tdc->free_sg_req);
556 if (sgreq->last_sg) {
557 dma_desc = sgreq->dma_desc;
558 dma_desc->dma_status = DMA_ERROR;
559 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
560
561 /* Add in cb list if it is not there. */
562 if (!dma_desc->cb_count)
563 list_add_tail(&dma_desc->cb_node,
564 &tdc->cb_desc);
565 dma_desc->cb_count++;
566 }
567 }
568 tdc->isr_handler = NULL;
569 }
570
571 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
572 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
573 {
574 struct tegra_dma_sg_req *hsgreq = NULL;
575
576 if (list_empty(&tdc->pending_sg_req)) {
577 dev_err(tdc2dev(tdc), "Dma is running without req\n");
578 tegra_dma_stop(tdc);
579 return false;
580 }
581
582 /*
583 * Check that head req on list should be in flight.
584 * If it is not in flight then abort transfer as
585 * looping of transfer can not continue.
586 */
587 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
588 if (!hsgreq->configured) {
589 tegra_dma_stop(tdc);
590 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
591 tegra_dma_abort_all(tdc);
592 return false;
593 }
594
595 /* Configure next request */
596 if (!to_terminate)
597 tdc_configure_next_head_desc(tdc);
598 return true;
599 }
600
601 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
602 bool to_terminate)
603 {
604 struct tegra_dma_sg_req *sgreq;
605 struct tegra_dma_desc *dma_desc;
606
607 tdc->busy = false;
608 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
609 dma_desc = sgreq->dma_desc;
610 dma_desc->bytes_transferred += sgreq->req_len;
611
612 list_del(&sgreq->node);
613 if (sgreq->last_sg) {
614 dma_desc->dma_status = DMA_COMPLETE;
615 dma_cookie_complete(&dma_desc->txd);
616 if (!dma_desc->cb_count)
617 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
618 dma_desc->cb_count++;
619 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
620 }
621 list_add_tail(&sgreq->node, &tdc->free_sg_req);
622
623 /* Do not start DMA if it is going to be terminate */
624 if (to_terminate || list_empty(&tdc->pending_sg_req))
625 return;
626
627 tdc_start_head_req(tdc);
628 }
629
630 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
631 bool to_terminate)
632 {
633 struct tegra_dma_sg_req *sgreq;
634 struct tegra_dma_desc *dma_desc;
635 bool st;
636
637 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
638 dma_desc = sgreq->dma_desc;
639 /* if we dma for long enough the transfer count will wrap */
640 dma_desc->bytes_transferred =
641 (dma_desc->bytes_transferred + sgreq->req_len) %
642 dma_desc->bytes_requested;
643
644 /* Callback need to be call */
645 if (!dma_desc->cb_count)
646 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
647 dma_desc->cb_count++;
648
649 /* If not last req then put at end of pending list */
650 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
651 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
652 sgreq->configured = false;
653 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
654 if (!st)
655 dma_desc->dma_status = DMA_ERROR;
656 }
657 }
658
659 static void tegra_dma_tasklet(unsigned long data)
660 {
661 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
662 struct dmaengine_desc_callback cb;
663 struct tegra_dma_desc *dma_desc;
664 unsigned long flags;
665 int cb_count;
666
667 spin_lock_irqsave(&tdc->lock, flags);
668 while (!list_empty(&tdc->cb_desc)) {
669 dma_desc = list_first_entry(&tdc->cb_desc,
670 typeof(*dma_desc), cb_node);
671 list_del(&dma_desc->cb_node);
672 dmaengine_desc_get_callback(&dma_desc->txd, &cb);
673 cb_count = dma_desc->cb_count;
674 dma_desc->cb_count = 0;
675 spin_unlock_irqrestore(&tdc->lock, flags);
676 while (cb_count--)
677 dmaengine_desc_callback_invoke(&cb, NULL);
678 spin_lock_irqsave(&tdc->lock, flags);
679 }
680 spin_unlock_irqrestore(&tdc->lock, flags);
681 }
682
683 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
684 {
685 struct tegra_dma_channel *tdc = dev_id;
686 unsigned long status;
687 unsigned long flags;
688
689 spin_lock_irqsave(&tdc->lock, flags);
690
691 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
692 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
693 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
694 tdc->isr_handler(tdc, false);
695 tasklet_schedule(&tdc->tasklet);
696 spin_unlock_irqrestore(&tdc->lock, flags);
697 return IRQ_HANDLED;
698 }
699
700 spin_unlock_irqrestore(&tdc->lock, flags);
701 dev_info(tdc2dev(tdc),
702 "Interrupt already served status 0x%08lx\n", status);
703 return IRQ_NONE;
704 }
705
706 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
707 {
708 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
709 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
710 unsigned long flags;
711 dma_cookie_t cookie;
712
713 spin_lock_irqsave(&tdc->lock, flags);
714 dma_desc->dma_status = DMA_IN_PROGRESS;
715 cookie = dma_cookie_assign(&dma_desc->txd);
716 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
717 spin_unlock_irqrestore(&tdc->lock, flags);
718 return cookie;
719 }
720
721 static void tegra_dma_issue_pending(struct dma_chan *dc)
722 {
723 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
724 unsigned long flags;
725
726 spin_lock_irqsave(&tdc->lock, flags);
727 if (list_empty(&tdc->pending_sg_req)) {
728 dev_err(tdc2dev(tdc), "No DMA request\n");
729 goto end;
730 }
731 if (!tdc->busy) {
732 tdc_start_head_req(tdc);
733
734 /* Continuous single mode: Configure next req */
735 if (tdc->cyclic) {
736 /*
737 * Wait for 1 burst time for configure DMA for
738 * next transfer.
739 */
740 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
741 tdc_configure_next_head_desc(tdc);
742 }
743 }
744 end:
745 spin_unlock_irqrestore(&tdc->lock, flags);
746 }
747
748 static int tegra_dma_terminate_all(struct dma_chan *dc)
749 {
750 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
751 struct tegra_dma_sg_req *sgreq;
752 struct tegra_dma_desc *dma_desc;
753 unsigned long flags;
754 unsigned long status;
755 unsigned long wcount;
756 bool was_busy;
757
758 spin_lock_irqsave(&tdc->lock, flags);
759
760 if (!tdc->busy)
761 goto skip_dma_stop;
762
763 /* Pause DMA before checking the queue status */
764 tegra_dma_pause(tdc, true);
765
766 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
767 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
768 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
769 tdc->isr_handler(tdc, true);
770 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
771 }
772 if (tdc->tdma->chip_data->support_separate_wcount_reg)
773 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
774 else
775 wcount = status;
776
777 was_busy = tdc->busy;
778 tegra_dma_stop(tdc);
779
780 if (!list_empty(&tdc->pending_sg_req) && was_busy) {
781 sgreq = list_first_entry(&tdc->pending_sg_req,
782 typeof(*sgreq), node);
783 sgreq->dma_desc->bytes_transferred +=
784 get_current_xferred_count(tdc, sgreq, wcount);
785 }
786 tegra_dma_resume(tdc);
787
788 skip_dma_stop:
789 tegra_dma_abort_all(tdc);
790
791 while (!list_empty(&tdc->cb_desc)) {
792 dma_desc = list_first_entry(&tdc->cb_desc,
793 typeof(*dma_desc), cb_node);
794 list_del(&dma_desc->cb_node);
795 dma_desc->cb_count = 0;
796 }
797 spin_unlock_irqrestore(&tdc->lock, flags);
798 return 0;
799 }
800
801 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
802 dma_cookie_t cookie, struct dma_tx_state *txstate)
803 {
804 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
805 struct tegra_dma_desc *dma_desc;
806 struct tegra_dma_sg_req *sg_req;
807 enum dma_status ret;
808 unsigned long flags;
809 unsigned int residual;
810
811 ret = dma_cookie_status(dc, cookie, txstate);
812 if (ret == DMA_COMPLETE)
813 return ret;
814
815 spin_lock_irqsave(&tdc->lock, flags);
816
817 /* Check on wait_ack desc status */
818 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
819 if (dma_desc->txd.cookie == cookie) {
820 ret = dma_desc->dma_status;
821 goto found;
822 }
823 }
824
825 /* Check in pending list */
826 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
827 dma_desc = sg_req->dma_desc;
828 if (dma_desc->txd.cookie == cookie) {
829 ret = dma_desc->dma_status;
830 goto found;
831 }
832 }
833
834 dev_dbg(tdc2dev(tdc), "cookie %d not found\n", cookie);
835 dma_desc = NULL;
836
837 found:
838 if (dma_desc && txstate) {
839 residual = dma_desc->bytes_requested -
840 (dma_desc->bytes_transferred %
841 dma_desc->bytes_requested);
842 dma_set_residue(txstate, residual);
843 }
844
845 spin_unlock_irqrestore(&tdc->lock, flags);
846 return ret;
847 }
848
849 static inline int get_bus_width(struct tegra_dma_channel *tdc,
850 enum dma_slave_buswidth slave_bw)
851 {
852 switch (slave_bw) {
853 case DMA_SLAVE_BUSWIDTH_1_BYTE:
854 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
855 case DMA_SLAVE_BUSWIDTH_2_BYTES:
856 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
857 case DMA_SLAVE_BUSWIDTH_4_BYTES:
858 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
859 case DMA_SLAVE_BUSWIDTH_8_BYTES:
860 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
861 default:
862 dev_warn(tdc2dev(tdc),
863 "slave bw is not supported, using 32bits\n");
864 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
865 }
866 }
867
868 static inline int get_burst_size(struct tegra_dma_channel *tdc,
869 u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
870 {
871 int burst_byte;
872 int burst_ahb_width;
873
874 /*
875 * burst_size from client is in terms of the bus_width.
876 * convert them into AHB memory width which is 4 byte.
877 */
878 burst_byte = burst_size * slave_bw;
879 burst_ahb_width = burst_byte / 4;
880
881 /* If burst size is 0 then calculate the burst size based on length */
882 if (!burst_ahb_width) {
883 if (len & 0xF)
884 return TEGRA_APBDMA_AHBSEQ_BURST_1;
885 else if ((len >> 4) & 0x1)
886 return TEGRA_APBDMA_AHBSEQ_BURST_4;
887 else
888 return TEGRA_APBDMA_AHBSEQ_BURST_8;
889 }
890 if (burst_ahb_width < 4)
891 return TEGRA_APBDMA_AHBSEQ_BURST_1;
892 else if (burst_ahb_width < 8)
893 return TEGRA_APBDMA_AHBSEQ_BURST_4;
894 else
895 return TEGRA_APBDMA_AHBSEQ_BURST_8;
896 }
897
898 static int get_transfer_param(struct tegra_dma_channel *tdc,
899 enum dma_transfer_direction direction, unsigned long *apb_addr,
900 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
901 enum dma_slave_buswidth *slave_bw)
902 {
903 switch (direction) {
904 case DMA_MEM_TO_DEV:
905 *apb_addr = tdc->dma_sconfig.dst_addr;
906 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
907 *burst_size = tdc->dma_sconfig.dst_maxburst;
908 *slave_bw = tdc->dma_sconfig.dst_addr_width;
909 *csr = TEGRA_APBDMA_CSR_DIR;
910 return 0;
911
912 case DMA_DEV_TO_MEM:
913 *apb_addr = tdc->dma_sconfig.src_addr;
914 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
915 *burst_size = tdc->dma_sconfig.src_maxburst;
916 *slave_bw = tdc->dma_sconfig.src_addr_width;
917 *csr = 0;
918 return 0;
919
920 default:
921 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
922 return -EINVAL;
923 }
924 return -EINVAL;
925 }
926
927 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
928 struct tegra_dma_channel_regs *ch_regs, u32 len)
929 {
930 u32 len_field = (len - 4) & 0xFFFC;
931
932 if (tdc->tdma->chip_data->support_separate_wcount_reg)
933 ch_regs->wcount = len_field;
934 else
935 ch_regs->csr |= len_field;
936 }
937
938 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
939 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
940 enum dma_transfer_direction direction, unsigned long flags,
941 void *context)
942 {
943 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
944 struct tegra_dma_desc *dma_desc;
945 unsigned int i;
946 struct scatterlist *sg;
947 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
948 struct list_head req_list;
949 struct tegra_dma_sg_req *sg_req = NULL;
950 u32 burst_size;
951 enum dma_slave_buswidth slave_bw;
952
953 if (!tdc->config_init) {
954 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
955 return NULL;
956 }
957 if (sg_len < 1) {
958 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
959 return NULL;
960 }
961
962 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
963 &burst_size, &slave_bw) < 0)
964 return NULL;
965
966 INIT_LIST_HEAD(&req_list);
967
968 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
969 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
970 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
971 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
972
973 csr |= TEGRA_APBDMA_CSR_ONCE;
974
975 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
976 csr |= TEGRA_APBDMA_CSR_FLOW;
977 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
978 }
979
980 if (flags & DMA_PREP_INTERRUPT) {
981 csr |= TEGRA_APBDMA_CSR_IE_EOC;
982 } else {
983 WARN_ON_ONCE(1);
984 return NULL;
985 }
986
987 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
988
989 dma_desc = tegra_dma_desc_get(tdc);
990 if (!dma_desc) {
991 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
992 return NULL;
993 }
994 INIT_LIST_HEAD(&dma_desc->tx_list);
995 INIT_LIST_HEAD(&dma_desc->cb_node);
996 dma_desc->cb_count = 0;
997 dma_desc->bytes_requested = 0;
998 dma_desc->bytes_transferred = 0;
999 dma_desc->dma_status = DMA_IN_PROGRESS;
1000
1001 /* Make transfer requests */
1002 for_each_sg(sgl, sg, sg_len, i) {
1003 u32 len, mem;
1004
1005 mem = sg_dma_address(sg);
1006 len = sg_dma_len(sg);
1007
1008 if ((len & 3) || (mem & 3) ||
1009 (len > tdc->tdma->chip_data->max_dma_count)) {
1010 dev_err(tdc2dev(tdc),
1011 "Dma length/memory address is not supported\n");
1012 tegra_dma_desc_put(tdc, dma_desc);
1013 return NULL;
1014 }
1015
1016 sg_req = tegra_dma_sg_req_get(tdc);
1017 if (!sg_req) {
1018 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1019 tegra_dma_desc_put(tdc, dma_desc);
1020 return NULL;
1021 }
1022
1023 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1024 dma_desc->bytes_requested += len;
1025
1026 sg_req->ch_regs.apb_ptr = apb_ptr;
1027 sg_req->ch_regs.ahb_ptr = mem;
1028 sg_req->ch_regs.csr = csr;
1029 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1030 sg_req->ch_regs.apb_seq = apb_seq;
1031 sg_req->ch_regs.ahb_seq = ahb_seq;
1032 sg_req->configured = false;
1033 sg_req->last_sg = false;
1034 sg_req->dma_desc = dma_desc;
1035 sg_req->req_len = len;
1036
1037 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1038 }
1039 sg_req->last_sg = true;
1040 if (flags & DMA_CTRL_ACK)
1041 dma_desc->txd.flags = DMA_CTRL_ACK;
1042
1043 /*
1044 * Make sure that mode should not be conflicting with currently
1045 * configured mode.
1046 */
1047 if (!tdc->isr_handler) {
1048 tdc->isr_handler = handle_once_dma_done;
1049 tdc->cyclic = false;
1050 } else {
1051 if (tdc->cyclic) {
1052 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1053 tegra_dma_desc_put(tdc, dma_desc);
1054 return NULL;
1055 }
1056 }
1057
1058 return &dma_desc->txd;
1059 }
1060
1061 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1062 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1063 size_t period_len, enum dma_transfer_direction direction,
1064 unsigned long flags)
1065 {
1066 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1067 struct tegra_dma_desc *dma_desc = NULL;
1068 struct tegra_dma_sg_req *sg_req = NULL;
1069 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1070 int len;
1071 size_t remain_len;
1072 dma_addr_t mem = buf_addr;
1073 u32 burst_size;
1074 enum dma_slave_buswidth slave_bw;
1075
1076 if (!buf_len || !period_len) {
1077 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1078 return NULL;
1079 }
1080
1081 if (!tdc->config_init) {
1082 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1083 return NULL;
1084 }
1085
1086 /*
1087 * We allow to take more number of requests till DMA is
1088 * not started. The driver will loop over all requests.
1089 * Once DMA is started then new requests can be queued only after
1090 * terminating the DMA.
1091 */
1092 if (tdc->busy) {
1093 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1094 return NULL;
1095 }
1096
1097 /*
1098 * We only support cycle transfer when buf_len is multiple of
1099 * period_len.
1100 */
1101 if (buf_len % period_len) {
1102 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1103 return NULL;
1104 }
1105
1106 len = period_len;
1107 if ((len & 3) || (buf_addr & 3) ||
1108 (len > tdc->tdma->chip_data->max_dma_count)) {
1109 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1110 return NULL;
1111 }
1112
1113 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1114 &burst_size, &slave_bw) < 0)
1115 return NULL;
1116
1117 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1118 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1119 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1120 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1121
1122 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
1123 csr |= TEGRA_APBDMA_CSR_FLOW;
1124 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1125 }
1126
1127 if (flags & DMA_PREP_INTERRUPT) {
1128 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1129 } else {
1130 WARN_ON_ONCE(1);
1131 return NULL;
1132 }
1133
1134 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1135
1136 dma_desc = tegra_dma_desc_get(tdc);
1137 if (!dma_desc) {
1138 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1139 return NULL;
1140 }
1141
1142 INIT_LIST_HEAD(&dma_desc->tx_list);
1143 INIT_LIST_HEAD(&dma_desc->cb_node);
1144 dma_desc->cb_count = 0;
1145
1146 dma_desc->bytes_transferred = 0;
1147 dma_desc->bytes_requested = buf_len;
1148 remain_len = buf_len;
1149
1150 /* Split transfer equal to period size */
1151 while (remain_len) {
1152 sg_req = tegra_dma_sg_req_get(tdc);
1153 if (!sg_req) {
1154 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1155 tegra_dma_desc_put(tdc, dma_desc);
1156 return NULL;
1157 }
1158
1159 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1160 sg_req->ch_regs.apb_ptr = apb_ptr;
1161 sg_req->ch_regs.ahb_ptr = mem;
1162 sg_req->ch_regs.csr = csr;
1163 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1164 sg_req->ch_regs.apb_seq = apb_seq;
1165 sg_req->ch_regs.ahb_seq = ahb_seq;
1166 sg_req->configured = false;
1167 sg_req->last_sg = false;
1168 sg_req->dma_desc = dma_desc;
1169 sg_req->req_len = len;
1170
1171 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1172 remain_len -= len;
1173 mem += len;
1174 }
1175 sg_req->last_sg = true;
1176 if (flags & DMA_CTRL_ACK)
1177 dma_desc->txd.flags = DMA_CTRL_ACK;
1178
1179 /*
1180 * Make sure that mode should not be conflicting with currently
1181 * configured mode.
1182 */
1183 if (!tdc->isr_handler) {
1184 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1185 tdc->cyclic = true;
1186 } else {
1187 if (!tdc->cyclic) {
1188 dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1189 tegra_dma_desc_put(tdc, dma_desc);
1190 return NULL;
1191 }
1192 }
1193
1194 return &dma_desc->txd;
1195 }
1196
1197 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1198 {
1199 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1200 struct tegra_dma *tdma = tdc->tdma;
1201 int ret;
1202
1203 dma_cookie_init(&tdc->dma_chan);
1204 tdc->config_init = false;
1205
1206 ret = pm_runtime_get_sync(tdma->dev);
1207 if (ret < 0)
1208 return ret;
1209
1210 return 0;
1211 }
1212
1213 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1214 {
1215 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1216 struct tegra_dma *tdma = tdc->tdma;
1217 struct tegra_dma_desc *dma_desc;
1218 struct tegra_dma_sg_req *sg_req;
1219 struct list_head dma_desc_list;
1220 struct list_head sg_req_list;
1221 unsigned long flags;
1222
1223 INIT_LIST_HEAD(&dma_desc_list);
1224 INIT_LIST_HEAD(&sg_req_list);
1225
1226 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1227
1228 if (tdc->busy)
1229 tegra_dma_terminate_all(dc);
1230
1231 spin_lock_irqsave(&tdc->lock, flags);
1232 list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1233 list_splice_init(&tdc->free_sg_req, &sg_req_list);
1234 list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1235 INIT_LIST_HEAD(&tdc->cb_desc);
1236 tdc->config_init = false;
1237 tdc->isr_handler = NULL;
1238 spin_unlock_irqrestore(&tdc->lock, flags);
1239
1240 while (!list_empty(&dma_desc_list)) {
1241 dma_desc = list_first_entry(&dma_desc_list,
1242 typeof(*dma_desc), node);
1243 list_del(&dma_desc->node);
1244 kfree(dma_desc);
1245 }
1246
1247 while (!list_empty(&sg_req_list)) {
1248 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1249 list_del(&sg_req->node);
1250 kfree(sg_req);
1251 }
1252 pm_runtime_put(tdma->dev);
1253
1254 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1255 }
1256
1257 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1258 struct of_dma *ofdma)
1259 {
1260 struct tegra_dma *tdma = ofdma->of_dma_data;
1261 struct dma_chan *chan;
1262 struct tegra_dma_channel *tdc;
1263
1264 if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) {
1265 dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);
1266 return NULL;
1267 }
1268
1269 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1270 if (!chan)
1271 return NULL;
1272
1273 tdc = to_tegra_dma_chan(chan);
1274 tdc->slave_id = dma_spec->args[0];
1275
1276 return chan;
1277 }
1278
1279 /* Tegra20 specific DMA controller information */
1280 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1281 .nr_channels = 16,
1282 .channel_reg_size = 0x20,
1283 .max_dma_count = 1024UL * 64,
1284 .support_channel_pause = false,
1285 .support_separate_wcount_reg = false,
1286 };
1287
1288 /* Tegra30 specific DMA controller information */
1289 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1290 .nr_channels = 32,
1291 .channel_reg_size = 0x20,
1292 .max_dma_count = 1024UL * 64,
1293 .support_channel_pause = false,
1294 .support_separate_wcount_reg = false,
1295 };
1296
1297 /* Tegra114 specific DMA controller information */
1298 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1299 .nr_channels = 32,
1300 .channel_reg_size = 0x20,
1301 .max_dma_count = 1024UL * 64,
1302 .support_channel_pause = true,
1303 .support_separate_wcount_reg = false,
1304 };
1305
1306 /* Tegra148 specific DMA controller information */
1307 static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
1308 .nr_channels = 32,
1309 .channel_reg_size = 0x40,
1310 .max_dma_count = 1024UL * 64,
1311 .support_channel_pause = true,
1312 .support_separate_wcount_reg = true,
1313 };
1314
1315 static int tegra_dma_probe(struct platform_device *pdev)
1316 {
1317 struct resource *res;
1318 struct tegra_dma *tdma;
1319 int ret;
1320 int i;
1321 const struct tegra_dma_chip_data *cdata;
1322
1323 cdata = of_device_get_match_data(&pdev->dev);
1324 if (!cdata) {
1325 dev_err(&pdev->dev, "Error: No device match data found\n");
1326 return -ENODEV;
1327 }
1328
1329 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1330 sizeof(struct tegra_dma_channel), GFP_KERNEL);
1331 if (!tdma)
1332 return -ENOMEM;
1333
1334 tdma->dev = &pdev->dev;
1335 tdma->chip_data = cdata;
1336 platform_set_drvdata(pdev, tdma);
1337
1338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1339 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1340 if (IS_ERR(tdma->base_addr))
1341 return PTR_ERR(tdma->base_addr);
1342
1343 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1344 if (IS_ERR(tdma->dma_clk)) {
1345 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1346 return PTR_ERR(tdma->dma_clk);
1347 }
1348
1349 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1350 if (IS_ERR(tdma->rst)) {
1351 dev_err(&pdev->dev, "Error: Missing reset\n");
1352 return PTR_ERR(tdma->rst);
1353 }
1354
1355 spin_lock_init(&tdma->global_lock);
1356
1357 pm_runtime_enable(&pdev->dev);
1358 if (!pm_runtime_enabled(&pdev->dev))
1359 ret = tegra_dma_runtime_resume(&pdev->dev);
1360 else
1361 ret = pm_runtime_get_sync(&pdev->dev);
1362
1363 if (ret < 0) {
1364 pm_runtime_disable(&pdev->dev);
1365 return ret;
1366 }
1367
1368 /* Reset DMA controller */
1369 reset_control_assert(tdma->rst);
1370 udelay(2);
1371 reset_control_deassert(tdma->rst);
1372
1373 /* Enable global DMA registers */
1374 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1375 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1376 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1377
1378 pm_runtime_put(&pdev->dev);
1379
1380 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1381 for (i = 0; i < cdata->nr_channels; i++) {
1382 struct tegra_dma_channel *tdc = &tdma->channels[i];
1383
1384 tdc->chan_addr = tdma->base_addr +
1385 TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1386 (i * cdata->channel_reg_size);
1387
1388 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1389 if (!res) {
1390 ret = -EINVAL;
1391 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1392 goto err_irq;
1393 }
1394 tdc->irq = res->start;
1395 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1396 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc);
1397 if (ret) {
1398 dev_err(&pdev->dev,
1399 "request_irq failed with err %d channel %d\n",
1400 ret, i);
1401 goto err_irq;
1402 }
1403
1404 tdc->dma_chan.device = &tdma->dma_dev;
1405 dma_cookie_init(&tdc->dma_chan);
1406 list_add_tail(&tdc->dma_chan.device_node,
1407 &tdma->dma_dev.channels);
1408 tdc->tdma = tdma;
1409 tdc->id = i;
1410 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1411
1412 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1413 (unsigned long)tdc);
1414 spin_lock_init(&tdc->lock);
1415
1416 INIT_LIST_HEAD(&tdc->pending_sg_req);
1417 INIT_LIST_HEAD(&tdc->free_sg_req);
1418 INIT_LIST_HEAD(&tdc->free_dma_desc);
1419 INIT_LIST_HEAD(&tdc->cb_desc);
1420 }
1421
1422 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1423 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1424 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1425
1426 tdma->global_pause_count = 0;
1427 tdma->dma_dev.dev = &pdev->dev;
1428 tdma->dma_dev.device_alloc_chan_resources =
1429 tegra_dma_alloc_chan_resources;
1430 tdma->dma_dev.device_free_chan_resources =
1431 tegra_dma_free_chan_resources;
1432 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1433 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1434 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1435 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1436 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1437 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1438 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1439 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1440 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1441 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1442 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1443 /*
1444 * XXX The hardware appears to support
1445 * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1446 * only used by this driver during tegra_dma_terminate_all()
1447 */
1448 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1449 tdma->dma_dev.device_config = tegra_dma_slave_config;
1450 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1451 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1452 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1453
1454 ret = dma_async_device_register(&tdma->dma_dev);
1455 if (ret < 0) {
1456 dev_err(&pdev->dev,
1457 "Tegra20 APB DMA driver registration failed %d\n", ret);
1458 goto err_irq;
1459 }
1460
1461 ret = of_dma_controller_register(pdev->dev.of_node,
1462 tegra_dma_of_xlate, tdma);
1463 if (ret < 0) {
1464 dev_err(&pdev->dev,
1465 "Tegra20 APB DMA OF registration failed %d\n", ret);
1466 goto err_unregister_dma_dev;
1467 }
1468
1469 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1470 cdata->nr_channels);
1471 return 0;
1472
1473 err_unregister_dma_dev:
1474 dma_async_device_unregister(&tdma->dma_dev);
1475 err_irq:
1476 while (--i >= 0) {
1477 struct tegra_dma_channel *tdc = &tdma->channels[i];
1478
1479 free_irq(tdc->irq, tdc);
1480 tasklet_kill(&tdc->tasklet);
1481 }
1482
1483 pm_runtime_disable(&pdev->dev);
1484 if (!pm_runtime_status_suspended(&pdev->dev))
1485 tegra_dma_runtime_suspend(&pdev->dev);
1486 return ret;
1487 }
1488
1489 static int tegra_dma_remove(struct platform_device *pdev)
1490 {
1491 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1492 int i;
1493 struct tegra_dma_channel *tdc;
1494
1495 dma_async_device_unregister(&tdma->dma_dev);
1496
1497 for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1498 tdc = &tdma->channels[i];
1499 free_irq(tdc->irq, tdc);
1500 tasklet_kill(&tdc->tasklet);
1501 }
1502
1503 pm_runtime_disable(&pdev->dev);
1504 if (!pm_runtime_status_suspended(&pdev->dev))
1505 tegra_dma_runtime_suspend(&pdev->dev);
1506
1507 return 0;
1508 }
1509
1510 static int tegra_dma_runtime_suspend(struct device *dev)
1511 {
1512 struct tegra_dma *tdma = dev_get_drvdata(dev);
1513 int i;
1514
1515 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1516 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1517 struct tegra_dma_channel *tdc = &tdma->channels[i];
1518 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1519
1520 /* Only save the state of DMA channels that are in use */
1521 if (!tdc->config_init)
1522 continue;
1523
1524 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1525 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1526 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1527 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1528 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1529 if (tdma->chip_data->support_separate_wcount_reg)
1530 ch_reg->wcount = tdc_read(tdc,
1531 TEGRA_APBDMA_CHAN_WCOUNT);
1532 }
1533
1534 clk_disable_unprepare(tdma->dma_clk);
1535
1536 return 0;
1537 }
1538
1539 static int tegra_dma_runtime_resume(struct device *dev)
1540 {
1541 struct tegra_dma *tdma = dev_get_drvdata(dev);
1542 int i, ret;
1543
1544 ret = clk_prepare_enable(tdma->dma_clk);
1545 if (ret < 0) {
1546 dev_err(dev, "clk_enable failed: %d\n", ret);
1547 return ret;
1548 }
1549
1550 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1551 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1552 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1553
1554 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1555 struct tegra_dma_channel *tdc = &tdma->channels[i];
1556 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1557
1558 /* Only restore the state of DMA channels that are in use */
1559 if (!tdc->config_init)
1560 continue;
1561
1562 if (tdma->chip_data->support_separate_wcount_reg)
1563 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
1564 ch_reg->wcount);
1565 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1566 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1567 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1568 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1569 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1570 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1571 }
1572
1573 return 0;
1574 }
1575
1576 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1577 SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
1578 NULL)
1579 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1580 pm_runtime_force_resume)
1581 };
1582
1583 static const struct of_device_id tegra_dma_of_match[] = {
1584 {
1585 .compatible = "nvidia,tegra148-apbdma",
1586 .data = &tegra148_dma_chip_data,
1587 }, {
1588 .compatible = "nvidia,tegra114-apbdma",
1589 .data = &tegra114_dma_chip_data,
1590 }, {
1591 .compatible = "nvidia,tegra30-apbdma",
1592 .data = &tegra30_dma_chip_data,
1593 }, {
1594 .compatible = "nvidia,tegra20-apbdma",
1595 .data = &tegra20_dma_chip_data,
1596 }, {
1597 },
1598 };
1599 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1600
1601 static struct platform_driver tegra_dmac_driver = {
1602 .driver = {
1603 .name = "tegra-apbdma",
1604 .pm = &tegra_dma_dev_pm_ops,
1605 .of_match_table = tegra_dma_of_match,
1606 },
1607 .probe = tegra_dma_probe,
1608 .remove = tegra_dma_remove,
1609 };
1610
1611 module_platform_driver(tegra_dmac_driver);
1612
1613 MODULE_ALIAS("platform:tegra20-apbdma");
1614 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1615 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1616 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support