drivers/fpga/dfl.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Driver Header File for FPGA Device Feature List (DFL) Support
   4  *
   5  * Copyright (C) 2017-2018 Intel Corporation, Inc.
   6  *
   7  * Authors:
   8  *   Kang Luwei <luwei.kang@intel.com>
   9  *   Zhang Yi <yi.z.zhang@intel.com>
  10  *   Wu Hao <hao.wu@intel.com>
  11  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
  12  */
  13
  14 #ifndef __FPGA_DFL_H
  15 #define __FPGA_DFL_H
  16
  17 #include <linux/bitfield.h>
  18 #include <linux/cdev.h>
  19 #include <linux/delay.h>
  20 #include <linux/fs.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/io-64-nonatomic-lo-hi.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25 #include <linux/uuid.h>
  26 #include <linux/fpga/fpga-region.h>
  27
  28 /* maximum supported number of ports */
  29 #define MAX_DFL_FPGA_PORT_NUM 4
  30 /* plus one for fme device */
  31 #define MAX_DFL_FEATURE_DEV_NUM    (MAX_DFL_FPGA_PORT_NUM + 1)
  32
  33 /* Reserved 0x0 for Header Group Register and 0xff for AFU */
  34 #define FEATURE_ID_FIU_HEADER           0x0
  35 #define FEATURE_ID_AFU                  0xff
  36
  37 #define FME_FEATURE_ID_HEADER           FEATURE_ID_FIU_HEADER
  38 #define FME_FEATURE_ID_THERMAL_MGMT     0x1
  39 #define FME_FEATURE_ID_POWER_MGMT       0x2
  40 #define FME_FEATURE_ID_GLOBAL_IPERF     0x3
  41 #define FME_FEATURE_ID_GLOBAL_ERR       0x4
  42 #define FME_FEATURE_ID_PR_MGMT          0x5
  43 #define FME_FEATURE_ID_HSSI             0x6
  44 #define FME_FEATURE_ID_GLOBAL_DPERF     0x7
  45
  46 #define PORT_FEATURE_ID_HEADER          FEATURE_ID_FIU_HEADER
  47 #define PORT_FEATURE_ID_AFU             FEATURE_ID_AFU
  48 #define PORT_FEATURE_ID_ERROR           0x10
  49 #define PORT_FEATURE_ID_UMSG            0x11
  50 #define PORT_FEATURE_ID_UINT            0x12
  51 #define PORT_FEATURE_ID_STP             0x13
  52
  53 /*
  54  * Device Feature Header Register Set
  55  *
  56  * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
  57  * For AFUs, they have DFH + GUID as common header registers.
  58  * For private features, they only have DFH register as common header.
  59  */
  60 #define DFH                     0x0
  61 #define GUID_L                  0x8
  62 #define GUID_H                  0x10
  63 #define NEXT_AFU                0x18
  64
  65 #define DFH_SIZE                0x8
  66
  67 /* Device Feature Header Register Bitfield */
  68 #define DFH_ID                  GENMASK_ULL(11, 0)      /* Feature ID */
  69 #define DFH_ID_FIU_FME          0
  70 #define DFH_ID_FIU_PORT         1
  71 #define DFH_REVISION            GENMASK_ULL(15, 12)     /* Feature revision */
  72 #define DFH_NEXT_HDR_OFST       GENMASK_ULL(39, 16)     /* Offset to next DFH */
  73 #define DFH_EOL                 BIT_ULL(40)             /* End of list */
  74 #define DFH_TYPE                GENMASK_ULL(63, 60)     /* Feature type */
  75 #define DFH_TYPE_AFU            1
  76 #define DFH_TYPE_PRIVATE        3
  77 #define DFH_TYPE_FIU            4
  78
  79 /* Next AFU Register Bitfield */
  80 #define NEXT_AFU_NEXT_DFH_OFST  GENMASK_ULL(23, 0)      /* Offset to next AFU */
  81
  82 /* FME Header Register Set */
  83 #define FME_HDR_DFH             DFH
  84 #define FME_HDR_GUID_L          GUID_L
  85 #define FME_HDR_GUID_H          GUID_H
  86 #define FME_HDR_NEXT_AFU        NEXT_AFU
  87 #define FME_HDR_CAP             0x30
  88 #define FME_HDR_PORT_OFST(n)    (0x38 + ((n) * 0x8))
  89 #define FME_HDR_BITSTREAM_ID    0x60
  90 #define FME_HDR_BITSTREAM_MD    0x68
  91
  92 /* FME Fab Capability Register Bitfield */
  93 #define FME_CAP_FABRIC_VERID    GENMASK_ULL(7, 0)       /* Fabric version ID */
  94 #define FME_CAP_SOCKET_ID       BIT_ULL(8)              /* Socket ID */
  95 #define FME_CAP_PCIE0_LINK_AVL  BIT_ULL(12)             /* PCIE0 Link */
  96 #define FME_CAP_PCIE1_LINK_AVL  BIT_ULL(13)             /* PCIE1 Link */
  97 #define FME_CAP_COHR_LINK_AVL   BIT_ULL(14)             /* Coherent Link */
  98 #define FME_CAP_IOMMU_AVL       BIT_ULL(16)             /* IOMMU available */
  99 #define FME_CAP_NUM_PORTS       GENMASK_ULL(19, 17)     /* Number of ports */
 100 #define FME_CAP_ADDR_WIDTH      GENMASK_ULL(29, 24)     /* Address bus width */
 101 #define FME_CAP_CACHE_SIZE      GENMASK_ULL(43, 32)     /* cache size in KB */
 102 #define FME_CAP_CACHE_ASSOC     GENMASK_ULL(47, 44)     /* Associativity */
 103
 104 /* FME Port Offset Register Bitfield */
 105 /* Offset to port device feature header */
 106 #define FME_PORT_OFST_DFH_OFST  GENMASK_ULL(23, 0)
 107 /* PCI Bar ID for this port */
 108 #define FME_PORT_OFST_BAR_ID    GENMASK_ULL(34, 32)
 109 /* AFU MMIO access permission. 1 - VF, 0 - PF. */
 110 #define FME_PORT_OFST_ACC_CTRL  BIT_ULL(55)
 111 #define FME_PORT_OFST_ACC_PF    0
 112 #define FME_PORT_OFST_ACC_VF    1
 113 #define FME_PORT_OFST_IMP       BIT_ULL(60)
 114
 115 /* PORT Header Register Set */
 116 #define PORT_HDR_DFH            DFH
 117 #define PORT_HDR_GUID_L         GUID_L
 118 #define PORT_HDR_GUID_H         GUID_H
 119 #define PORT_HDR_NEXT_AFU       NEXT_AFU
 120 #define PORT_HDR_CAP            0x30
 121 #define PORT_HDR_CTRL           0x38
 122
 123 /* Port Capability Register Bitfield */
 124 #define PORT_CAP_PORT_NUM       GENMASK_ULL(1, 0)       /* ID of this port */
 125 #define PORT_CAP_MMIO_SIZE      GENMASK_ULL(23, 8)      /* MMIO size in KB */
 126 #define PORT_CAP_SUPP_INT_NUM   GENMASK_ULL(35, 32)     /* Interrupts num */
 127
 128 /* Port Control Register Bitfield */
 129 #define PORT_CTRL_SFTRST        BIT_ULL(0)              /* Port soft reset */
 130 /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
 131 #define PORT_CTRL_LATENCY       BIT_ULL(2)
 132 #define PORT_CTRL_SFTRST_ACK    BIT_ULL(4)              /* HW ack for reset */
 133 /**
 134  * struct dfl_fpga_port_ops - port ops
 135  *
 136  * @name: name of this port ops, to match with port platform device.
 137  * @owner: pointer to the module which owns this port ops.
 138  * @node: node to link port ops to global list.
 139  * @get_id: get port id from hardware.
 140  * @enable_set: enable/disable the port.
 141  */
 142 struct dfl_fpga_port_ops {
 143         const char *name;
 144         struct module *owner;
 145         struct list_head node;
 146         int (*get_id)(struct platform_device *pdev);
 147         int (*enable_set)(struct platform_device *pdev, bool enable);
 148 };
 149
 150 void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
 151 void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
 152 struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
 153 void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
 154 int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
 155
 156 /**
 157  * struct dfl_feature_driver - sub feature's driver
 158  *
 159  * @id: sub feature id.
 160  * @ops: ops of this sub feature.
 161  */
 162 struct dfl_feature_driver {
 163         u64 id;
 164         const struct dfl_feature_ops *ops;
 165 };
 166
 167 /**
 168  * struct dfl_feature - sub feature of the feature devices
 169  *
 170  * @id: sub feature id.
 171  * @resource_index: each sub feature has one mmio resource for its registers.
 172  *                  this index is used to find its mmio resource from the
 173  *                  feature dev (platform device)'s reources.
 174  * @ioaddr: mapped mmio resource address.
 175  * @ops: ops of this sub feature.
 176  */
 177 struct dfl_feature {
 178         u64 id;
 179         int resource_index;
 180         void __iomem *ioaddr;
 181         const struct dfl_feature_ops *ops;
 182 };
 183
 184 #define DEV_STATUS_IN_USE       0
 185
 186 /**
 187  * struct dfl_feature_platform_data - platform data for feature devices
 188  *
 189  * @node: node to link feature devs to container device's port_dev_list.
 190  * @lock: mutex to protect platform data.
 191  * @cdev: cdev of feature dev.
 192  * @dev: ptr to platform device linked with this platform data.
 193  * @dfl_cdev: ptr to container device.
 194  * @disable_count: count for port disable.
 195  * @num: number for sub features.
 196  * @dev_status: dev status (e.g. DEV_STATUS_IN_USE).
 197  * @private: ptr to feature dev private data.
 198  * @features: sub features of this feature dev.
 199  */
 200 struct dfl_feature_platform_data {
 201         struct list_head node;
 202         struct mutex lock;
 203         struct cdev cdev;
 204         struct platform_device *dev;
 205         struct dfl_fpga_cdev *dfl_cdev;
 206         unsigned int disable_count;
 207         unsigned long dev_status;
 208         void *private;
 209         int num;
 210         struct dfl_feature features[0];
 211 };
 212
 213 static inline
 214 int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata)
 215 {
 216         /* Test and set IN_USE flags to ensure file is exclusively used */
 217         if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status))
 218                 return -EBUSY;
 219
 220         return 0;
 221 }
 222
 223 static inline
 224 void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
 225 {
 226         clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status);
 227 }
 228
 229 static inline
 230 void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
 231                                 void *private)
 232 {
 233         pdata->private = private;
 234 }
 235
 236 static inline
 237 void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
 238 {
 239         return pdata->private;
 240 }
 241
 242 struct dfl_feature_ops {
 243         int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
 244         void (*uinit)(struct platform_device *pdev,
 245                       struct dfl_feature *feature);
 246         long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
 247                       unsigned int cmd, unsigned long arg);
 248 };
 249
 250 #define DFL_FPGA_FEATURE_DEV_FME                "dfl-fme"
 251 #define DFL_FPGA_FEATURE_DEV_PORT               "dfl-port"
 252
 253 static inline int dfl_feature_platform_data_size(const int num)
 254 {
 255         return sizeof(struct dfl_feature_platform_data) +
 256                 num * sizeof(struct dfl_feature);
 257 }
 258
 259 void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
 260 int dfl_fpga_dev_feature_init(struct platform_device *pdev,
 261                               struct dfl_feature_driver *feature_drvs);
 262
 263 int dfl_fpga_dev_ops_register(struct platform_device *pdev,
 264                               const struct file_operations *fops,
 265                               struct module *owner);
 266 void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
 267
 268 static inline
 269 struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
 270 {
 271         struct dfl_feature_platform_data *pdata;
 272
 273         pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
 274                              cdev);
 275         return pdata->dev;
 276 }
 277
 278 #define dfl_fpga_dev_for_each_feature(pdata, feature)                       \
 279         for ((feature) = (pdata)->features;                                 \
 280            (feature) < (pdata)->features + (pdata)->num; (feature)++)
 281
 282 static inline
 283 struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id)
 284 {
 285         struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
 286         struct dfl_feature *feature;
 287
 288         dfl_fpga_dev_for_each_feature(pdata, feature)
 289                 if (feature->id == id)
 290                         return feature;
 291
 292         return NULL;
 293 }
 294
 295 static inline
 296 void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id)
 297 {
 298         struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
 299
 300         if (feature && feature->ioaddr)
 301                 return feature->ioaddr;
 302
 303         WARN_ON(1);
 304         return NULL;
 305 }
 306
 307 static inline bool is_dfl_feature_present(struct device *dev, u64 id)
 308 {
 309         return !!dfl_get_feature_ioaddr_by_id(dev, id);
 310 }
 311
 312 static inline
 313 struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
 314 {
 315         return pdata->dev->dev.parent->parent;
 316 }
 317
 318 static inline bool dfl_feature_is_fme(void __iomem *base)
 319 {
 320         u64 v = readq(base + DFH);
 321
 322         return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
 323                 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
 324 }
 325
 326 static inline bool dfl_feature_is_port(void __iomem *base)
 327 {
 328         u64 v = readq(base + DFH);
 329
 330         return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
 331                 (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
 332 }
 333
 334 /**
 335  * struct dfl_fpga_enum_info - DFL FPGA enumeration information
 336  *
 337  * @dev: parent device.
 338  * @dfls: list of device feature lists.
 339  */
 340 struct dfl_fpga_enum_info {
 341         struct device *dev;
 342         struct list_head dfls;
 343 };
 344
 345 /**
 346  * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
 347  *
 348  * @start: base address of this device feature list.
 349  * @len: size of this device feature list.
 350  * @ioaddr: mapped base address of this device feature list.
 351  * @node: node in list of device feature lists.
 352  */
 353 struct dfl_fpga_enum_dfl {
 354         resource_size_t start;
 355         resource_size_t len;
 356
 357         void __iomem *ioaddr;
 358
 359         struct list_head node;
 360 };
 361
 362 struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
 363 int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
 364                                resource_size_t start, resource_size_t len,
 365                                void __iomem *ioaddr);
 366 void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
 367
 368 /**
 369  * struct dfl_fpga_cdev - container device of DFL based FPGA
 370  *
 371  * @parent: parent device of this container device.
 372  * @region: base fpga region.
 373  * @fme_dev: FME feature device under this container device.
 374  * @lock: mutex lock to protect the port device list.
 375  * @port_dev_list: list of all port feature devices under this container device.
 376  */
 377 struct dfl_fpga_cdev {
 378         struct device *parent;
 379         struct fpga_region *region;
 380         struct device *fme_dev;
 381         struct mutex lock;
 382         struct list_head port_dev_list;
 383 };
 384
 385 struct dfl_fpga_cdev *
 386 dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
 387 void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
 388
 389 /*
 390  * need to drop the device reference with put_device() after use port platform
 391  * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
 392  * functions.
 393  */
 394 struct platform_device *
 395 __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
 396                           int (*match)(struct platform_device *, void *));
 397
 398 static inline struct platform_device *
 399 dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
 400                         int (*match)(struct platform_device *, void *))
 401 {
 402         struct platform_device *pdev;
 403
 404         mutex_lock(&cdev->lock);
 405         pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
 406         mutex_unlock(&cdev->lock);
 407
 408         return pdev;
 409 }
 410 #endif /* __FPGA_DFL_H */