?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / gpio / gpio-brcmstb.c
blobaf936dcca6596f2e60fb66f5615ff80210e1905d
1 /*
2 * Copyright (C) 2015-2017 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/bitops.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/module.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/interrupt.h>
22
23 enum gio_reg_index {
24 GIO_REG_ODEN = 0,
25 GIO_REG_DATA,
26 GIO_REG_IODIR,
27 GIO_REG_EC,
28 GIO_REG_EI,
29 GIO_REG_MASK,
30 GIO_REG_LEVEL,
31 GIO_REG_STAT,
32 NUMBER_OF_GIO_REGISTERS
33 };
34
35 #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
45
46 struct brcmstb_gpio_bank {
47 struct list_head node;
48 int id;
49 struct gpio_chip gc;
50 struct brcmstb_gpio_priv *parent_priv;
51 u32 width;
52 u32 wake_active;
53 u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
54 };
55
56 struct brcmstb_gpio_priv {
57 struct list_head bank_list;
58 void __iomem *reg_base;
59 struct platform_device *pdev;
60 struct irq_domain *irq_domain;
61 struct irq_chip irq_chip;
62 int parent_irq;
63 int gpio_base;
64 int num_gpios;
65 int parent_wake_irq;
66 };
67
68 #define MAX_GPIO_PER_BANK 32
69 #define GPIO_BANK(gpio) ((gpio) >> 5)
70 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
71 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
72
73 static inline struct brcmstb_gpio_priv *
74 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
75 {
76 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
77 return bank->parent_priv;
78 }
79
80 static unsigned long
81 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
82 {
83 void __iomem *reg_base = bank->parent_priv->reg_base;
84
85 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
86 bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
87 }
88
89 static unsigned long
90 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
91 {
92 unsigned long status;
93 unsigned long flags;
94
95 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
96 status = __brcmstb_gpio_get_active_irqs(bank);
97 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
98
99 return status;
100 }
101
102 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
103 struct brcmstb_gpio_bank *bank)
104 {
105 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
106 }
107
108 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
109 unsigned int hwirq, bool enable)
110 {
111 struct gpio_chip *gc = &bank->gc;
112 struct brcmstb_gpio_priv *priv = bank->parent_priv;
113 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
114 u32 imask;
115 unsigned long flags;
116
117 spin_lock_irqsave(&gc->bgpio_lock, flags);
118 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
119 if (enable)
120 imask |= mask;
121 else
122 imask &= ~mask;
123 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
124 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
125 }
126
127 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
128 {
129 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
130 /* gc_offset is relative to this gpio_chip; want real offset */
131 int hwirq = offset + (gc->base - priv->gpio_base);
132
133 if (hwirq >= priv->num_gpios)
134 return -ENXIO;
135 return irq_create_mapping(priv->irq_domain, hwirq);
136 }
137
138 /* -------------------- IRQ chip functions -------------------- */
139
140 static void brcmstb_gpio_irq_mask(struct irq_data *d)
141 {
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
144
145 brcmstb_gpio_set_imask(bank, d->hwirq, false);
146 }
147
148 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
149 {
150 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
151 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
152
153 brcmstb_gpio_set_imask(bank, d->hwirq, true);
154 }
155
156 static void brcmstb_gpio_irq_ack(struct irq_data *d)
157 {
158 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
162
163 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
164 }
165
166 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
167 {
168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
170 struct brcmstb_gpio_priv *priv = bank->parent_priv;
171 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
172 u32 edge_insensitive, iedge_insensitive;
173 u32 edge_config, iedge_config;
174 u32 level, ilevel;
175 unsigned long flags;
176
177 switch (type) {
178 case IRQ_TYPE_LEVEL_LOW:
179 level = mask;
180 edge_config = 0;
181 edge_insensitive = 0;
182 break;
183 case IRQ_TYPE_LEVEL_HIGH:
184 level = mask;
185 edge_config = mask;
186 edge_insensitive = 0;
187 break;
188 case IRQ_TYPE_EDGE_FALLING:
189 level = 0;
190 edge_config = 0;
191 edge_insensitive = 0;
192 break;
193 case IRQ_TYPE_EDGE_RISING:
194 level = 0;
195 edge_config = mask;
196 edge_insensitive = 0;
197 break;
198 case IRQ_TYPE_EDGE_BOTH:
199 level = 0;
200 edge_config = 0; /* don't care, but want known value */
201 edge_insensitive = mask;
202 break;
203 default:
204 return -EINVAL;
205 }
206
207 spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
208
209 iedge_config = bank->gc.read_reg(priv->reg_base +
210 GIO_EC(bank->id)) & ~mask;
211 iedge_insensitive = bank->gc.read_reg(priv->reg_base +
212 GIO_EI(bank->id)) & ~mask;
213 ilevel = bank->gc.read_reg(priv->reg_base +
214 GIO_LEVEL(bank->id)) & ~mask;
215
216 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
217 iedge_config | edge_config);
218 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
219 iedge_insensitive | edge_insensitive);
220 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
221 ilevel | level);
222
223 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
224 return 0;
225 }
226
227 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
228 unsigned int enable)
229 {
230 int ret = 0;
231
232 if (enable)
233 ret = enable_irq_wake(priv->parent_wake_irq);
234 else
235 ret = disable_irq_wake(priv->parent_wake_irq);
236 if (ret)
237 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
238 enable ? "enable" : "disable");
239 return ret;
240 }
241
242 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
243 {
244 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
245 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
246 struct brcmstb_gpio_priv *priv = bank->parent_priv;
247 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
248
249 /*
250 * Do not do anything specific for now, suspend/resume callbacks will
251 * configure the interrupt mask appropriately
252 */
253 if (enable)
254 bank->wake_active |= mask;
255 else
256 bank->wake_active &= ~mask;
257
258 return brcmstb_gpio_priv_set_wake(priv, enable);
259 }
260
261 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
262 {
263 struct brcmstb_gpio_priv *priv = data;
264
265 if (!priv || irq != priv->parent_wake_irq)
266 return IRQ_NONE;
267
268 /* Nothing to do */
269 return IRQ_HANDLED;
270 }
271
272 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
273 {
274 struct brcmstb_gpio_priv *priv = bank->parent_priv;
275 struct irq_domain *domain = priv->irq_domain;
276 int hwbase = bank->gc.base - priv->gpio_base;
277 unsigned long status;
278
279 while ((status = brcmstb_gpio_get_active_irqs(bank))) {
280 unsigned int irq, offset;
281
282 for_each_set_bit(offset, &status, 32) {
283 if (offset >= bank->width)
284 dev_warn(&priv->pdev->dev,
285 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
286 bank->id, offset);
287 irq = irq_linear_revmap(domain, hwbase + offset);
288 generic_handle_irq(irq);
289 }
290 }
291 }
292
293 /* Each UPG GIO block has one IRQ for all banks */
294 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
295 {
296 struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
297 struct irq_chip *chip = irq_desc_get_chip(desc);
298 struct brcmstb_gpio_bank *bank;
299
300 /* Interrupts weren't properly cleared during probe */
301 BUG_ON(!priv || !chip);
302
303 chained_irq_enter(chip, desc);
304 list_for_each_entry(bank, &priv->bank_list, node)
305 brcmstb_gpio_irq_bank_handler(bank);
306 chained_irq_exit(chip, desc);
307 }
308
309 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
310 struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
311 {
312 struct brcmstb_gpio_bank *bank;
313 int i = 0;
314
315 /* banks are in descending order */
316 list_for_each_entry_reverse(bank, &priv->bank_list, node) {
317 i += bank->gc.ngpio;
318 if (hwirq < i)
319 return bank;
320 }
321 return NULL;
322 }
323
324 /*
325 * This lock class tells lockdep that GPIO irqs are in a different
326 * category than their parents, so it won't report false recursion.
327 */
328 static struct lock_class_key brcmstb_gpio_irq_lock_class;
329 static struct lock_class_key brcmstb_gpio_irq_request_class;
330
331
332 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
333 irq_hw_number_t hwirq)
334 {
335 struct brcmstb_gpio_priv *priv = d->host_data;
336 struct brcmstb_gpio_bank *bank =
337 brcmstb_gpio_hwirq_to_bank(priv, hwirq);
338 struct platform_device *pdev = priv->pdev;
339 int ret;
340
341 if (!bank)
342 return -EINVAL;
343
344 dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
345 irq, (int)hwirq, bank->id);
346 ret = irq_set_chip_data(irq, &bank->gc);
347 if (ret < 0)
348 return ret;
349 irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
350 &brcmstb_gpio_irq_request_class);
351 irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
352 irq_set_noprobe(irq);
353 return 0;
354 }
355
356 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
357 {
358 irq_set_chip_and_handler(irq, NULL, NULL);
359 irq_set_chip_data(irq, NULL);
360 }
361
362 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
363 .map = brcmstb_gpio_irq_map,
364 .unmap = brcmstb_gpio_irq_unmap,
365 .xlate = irq_domain_xlate_twocell,
366 };
367
368 /* Make sure that the number of banks matches up between properties */
369 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
370 struct device_node *np, struct resource *res)
371 {
372 int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
373 int num_banks =
374 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
375
376 if (res_num_banks != num_banks) {
377 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
378 res_num_banks, num_banks);
379 return -EINVAL;
380 } else {
381 return 0;
382 }
383 }
384
385 static int brcmstb_gpio_remove(struct platform_device *pdev)
386 {
387 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
388 struct brcmstb_gpio_bank *bank;
389 int offset, ret = 0, virq;
390
391 if (!priv) {
392 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
393 return -EFAULT;
394 }
395
396 if (priv->parent_irq > 0)
397 irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
398
399 /* Remove all IRQ mappings and delete the domain */
400 if (priv->irq_domain) {
401 for (offset = 0; offset < priv->num_gpios; offset++) {
402 virq = irq_find_mapping(priv->irq_domain, offset);
403 irq_dispose_mapping(virq);
404 }
405 irq_domain_remove(priv->irq_domain);
406 }
407
408 /*
409 * You can lose return values below, but we report all errors, and it's
410 * more important to actually perform all of the steps.
411 */
412 list_for_each_entry(bank, &priv->bank_list, node)
413 gpiochip_remove(&bank->gc);
414
415 return ret;
416 }
417
418 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
419 const struct of_phandle_args *gpiospec, u32 *flags)
420 {
421 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
422 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
423 int offset;
424
425 if (gc->of_gpio_n_cells != 2) {
426 WARN_ON(1);
427 return -EINVAL;
428 }
429
430 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
431 return -EINVAL;
432
433 offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
434 if (offset >= gc->ngpio || offset < 0)
435 return -EINVAL;
436
437 if (unlikely(offset >= bank->width)) {
438 dev_warn_ratelimited(&priv->pdev->dev,
439 "Received request for invalid GPIO offset %d\n",
440 gpiospec->args[0]);
441 }
442
443 if (flags)
444 *flags = gpiospec->args[1];
445
446 return offset;
447 }
448
449 /* priv->parent_irq and priv->num_gpios must be set before calling */
450 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
451 struct brcmstb_gpio_priv *priv)
452 {
453 struct device *dev = &pdev->dev;
454 struct device_node *np = dev->of_node;
455 int err;
456
457 priv->irq_domain =
458 irq_domain_add_linear(np, priv->num_gpios,
459 &brcmstb_gpio_irq_domain_ops,
460 priv);
461 if (!priv->irq_domain) {
462 dev_err(dev, "Couldn't allocate IRQ domain\n");
463 return -ENXIO;
464 }
465
466 if (of_property_read_bool(np, "wakeup-source")) {
467 priv->parent_wake_irq = platform_get_irq(pdev, 1);
468 if (priv->parent_wake_irq < 0) {
469 priv->parent_wake_irq = 0;
470 dev_warn(dev,
471 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
472 } else {
473 /*
474 * Set wakeup capability so we can process boot-time
475 * "wakeups" (e.g., from S5 cold boot)
476 */
477 device_set_wakeup_capable(dev, true);
478 device_wakeup_enable(dev);
479 err = devm_request_irq(dev, priv->parent_wake_irq,
480 brcmstb_gpio_wake_irq_handler,
481 IRQF_SHARED,
482 "brcmstb-gpio-wake", priv);
483
484 if (err < 0) {
485 dev_err(dev, "Couldn't request wake IRQ");
486 goto out_free_domain;
487 }
488 }
489 }
490
491 priv->irq_chip.name = dev_name(dev);
492 priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
493 priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
494 priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
495 priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
496 priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
497
498 if (priv->parent_wake_irq)
499 priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
500
501 irq_set_chained_handler_and_data(priv->parent_irq,
502 brcmstb_gpio_irq_handler, priv);
503 irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
504
505 return 0;
506
507 out_free_domain:
508 irq_domain_remove(priv->irq_domain);
509
510 return err;
511 }
512
513 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
514 struct brcmstb_gpio_bank *bank)
515 {
516 struct gpio_chip *gc = &bank->gc;
517 unsigned int i;
518
519 for (i = 0; i < GIO_REG_STAT; i++)
520 bank->saved_regs[i] = gc->read_reg(priv->reg_base +
521 GIO_BANK_OFF(bank->id, i));
522 }
523
524 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
525 {
526 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
527 struct brcmstb_gpio_bank *bank;
528 struct gpio_chip *gc;
529 u32 imask;
530
531 /* disable non-wake interrupt */
532 if (priv->parent_irq >= 0)
533 disable_irq(priv->parent_irq);
534
535 list_for_each_entry(bank, &priv->bank_list, node) {
536 gc = &bank->gc;
537
538 if (save)
539 brcmstb_gpio_bank_save(priv, bank);
540
541 /* Unmask GPIOs which have been flagged as wake-up sources */
542 if (priv->parent_wake_irq)
543 imask = bank->wake_active;
544 else
545 imask = 0;
546 gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
547 imask);
548 }
549 }
550
551 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
552 {
553 /* Enable GPIO for S5 cold boot */
554 brcmstb_gpio_quiesce(&pdev->dev, false);
555 }
556
557 #ifdef CONFIG_PM_SLEEP
558 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
559 struct brcmstb_gpio_bank *bank)
560 {
561 struct gpio_chip *gc = &bank->gc;
562 unsigned int i;
563
564 for (i = 0; i < GIO_REG_STAT; i++)
565 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
566 bank->saved_regs[i]);
567 }
568
569 static int brcmstb_gpio_suspend(struct device *dev)
570 {
571 brcmstb_gpio_quiesce(dev, true);
572 return 0;
573 }
574
575 static int brcmstb_gpio_resume(struct device *dev)
576 {
577 struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
578 struct brcmstb_gpio_bank *bank;
579 bool need_wakeup_event = false;
580
581 list_for_each_entry(bank, &priv->bank_list, node) {
582 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
583 brcmstb_gpio_bank_restore(priv, bank);
584 }
585
586 if (priv->parent_wake_irq && need_wakeup_event)
587 pm_wakeup_event(dev, 0);
588
589 /* enable non-wake interrupt */
590 if (priv->parent_irq >= 0)
591 enable_irq(priv->parent_irq);
592
593 return 0;
594 }
595
596 #else
597 #define brcmstb_gpio_suspend NULL
598 #define brcmstb_gpio_resume NULL
599 #endif /* CONFIG_PM_SLEEP */
600
601 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
602 .suspend_noirq = brcmstb_gpio_suspend,
603 .resume_noirq = brcmstb_gpio_resume,
604 };
605
606 static int brcmstb_gpio_probe(struct platform_device *pdev)
607 {
608 struct device *dev = &pdev->dev;
609 struct device_node *np = dev->of_node;
610 void __iomem *reg_base;
611 struct brcmstb_gpio_priv *priv;
612 struct resource *res;
613 struct property *prop;
614 const __be32 *p;
615 u32 bank_width;
616 int num_banks = 0;
617 int err;
618 static int gpio_base;
619 unsigned long flags = 0;
620 bool need_wakeup_event = false;
621
622 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
623 if (!priv)
624 return -ENOMEM;
625 platform_set_drvdata(pdev, priv);
626 INIT_LIST_HEAD(&priv->bank_list);
627
628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
629 reg_base = devm_ioremap_resource(dev, res);
630 if (IS_ERR(reg_base))
631 return PTR_ERR(reg_base);
632
633 priv->gpio_base = gpio_base;
634 priv->reg_base = reg_base;
635 priv->pdev = pdev;
636
637 if (of_property_read_bool(np, "interrupt-controller")) {
638 priv->parent_irq = platform_get_irq(pdev, 0);
639 if (priv->parent_irq <= 0) {
640 dev_err(dev, "Couldn't get IRQ");
641 return -ENOENT;
642 }
643 } else {
644 priv->parent_irq = -ENOENT;
645 }
646
647 if (brcmstb_gpio_sanity_check_banks(dev, np, res))
648 return -EINVAL;
649
650 /*
651 * MIPS endianness is configured by boot strap, which also reverses all
652 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
653 * endian I/O).
654 *
655 * Other architectures (e.g., ARM) either do not support big endian, or
656 * else leave I/O in little endian mode.
657 */
658 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
659 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
660 #endif
661
662 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
663 bank_width) {
664 struct brcmstb_gpio_bank *bank;
665 struct gpio_chip *gc;
666
667 /*
668 * If bank_width is 0, then there is an empty bank in the
669 * register block. Special handling for this case.
670 */
671 if (bank_width == 0) {
672 dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
673 num_banks);
674 num_banks++;
675 gpio_base += MAX_GPIO_PER_BANK;
676 continue;
677 }
678
679 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
680 if (!bank) {
681 err = -ENOMEM;
682 goto fail;
683 }
684
685 bank->parent_priv = priv;
686 bank->id = num_banks;
687 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
688 dev_err(dev, "Invalid bank width %d\n", bank_width);
689 err = -EINVAL;
690 goto fail;
691 } else {
692 bank->width = bank_width;
693 }
694
695 /*
696 * Regs are 4 bytes wide, have data reg, no set/clear regs,
697 * and direction bits have 0 = output and 1 = input
698 */
699 gc = &bank->gc;
700 err = bgpio_init(gc, dev, 4,
701 reg_base + GIO_DATA(bank->id),
702 NULL, NULL, NULL,
703 reg_base + GIO_IODIR(bank->id), flags);
704 if (err) {
705 dev_err(dev, "bgpio_init() failed\n");
706 goto fail;
707 }
708
709 gc->of_node = np;
710 gc->owner = THIS_MODULE;
711 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
712 if (!gc->label) {
713 err = -ENOMEM;
714 goto fail;
715 }
716 gc->base = gpio_base;
717 gc->of_gpio_n_cells = 2;
718 gc->of_xlate = brcmstb_gpio_of_xlate;
719 /* not all ngpio lines are valid, will use bank width later */
720 gc->ngpio = MAX_GPIO_PER_BANK;
721 if (priv->parent_irq > 0)
722 gc->to_irq = brcmstb_gpio_to_irq;
723
724 /*
725 * Mask all interrupts by default, since wakeup interrupts may
726 * be retained from S5 cold boot
727 */
728 need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
729 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
730
731 err = gpiochip_add_data(gc, bank);
732 if (err) {
733 dev_err(dev, "Could not add gpiochip for bank %d\n",
734 bank->id);
735 goto fail;
736 }
737 gpio_base += gc->ngpio;
738
739 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
740 gc->base, gc->ngpio, bank->width);
741
742 /* Everything looks good, so add bank to list */
743 list_add(&bank->node, &priv->bank_list);
744
745 num_banks++;
746 }
747
748 priv->num_gpios = gpio_base - priv->gpio_base;
749 if (priv->parent_irq > 0) {
750 err = brcmstb_gpio_irq_setup(pdev, priv);
751 if (err)
752 goto fail;
753 }
754
755 if (priv->parent_wake_irq && need_wakeup_event)
756 pm_wakeup_event(dev, 0);
757
758 return 0;
759
760 fail:
761 (void) brcmstb_gpio_remove(pdev);
762 return err;
763 }
764
765 static const struct of_device_id brcmstb_gpio_of_match[] = {
766 { .compatible = "brcm,brcmstb-gpio" },
767 {},
768 };
769
770 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
771
772 static struct platform_driver brcmstb_gpio_driver = {
773 .driver = {
774 .name = "brcmstb-gpio",
775 .of_match_table = brcmstb_gpio_of_match,
776 .pm = &brcmstb_gpio_pm_ops,
777 },
778 .probe = brcmstb_gpio_probe,
779 .remove = brcmstb_gpio_remove,
780 .shutdown = brcmstb_gpio_shutdown,
781 };
782 module_platform_driver(brcmstb_gpio_driver);
783
784 MODULE_AUTHOR("Gregory Fong");
785 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
786 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support