2 * Intel MID GPIO driver
4 * Copyright (c) 2008-2014,2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 * Moorestown platform Langwell chip.
18 * Medfield platform Penwell chip.
19 * Clovertrail platform Cloverview chip.
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33 #include <linux/stddef.h>
35 #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
36 #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
39 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
40 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
41 * registers to control them, so we only define the order here instead of a
42 * structure, to get a bit offset for a pin (use GPDR as an example):
47 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
49 * so the bit of reg_addr is to control pin offset's GPDR feature
53 GPLR
= 0, /* pin level read-only */
54 GPDR
, /* pin direction */
57 GRER
, /* rising edge detect */
58 GFER
, /* falling edge detect */
59 GEDR
, /* edge detect result */
60 GAFR
, /* alt function */
63 /* intel_mid gpio driver data */
64 struct intel_mid_gpio_ddata
{
65 u16 ngpio
; /* number of gpio pins */
66 u32 chip_irq_type
; /* chip interrupt type */
69 struct intel_mid_gpio
{
70 struct gpio_chip chip
;
71 void __iomem
*reg_base
;
76 static void __iomem
*gpio_reg(struct gpio_chip
*chip
, unsigned offset
,
77 enum GPIO_REG reg_type
)
79 struct intel_mid_gpio
*priv
= gpiochip_get_data(chip
);
80 unsigned nreg
= chip
->ngpio
/ 32;
83 return priv
->reg_base
+ reg_type
* nreg
* 4 + reg
* 4;
86 static void __iomem
*gpio_reg_2bit(struct gpio_chip
*chip
, unsigned offset
,
87 enum GPIO_REG reg_type
)
89 struct intel_mid_gpio
*priv
= gpiochip_get_data(chip
);
90 unsigned nreg
= chip
->ngpio
/ 32;
93 return priv
->reg_base
+ reg_type
* nreg
* 4 + reg
* 4;
96 static int intel_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
98 void __iomem
*gafr
= gpio_reg_2bit(chip
, offset
, GAFR
);
99 u32 value
= readl(gafr
);
100 int shift
= (offset
% 16) << 1, af
= (value
>> shift
) & 3;
103 value
&= ~(3 << shift
);
109 static int intel_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
111 void __iomem
*gplr
= gpio_reg(chip
, offset
, GPLR
);
113 return !!(readl(gplr
) & BIT(offset
% 32));
116 static void intel_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
118 void __iomem
*gpsr
, *gpcr
;
121 gpsr
= gpio_reg(chip
, offset
, GPSR
);
122 writel(BIT(offset
% 32), gpsr
);
124 gpcr
= gpio_reg(chip
, offset
, GPCR
);
125 writel(BIT(offset
% 32), gpcr
);
129 static int intel_gpio_direction_input(struct gpio_chip
*chip
, unsigned offset
)
131 struct intel_mid_gpio
*priv
= gpiochip_get_data(chip
);
132 void __iomem
*gpdr
= gpio_reg(chip
, offset
, GPDR
);
137 pm_runtime_get(&priv
->pdev
->dev
);
139 spin_lock_irqsave(&priv
->lock
, flags
);
141 value
&= ~BIT(offset
% 32);
143 spin_unlock_irqrestore(&priv
->lock
, flags
);
146 pm_runtime_put(&priv
->pdev
->dev
);
151 static int intel_gpio_direction_output(struct gpio_chip
*chip
,
152 unsigned offset
, int value
)
154 struct intel_mid_gpio
*priv
= gpiochip_get_data(chip
);
155 void __iomem
*gpdr
= gpio_reg(chip
, offset
, GPDR
);
158 intel_gpio_set(chip
, offset
, value
);
161 pm_runtime_get(&priv
->pdev
->dev
);
163 spin_lock_irqsave(&priv
->lock
, flags
);
165 value
|= BIT(offset
% 32);
167 spin_unlock_irqrestore(&priv
->lock
, flags
);
170 pm_runtime_put(&priv
->pdev
->dev
);
175 static int intel_mid_irq_type(struct irq_data
*d
, unsigned type
)
177 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
178 struct intel_mid_gpio
*priv
= gpiochip_get_data(gc
);
179 u32 gpio
= irqd_to_hwirq(d
);
182 void __iomem
*grer
= gpio_reg(&priv
->chip
, gpio
, GRER
);
183 void __iomem
*gfer
= gpio_reg(&priv
->chip
, gpio
, GFER
);
185 if (gpio
>= priv
->chip
.ngpio
)
189 pm_runtime_get(&priv
->pdev
->dev
);
191 spin_lock_irqsave(&priv
->lock
, flags
);
192 if (type
& IRQ_TYPE_EDGE_RISING
)
193 value
= readl(grer
) | BIT(gpio
% 32);
195 value
= readl(grer
) & (~BIT(gpio
% 32));
198 if (type
& IRQ_TYPE_EDGE_FALLING
)
199 value
= readl(gfer
) | BIT(gpio
% 32);
201 value
= readl(gfer
) & (~BIT(gpio
% 32));
203 spin_unlock_irqrestore(&priv
->lock
, flags
);
206 pm_runtime_put(&priv
->pdev
->dev
);
211 static void intel_mid_irq_unmask(struct irq_data
*d
)
215 static void intel_mid_irq_mask(struct irq_data
*d
)
219 static struct irq_chip intel_mid_irqchip
= {
220 .name
= "INTEL_MID-GPIO",
221 .irq_mask
= intel_mid_irq_mask
,
222 .irq_unmask
= intel_mid_irq_unmask
,
223 .irq_set_type
= intel_mid_irq_type
,
226 static const struct intel_mid_gpio_ddata gpio_lincroft
= {
230 static const struct intel_mid_gpio_ddata gpio_penwell_aon
= {
232 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
,
235 static const struct intel_mid_gpio_ddata gpio_penwell_core
= {
237 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
,
240 static const struct intel_mid_gpio_ddata gpio_cloverview_aon
= {
242 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
| INTEL_MID_IRQ_TYPE_LEVEL
,
245 static const struct intel_mid_gpio_ddata gpio_cloverview_core
= {
247 .chip_irq_type
= INTEL_MID_IRQ_TYPE_EDGE
,
250 static const struct pci_device_id intel_gpio_ids
[] = {
253 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x080f),
254 .driver_data
= (kernel_ulong_t
)&gpio_lincroft
,
258 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081f),
259 .driver_data
= (kernel_ulong_t
)&gpio_penwell_aon
,
263 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081a),
264 .driver_data
= (kernel_ulong_t
)&gpio_penwell_core
,
268 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x08eb),
269 .driver_data
= (kernel_ulong_t
)&gpio_cloverview_aon
,
272 /* Cloverview Core */
273 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x08f7),
274 .driver_data
= (kernel_ulong_t
)&gpio_cloverview_core
,
278 MODULE_DEVICE_TABLE(pci
, intel_gpio_ids
);
280 static void intel_mid_irq_handler(struct irq_desc
*desc
)
282 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
283 struct intel_mid_gpio
*priv
= gpiochip_get_data(gc
);
284 struct irq_data
*data
= irq_desc_get_irq_data(desc
);
285 struct irq_chip
*chip
= irq_data_get_irq_chip(data
);
286 u32 base
, gpio
, mask
;
287 unsigned long pending
;
290 /* check GPIO controller to check which pin triggered the interrupt */
291 for (base
= 0; base
< priv
->chip
.ngpio
; base
+= 32) {
292 gedr
= gpio_reg(&priv
->chip
, base
, GEDR
);
293 while ((pending
= readl(gedr
))) {
294 gpio
= __ffs(pending
);
296 /* Clear before handling so we can't lose an edge */
298 generic_handle_irq(irq_find_mapping(gc
->irq
.domain
,
306 static void intel_mid_irq_init_hw(struct intel_mid_gpio
*priv
)
311 for (base
= 0; base
< priv
->chip
.ngpio
; base
+= 32) {
312 /* Clear the rising-edge detect register */
313 reg
= gpio_reg(&priv
->chip
, base
, GRER
);
315 /* Clear the falling-edge detect register */
316 reg
= gpio_reg(&priv
->chip
, base
, GFER
);
318 /* Clear the edge detect status register */
319 reg
= gpio_reg(&priv
->chip
, base
, GEDR
);
324 static int __maybe_unused
intel_gpio_runtime_idle(struct device
*dev
)
326 int err
= pm_schedule_suspend(dev
, 500);
327 return err
?: -EBUSY
;
330 static const struct dev_pm_ops intel_gpio_pm_ops
= {
331 SET_RUNTIME_PM_OPS(NULL
, NULL
, intel_gpio_runtime_idle
)
334 static int intel_gpio_probe(struct pci_dev
*pdev
,
335 const struct pci_device_id
*id
)
338 struct intel_mid_gpio
*priv
;
342 struct intel_mid_gpio_ddata
*ddata
=
343 (struct intel_mid_gpio_ddata
*)id
->driver_data
;
345 retval
= pcim_enable_device(pdev
);
349 retval
= pcim_iomap_regions(pdev
, 1 << 0 | 1 << 1, pci_name(pdev
));
351 dev_err(&pdev
->dev
, "I/O memory mapping error\n");
355 base
= pcim_iomap_table(pdev
)[1];
357 irq_base
= readl(base
);
358 gpio_base
= readl(sizeof(u32
) + base
);
360 /* release the IO mapping, since we already get the info from bar1 */
361 pcim_iounmap_regions(pdev
, 1 << 1);
363 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
367 priv
->reg_base
= pcim_iomap_table(pdev
)[0];
368 priv
->chip
.label
= dev_name(&pdev
->dev
);
369 priv
->chip
.parent
= &pdev
->dev
;
370 priv
->chip
.request
= intel_gpio_request
;
371 priv
->chip
.direction_input
= intel_gpio_direction_input
;
372 priv
->chip
.direction_output
= intel_gpio_direction_output
;
373 priv
->chip
.get
= intel_gpio_get
;
374 priv
->chip
.set
= intel_gpio_set
;
375 priv
->chip
.base
= gpio_base
;
376 priv
->chip
.ngpio
= ddata
->ngpio
;
377 priv
->chip
.can_sleep
= false;
380 spin_lock_init(&priv
->lock
);
382 pci_set_drvdata(pdev
, priv
);
383 retval
= devm_gpiochip_add_data(&pdev
->dev
, &priv
->chip
, priv
);
385 dev_err(&pdev
->dev
, "gpiochip_add error %d\n", retval
);
389 retval
= gpiochip_irqchip_add(&priv
->chip
,
396 "could not connect irqchip to gpiochip\n");
400 intel_mid_irq_init_hw(priv
);
402 gpiochip_set_chained_irqchip(&priv
->chip
,
405 intel_mid_irq_handler
);
407 pm_runtime_put_noidle(&pdev
->dev
);
408 pm_runtime_allow(&pdev
->dev
);
413 static struct pci_driver intel_gpio_driver
= {
414 .name
= "intel_mid_gpio",
415 .id_table
= intel_gpio_ids
,
416 .probe
= intel_gpio_probe
,
418 .pm
= &intel_gpio_pm_ops
,
422 builtin_pci_driver(intel_gpio_driver
);