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Linux 4.19.133
[linux/fpc-iii.git] / drivers / gpio / gpio-omap.c
blobfeabac40743ee04acdcc8f62b68ccd068f1e4a96
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio/driver.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
30
31 #define OFF_MODE 1
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
33
34 static LIST_HEAD(omap_gpio_list);
35
36 struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
47 u32 debounce;
48 u32 debounce_en;
49 };
50
51 struct gpio_bank {
52 struct list_head node;
53 void __iomem *base;
54 int irq;
55 u32 non_wakeup_gpios;
56 u32 enabled_non_wakeup_gpios;
57 struct gpio_regs context;
58 u32 saved_datain;
59 u32 level_mask;
60 u32 toggle_mask;
61 raw_spinlock_t lock;
62 raw_spinlock_t wa_lock;
63 struct gpio_chip chip;
64 struct clk *dbck;
65 u32 mod_usage;
66 u32 irq_usage;
67 u32 dbck_enable_mask;
68 bool dbck_enabled;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76 int power_mode;
77 bool workaround_enabled;
78
79 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
80 void (*set_dataout_multiple)(struct gpio_bank *bank,
81 unsigned long *mask, unsigned long *bits);
82 int (*get_context_loss_count)(struct device *dev);
83
84 struct omap_gpio_reg_offs *regs;
85 };
86
87 #define GPIO_MOD_CTRL_BIT BIT(0)
88
89 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
90 #define LINE_USED(line, offset) (line & (BIT(offset)))
91
92 static void omap_gpio_unmask_irq(struct irq_data *d);
93
94 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
95 {
96 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
97 return gpiochip_get_data(chip);
98 }
99
100 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
101 int is_input)
102 {
103 void __iomem *reg = bank->base;
104 u32 l;
105
106 reg += bank->regs->direction;
107 l = readl_relaxed(reg);
108 if (is_input)
109 l |= BIT(gpio);
110 else
111 l &= ~(BIT(gpio));
112 writel_relaxed(l, reg);
113 bank->context.oe = l;
114 }
115
116
117 /* set data out value using dedicate set/clear register */
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
119 int enable)
120 {
121 void __iomem *reg = bank->base;
122 u32 l = BIT(offset);
123
124 if (enable) {
125 reg += bank->regs->set_dataout;
126 bank->context.dataout |= l;
127 } else {
128 reg += bank->regs->clr_dataout;
129 bank->context.dataout &= ~l;
130 }
131
132 writel_relaxed(l, reg);
133 }
134
135 /* set data out value using mask register */
136 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
137 int enable)
138 {
139 void __iomem *reg = bank->base + bank->regs->dataout;
140 u32 gpio_bit = BIT(offset);
141 u32 l;
142
143 l = readl_relaxed(reg);
144 if (enable)
145 l |= gpio_bit;
146 else
147 l &= ~gpio_bit;
148 writel_relaxed(l, reg);
149 bank->context.dataout = l;
150 }
151
152 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
153 {
154 void __iomem *reg = bank->base + bank->regs->datain;
155
156 return (readl_relaxed(reg) & (BIT(offset))) != 0;
157 }
158
159 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
160 {
161 void __iomem *reg = bank->base + bank->regs->dataout;
162
163 return (readl_relaxed(reg) & (BIT(offset))) != 0;
164 }
165
166 /* set multiple data out values using dedicate set/clear register */
167 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank,
168 unsigned long *mask,
169 unsigned long *bits)
170 {
171 void __iomem *reg = bank->base;
172 u32 l;
173
174 l = *bits & *mask;
175 writel_relaxed(l, reg + bank->regs->set_dataout);
176 bank->context.dataout |= l;
177
178 l = ~*bits & *mask;
179 writel_relaxed(l, reg + bank->regs->clr_dataout);
180 bank->context.dataout &= ~l;
181 }
182
183 /* set multiple data out values using mask register */
184 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank,
185 unsigned long *mask,
186 unsigned long *bits)
187 {
188 void __iomem *reg = bank->base + bank->regs->dataout;
189 u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
190
191 writel_relaxed(l, reg);
192 bank->context.dataout = l;
193 }
194
195 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank,
196 unsigned long *mask)
197 {
198 void __iomem *reg = bank->base + bank->regs->datain;
199
200 return readl_relaxed(reg) & *mask;
201 }
202
203 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank,
204 unsigned long *mask)
205 {
206 void __iomem *reg = bank->base + bank->regs->dataout;
207
208 return readl_relaxed(reg) & *mask;
209 }
210
211 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
212 {
213 int l = readl_relaxed(base + reg);
214
215 if (set)
216 l |= mask;
217 else
218 l &= ~mask;
219
220 writel_relaxed(l, base + reg);
221 }
222
223 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
224 {
225 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
226 clk_enable(bank->dbck);
227 bank->dbck_enabled = true;
228
229 writel_relaxed(bank->dbck_enable_mask,
230 bank->base + bank->regs->debounce_en);
231 }
232 }
233
234 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
235 {
236 if (bank->dbck_enable_mask && bank->dbck_enabled) {
237 /*
238 * Disable debounce before cutting it's clock. If debounce is
239 * enabled but the clock is not, GPIO module seems to be unable
240 * to detect events and generate interrupts at least on OMAP3.
241 */
242 writel_relaxed(0, bank->base + bank->regs->debounce_en);
243
244 clk_disable(bank->dbck);
245 bank->dbck_enabled = false;
246 }
247 }
248
249 /**
250 * omap2_set_gpio_debounce - low level gpio debounce time
251 * @bank: the gpio bank we're acting upon
252 * @offset: the gpio number on this @bank
253 * @debounce: debounce time to use
254 *
255 * OMAP's debounce time is in 31us steps
256 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
257 * so we need to convert and round up to the closest unit.
258 *
259 * Return: 0 on success, negative error otherwise.
260 */
261 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
262 unsigned debounce)
263 {
264 void __iomem *reg;
265 u32 val;
266 u32 l;
267 bool enable = !!debounce;
268
269 if (!bank->dbck_flag)
270 return -ENOTSUPP;
271
272 if (enable) {
273 debounce = DIV_ROUND_UP(debounce, 31) - 1;
274 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
275 return -EINVAL;
276 }
277
278 l = BIT(offset);
279
280 clk_enable(bank->dbck);
281 reg = bank->base + bank->regs->debounce;
282 writel_relaxed(debounce, reg);
283
284 reg = bank->base + bank->regs->debounce_en;
285 val = readl_relaxed(reg);
286
287 if (enable)
288 val |= l;
289 else
290 val &= ~l;
291 bank->dbck_enable_mask = val;
292
293 writel_relaxed(val, reg);
294 clk_disable(bank->dbck);
295 /*
296 * Enable debounce clock per module.
297 * This call is mandatory because in omap_gpio_request() when
298 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
299 * runtime callbck fails to turn on dbck because dbck_enable_mask
300 * used within _gpio_dbck_enable() is still not initialized at
301 * that point. Therefore we have to enable dbck here.
302 */
303 omap_gpio_dbck_enable(bank);
304 if (bank->dbck_enable_mask) {
305 bank->context.debounce = debounce;
306 bank->context.debounce_en = val;
307 }
308
309 return 0;
310 }
311
312 /**
313 * omap_clear_gpio_debounce - clear debounce settings for a gpio
314 * @bank: the gpio bank we're acting upon
315 * @offset: the gpio number on this @bank
316 *
317 * If a gpio is using debounce, then clear the debounce enable bit and if
318 * this is the only gpio in this bank using debounce, then clear the debounce
319 * time too. The debounce clock will also be disabled when calling this function
320 * if this is the only gpio in the bank using debounce.
321 */
322 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
323 {
324 u32 gpio_bit = BIT(offset);
325
326 if (!bank->dbck_flag)
327 return;
328
329 if (!(bank->dbck_enable_mask & gpio_bit))
330 return;
331
332 bank->dbck_enable_mask &= ~gpio_bit;
333 bank->context.debounce_en &= ~gpio_bit;
334 writel_relaxed(bank->context.debounce_en,
335 bank->base + bank->regs->debounce_en);
336
337 if (!bank->dbck_enable_mask) {
338 bank->context.debounce = 0;
339 writel_relaxed(bank->context.debounce, bank->base +
340 bank->regs->debounce);
341 clk_disable(bank->dbck);
342 bank->dbck_enabled = false;
343 }
344 }
345
346 /*
347 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
348 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
349 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
350 * are capable waking up the system from off mode.
351 */
352 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
353 {
354 u32 no_wake = bank->non_wakeup_gpios;
355
356 if (no_wake)
357 return !!(~no_wake & gpio_mask);
358
359 return false;
360 }
361
362 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
363 unsigned trigger)
364 {
365 void __iomem *base = bank->base;
366 u32 gpio_bit = BIT(gpio);
367
368 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
369 trigger & IRQ_TYPE_LEVEL_LOW);
370 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
371 trigger & IRQ_TYPE_LEVEL_HIGH);
372 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
373 trigger & IRQ_TYPE_EDGE_RISING);
374 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
375 trigger & IRQ_TYPE_EDGE_FALLING);
376
377 bank->context.leveldetect0 =
378 readl_relaxed(bank->base + bank->regs->leveldetect0);
379 bank->context.leveldetect1 =
380 readl_relaxed(bank->base + bank->regs->leveldetect1);
381 bank->context.risingdetect =
382 readl_relaxed(bank->base + bank->regs->risingdetect);
383 bank->context.fallingdetect =
384 readl_relaxed(bank->base + bank->regs->fallingdetect);
385
386 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
387 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
388 bank->context.wake_en =
389 readl_relaxed(bank->base + bank->regs->wkup_en);
390 }
391
392 /* This part needs to be executed always for OMAP{34xx, 44xx} */
393 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
394 /*
395 * Log the edge gpio and manually trigger the IRQ
396 * after resume if the input level changes
397 * to avoid irq lost during PER RET/OFF mode
398 * Applies for omap2 non-wakeup gpio and all omap3 gpios
399 */
400 if (trigger & IRQ_TYPE_EDGE_BOTH)
401 bank->enabled_non_wakeup_gpios |= gpio_bit;
402 else
403 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
404 }
405
406 bank->level_mask =
407 readl_relaxed(bank->base + bank->regs->leveldetect0) |
408 readl_relaxed(bank->base + bank->regs->leveldetect1);
409 }
410
411 #ifdef CONFIG_ARCH_OMAP1
412 /*
413 * This only applies to chips that can't do both rising and falling edge
414 * detection at once. For all other chips, this function is a noop.
415 */
416 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
417 {
418 void __iomem *reg = bank->base;
419 u32 l = 0;
420
421 if (!bank->regs->irqctrl)
422 return;
423
424 reg += bank->regs->irqctrl;
425
426 l = readl_relaxed(reg);
427 if ((l >> gpio) & 1)
428 l &= ~(BIT(gpio));
429 else
430 l |= BIT(gpio);
431
432 writel_relaxed(l, reg);
433 }
434 #else
435 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
436 #endif
437
438 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
439 unsigned trigger)
440 {
441 void __iomem *reg = bank->base;
442 void __iomem *base = bank->base;
443 u32 l = 0;
444
445 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
446 omap_set_gpio_trigger(bank, gpio, trigger);
447 } else if (bank->regs->irqctrl) {
448 reg += bank->regs->irqctrl;
449
450 l = readl_relaxed(reg);
451 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
452 bank->toggle_mask |= BIT(gpio);
453 if (trigger & IRQ_TYPE_EDGE_RISING)
454 l |= BIT(gpio);
455 else if (trigger & IRQ_TYPE_EDGE_FALLING)
456 l &= ~(BIT(gpio));
457 else
458 return -EINVAL;
459
460 writel_relaxed(l, reg);
461 } else if (bank->regs->edgectrl1) {
462 if (gpio & 0x08)
463 reg += bank->regs->edgectrl2;
464 else
465 reg += bank->regs->edgectrl1;
466
467 gpio &= 0x07;
468 l = readl_relaxed(reg);
469 l &= ~(3 << (gpio << 1));
470 if (trigger & IRQ_TYPE_EDGE_RISING)
471 l |= 2 << (gpio << 1);
472 if (trigger & IRQ_TYPE_EDGE_FALLING)
473 l |= BIT(gpio << 1);
474
475 /* Enable wake-up during idle for dynamic tick */
476 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
477 bank->context.wake_en =
478 readl_relaxed(bank->base + bank->regs->wkup_en);
479 writel_relaxed(l, reg);
480 }
481 return 0;
482 }
483
484 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
485 {
486 if (bank->regs->pinctrl) {
487 void __iomem *reg = bank->base + bank->regs->pinctrl;
488
489 /* Claim the pin for MPU */
490 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
491 }
492
493 if (bank->regs->ctrl && !BANK_USED(bank)) {
494 void __iomem *reg = bank->base + bank->regs->ctrl;
495 u32 ctrl;
496
497 ctrl = readl_relaxed(reg);
498 /* Module is enabled, clocks are not gated */
499 ctrl &= ~GPIO_MOD_CTRL_BIT;
500 writel_relaxed(ctrl, reg);
501 bank->context.ctrl = ctrl;
502 }
503 }
504
505 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
506 {
507 void __iomem *base = bank->base;
508
509 if (bank->regs->wkup_en &&
510 !LINE_USED(bank->mod_usage, offset) &&
511 !LINE_USED(bank->irq_usage, offset)) {
512 /* Disable wake-up during idle for dynamic tick */
513 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
514 bank->context.wake_en =
515 readl_relaxed(bank->base + bank->regs->wkup_en);
516 }
517
518 if (bank->regs->ctrl && !BANK_USED(bank)) {
519 void __iomem *reg = bank->base + bank->regs->ctrl;
520 u32 ctrl;
521
522 ctrl = readl_relaxed(reg);
523 /* Module is disabled, clocks are gated */
524 ctrl |= GPIO_MOD_CTRL_BIT;
525 writel_relaxed(ctrl, reg);
526 bank->context.ctrl = ctrl;
527 }
528 }
529
530 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
531 {
532 void __iomem *reg = bank->base + bank->regs->direction;
533
534 return readl_relaxed(reg) & BIT(offset);
535 }
536
537 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
538 {
539 if (!LINE_USED(bank->mod_usage, offset)) {
540 omap_enable_gpio_module(bank, offset);
541 omap_set_gpio_direction(bank, offset, 1);
542 }
543 bank->irq_usage |= BIT(offset);
544 }
545
546 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
547 {
548 struct gpio_bank *bank = omap_irq_data_get_bank(d);
549 int retval;
550 unsigned long flags;
551 unsigned offset = d->hwirq;
552
553 if (type & ~IRQ_TYPE_SENSE_MASK)
554 return -EINVAL;
555
556 if (!bank->regs->leveldetect0 &&
557 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
558 return -EINVAL;
559
560 raw_spin_lock_irqsave(&bank->lock, flags);
561 retval = omap_set_gpio_triggering(bank, offset, type);
562 if (retval) {
563 raw_spin_unlock_irqrestore(&bank->lock, flags);
564 goto error;
565 }
566 omap_gpio_init_irq(bank, offset);
567 if (!omap_gpio_is_input(bank, offset)) {
568 raw_spin_unlock_irqrestore(&bank->lock, flags);
569 retval = -EINVAL;
570 goto error;
571 }
572 raw_spin_unlock_irqrestore(&bank->lock, flags);
573
574 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
575 irq_set_handler_locked(d, handle_level_irq);
576 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
577 /*
578 * Edge IRQs are already cleared/acked in irq_handler and
579 * not need to be masked, as result handle_edge_irq()
580 * logic is excessed here and may cause lose of interrupts.
581 * So just use handle_simple_irq.
582 */
583 irq_set_handler_locked(d, handle_simple_irq);
584
585 return 0;
586
587 error:
588 return retval;
589 }
590
591 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
592 {
593 void __iomem *reg = bank->base;
594
595 reg += bank->regs->irqstatus;
596 writel_relaxed(gpio_mask, reg);
597
598 /* Workaround for clearing DSP GPIO interrupts to allow retention */
599 if (bank->regs->irqstatus2) {
600 reg = bank->base + bank->regs->irqstatus2;
601 writel_relaxed(gpio_mask, reg);
602 }
603
604 /* Flush posted write for the irq status to avoid spurious interrupts */
605 readl_relaxed(reg);
606 }
607
608 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
609 unsigned offset)
610 {
611 omap_clear_gpio_irqbank(bank, BIT(offset));
612 }
613
614 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
615 {
616 void __iomem *reg = bank->base;
617 u32 l;
618 u32 mask = (BIT(bank->width)) - 1;
619
620 reg += bank->regs->irqenable;
621 l = readl_relaxed(reg);
622 if (bank->regs->irqenable_inv)
623 l = ~l;
624 l &= mask;
625 return l;
626 }
627
628 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
629 {
630 void __iomem *reg = bank->base;
631 u32 l;
632
633 if (bank->regs->set_irqenable) {
634 reg += bank->regs->set_irqenable;
635 l = gpio_mask;
636 bank->context.irqenable1 |= gpio_mask;
637 } else {
638 reg += bank->regs->irqenable;
639 l = readl_relaxed(reg);
640 if (bank->regs->irqenable_inv)
641 l &= ~gpio_mask;
642 else
643 l |= gpio_mask;
644 bank->context.irqenable1 = l;
645 }
646
647 writel_relaxed(l, reg);
648 }
649
650 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
651 {
652 void __iomem *reg = bank->base;
653 u32 l;
654
655 if (bank->regs->clr_irqenable) {
656 reg += bank->regs->clr_irqenable;
657 l = gpio_mask;
658 bank->context.irqenable1 &= ~gpio_mask;
659 } else {
660 reg += bank->regs->irqenable;
661 l = readl_relaxed(reg);
662 if (bank->regs->irqenable_inv)
663 l |= gpio_mask;
664 else
665 l &= ~gpio_mask;
666 bank->context.irqenable1 = l;
667 }
668
669 writel_relaxed(l, reg);
670 }
671
672 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
673 unsigned offset, int enable)
674 {
675 if (enable)
676 omap_enable_gpio_irqbank(bank, BIT(offset));
677 else
678 omap_disable_gpio_irqbank(bank, BIT(offset));
679 }
680
681 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
682 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
683 {
684 struct gpio_bank *bank = omap_irq_data_get_bank(d);
685
686 return irq_set_irq_wake(bank->irq, enable);
687 }
688
689 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
690 {
691 struct gpio_bank *bank = gpiochip_get_data(chip);
692 unsigned long flags;
693
694 /*
695 * If this is the first gpio_request for the bank,
696 * enable the bank module.
697 */
698 if (!BANK_USED(bank))
699 pm_runtime_get_sync(chip->parent);
700
701 raw_spin_lock_irqsave(&bank->lock, flags);
702 omap_enable_gpio_module(bank, offset);
703 bank->mod_usage |= BIT(offset);
704 raw_spin_unlock_irqrestore(&bank->lock, flags);
705
706 return 0;
707 }
708
709 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
710 {
711 struct gpio_bank *bank = gpiochip_get_data(chip);
712 unsigned long flags;
713
714 raw_spin_lock_irqsave(&bank->lock, flags);
715 bank->mod_usage &= ~(BIT(offset));
716 if (!LINE_USED(bank->irq_usage, offset)) {
717 omap_set_gpio_direction(bank, offset, 1);
718 omap_clear_gpio_debounce(bank, offset);
719 }
720 omap_disable_gpio_module(bank, offset);
721 raw_spin_unlock_irqrestore(&bank->lock, flags);
722
723 /*
724 * If this is the last gpio to be freed in the bank,
725 * disable the bank module.
726 */
727 if (!BANK_USED(bank))
728 pm_runtime_put(chip->parent);
729 }
730
731 /*
732 * We need to unmask the GPIO bank interrupt as soon as possible to
733 * avoid missing GPIO interrupts for other lines in the bank.
734 * Then we need to mask-read-clear-unmask the triggered GPIO lines
735 * in the bank to avoid missing nested interrupts for a GPIO line.
736 * If we wait to unmask individual GPIO lines in the bank after the
737 * line's interrupt handler has been run, we may miss some nested
738 * interrupts.
739 */
740 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
741 {
742 void __iomem *isr_reg = NULL;
743 u32 enabled, isr, level_mask;
744 unsigned int bit;
745 struct gpio_bank *bank = gpiobank;
746 unsigned long wa_lock_flags;
747 unsigned long lock_flags;
748
749 isr_reg = bank->base + bank->regs->irqstatus;
750 if (WARN_ON(!isr_reg))
751 goto exit;
752
753 pm_runtime_get_sync(bank->chip.parent);
754
755 while (1) {
756 raw_spin_lock_irqsave(&bank->lock, lock_flags);
757
758 enabled = omap_get_gpio_irqbank_mask(bank);
759 isr = readl_relaxed(isr_reg) & enabled;
760
761 if (bank->level_mask)
762 level_mask = bank->level_mask & enabled;
763 else
764 level_mask = 0;
765
766 /* clear edge sensitive interrupts before handler(s) are
767 called so that we don't miss any interrupt occurred while
768 executing them */
769 if (isr & ~level_mask)
770 omap_clear_gpio_irqbank(bank, isr & ~level_mask);
771
772 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
773
774 if (!isr)
775 break;
776
777 while (isr) {
778 bit = __ffs(isr);
779 isr &= ~(BIT(bit));
780
781 raw_spin_lock_irqsave(&bank->lock, lock_flags);
782 /*
783 * Some chips can't respond to both rising and falling
784 * at the same time. If this irq was requested with
785 * both flags, we need to flip the ICR data for the IRQ
786 * to respond to the IRQ for the opposite direction.
787 * This will be indicated in the bank toggle_mask.
788 */
789 if (bank->toggle_mask & (BIT(bit)))
790 omap_toggle_gpio_edge_triggering(bank, bit);
791
792 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
793
794 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
795
796 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
797 bit));
798
799 raw_spin_unlock_irqrestore(&bank->wa_lock,
800 wa_lock_flags);
801 }
802 }
803 exit:
804 pm_runtime_put(bank->chip.parent);
805 return IRQ_HANDLED;
806 }
807
808 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
809 {
810 struct gpio_bank *bank = omap_irq_data_get_bank(d);
811 unsigned long flags;
812 unsigned offset = d->hwirq;
813
814 raw_spin_lock_irqsave(&bank->lock, flags);
815
816 if (!LINE_USED(bank->mod_usage, offset))
817 omap_set_gpio_direction(bank, offset, 1);
818 else if (!omap_gpio_is_input(bank, offset))
819 goto err;
820 omap_enable_gpio_module(bank, offset);
821 bank->irq_usage |= BIT(offset);
822
823 raw_spin_unlock_irqrestore(&bank->lock, flags);
824 omap_gpio_unmask_irq(d);
825
826 return 0;
827 err:
828 raw_spin_unlock_irqrestore(&bank->lock, flags);
829 return -EINVAL;
830 }
831
832 static void omap_gpio_irq_shutdown(struct irq_data *d)
833 {
834 struct gpio_bank *bank = omap_irq_data_get_bank(d);
835 unsigned long flags;
836 unsigned offset = d->hwirq;
837
838 raw_spin_lock_irqsave(&bank->lock, flags);
839 bank->irq_usage &= ~(BIT(offset));
840 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
841 omap_clear_gpio_irqstatus(bank, offset);
842 omap_set_gpio_irqenable(bank, offset, 0);
843 if (!LINE_USED(bank->mod_usage, offset))
844 omap_clear_gpio_debounce(bank, offset);
845 omap_disable_gpio_module(bank, offset);
846 raw_spin_unlock_irqrestore(&bank->lock, flags);
847 }
848
849 static void omap_gpio_irq_bus_lock(struct irq_data *data)
850 {
851 struct gpio_bank *bank = omap_irq_data_get_bank(data);
852
853 if (!BANK_USED(bank))
854 pm_runtime_get_sync(bank->chip.parent);
855 }
856
857 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
858 {
859 struct gpio_bank *bank = omap_irq_data_get_bank(data);
860
861 /*
862 * If this is the last IRQ to be freed in the bank,
863 * disable the bank module.
864 */
865 if (!BANK_USED(bank))
866 pm_runtime_put(bank->chip.parent);
867 }
868
869 static void omap_gpio_ack_irq(struct irq_data *d)
870 {
871 struct gpio_bank *bank = omap_irq_data_get_bank(d);
872 unsigned offset = d->hwirq;
873
874 omap_clear_gpio_irqstatus(bank, offset);
875 }
876
877 static void omap_gpio_mask_irq(struct irq_data *d)
878 {
879 struct gpio_bank *bank = omap_irq_data_get_bank(d);
880 unsigned offset = d->hwirq;
881 unsigned long flags;
882
883 raw_spin_lock_irqsave(&bank->lock, flags);
884 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
885 omap_set_gpio_irqenable(bank, offset, 0);
886 raw_spin_unlock_irqrestore(&bank->lock, flags);
887 }
888
889 static void omap_gpio_unmask_irq(struct irq_data *d)
890 {
891 struct gpio_bank *bank = omap_irq_data_get_bank(d);
892 unsigned offset = d->hwirq;
893 u32 trigger = irqd_get_trigger_type(d);
894 unsigned long flags;
895
896 raw_spin_lock_irqsave(&bank->lock, flags);
897 omap_set_gpio_irqenable(bank, offset, 1);
898
899 /*
900 * For level-triggered GPIOs, clearing must be done after the source
901 * is cleared, thus after the handler has run. OMAP4 needs this done
902 * after enabing the interrupt to clear the wakeup status.
903 */
904 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
905 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
906 omap_clear_gpio_irqstatus(bank, offset);
907
908 if (trigger)
909 omap_set_gpio_triggering(bank, offset, trigger);
910
911 raw_spin_unlock_irqrestore(&bank->lock, flags);
912 }
913
914 /*---------------------------------------------------------------------*/
915
916 static int omap_mpuio_suspend_noirq(struct device *dev)
917 {
918 struct platform_device *pdev = to_platform_device(dev);
919 struct gpio_bank *bank = platform_get_drvdata(pdev);
920 void __iomem *mask_reg = bank->base +
921 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
922 unsigned long flags;
923
924 raw_spin_lock_irqsave(&bank->lock, flags);
925 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
926 raw_spin_unlock_irqrestore(&bank->lock, flags);
927
928 return 0;
929 }
930
931 static int omap_mpuio_resume_noirq(struct device *dev)
932 {
933 struct platform_device *pdev = to_platform_device(dev);
934 struct gpio_bank *bank = platform_get_drvdata(pdev);
935 void __iomem *mask_reg = bank->base +
936 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
937 unsigned long flags;
938
939 raw_spin_lock_irqsave(&bank->lock, flags);
940 writel_relaxed(bank->context.wake_en, mask_reg);
941 raw_spin_unlock_irqrestore(&bank->lock, flags);
942
943 return 0;
944 }
945
946 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
947 .suspend_noirq = omap_mpuio_suspend_noirq,
948 .resume_noirq = omap_mpuio_resume_noirq,
949 };
950
951 /* use platform_driver for this. */
952 static struct platform_driver omap_mpuio_driver = {
953 .driver = {
954 .name = "mpuio",
955 .pm = &omap_mpuio_dev_pm_ops,
956 },
957 };
958
959 static struct platform_device omap_mpuio_device = {
960 .name = "mpuio",
961 .id = -1,
962 .dev = {
963 .driver = &omap_mpuio_driver.driver,
964 }
965 /* could list the /proc/iomem resources */
966 };
967
968 static inline void omap_mpuio_init(struct gpio_bank *bank)
969 {
970 platform_set_drvdata(&omap_mpuio_device, bank);
971
972 if (platform_driver_register(&omap_mpuio_driver) == 0)
973 (void) platform_device_register(&omap_mpuio_device);
974 }
975
976 /*---------------------------------------------------------------------*/
977
978 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
979 {
980 struct gpio_bank *bank;
981 unsigned long flags;
982 void __iomem *reg;
983 int dir;
984
985 bank = gpiochip_get_data(chip);
986 reg = bank->base + bank->regs->direction;
987 raw_spin_lock_irqsave(&bank->lock, flags);
988 dir = !!(readl_relaxed(reg) & BIT(offset));
989 raw_spin_unlock_irqrestore(&bank->lock, flags);
990 return dir;
991 }
992
993 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
994 {
995 struct gpio_bank *bank;
996 unsigned long flags;
997
998 bank = gpiochip_get_data(chip);
999 raw_spin_lock_irqsave(&bank->lock, flags);
1000 omap_set_gpio_direction(bank, offset, 1);
1001 raw_spin_unlock_irqrestore(&bank->lock, flags);
1002 return 0;
1003 }
1004
1005 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
1006 {
1007 struct gpio_bank *bank;
1008
1009 bank = gpiochip_get_data(chip);
1010
1011 if (omap_gpio_is_input(bank, offset))
1012 return omap_get_gpio_datain(bank, offset);
1013 else
1014 return omap_get_gpio_dataout(bank, offset);
1015 }
1016
1017 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1018 {
1019 struct gpio_bank *bank;
1020 unsigned long flags;
1021
1022 bank = gpiochip_get_data(chip);
1023 raw_spin_lock_irqsave(&bank->lock, flags);
1024 bank->set_dataout(bank, offset, value);
1025 omap_set_gpio_direction(bank, offset, 0);
1026 raw_spin_unlock_irqrestore(&bank->lock, flags);
1027 return 0;
1028 }
1029
1030 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1031 unsigned long *bits)
1032 {
1033 struct gpio_bank *bank = gpiochip_get_data(chip);
1034 void __iomem *reg = bank->base + bank->regs->direction;
1035 unsigned long in = readl_relaxed(reg), l;
1036
1037 *bits = 0;
1038
1039 l = in & *mask;
1040 if (l)
1041 *bits |= omap_get_gpio_datain_multiple(bank, &l);
1042
1043 l = ~in & *mask;
1044 if (l)
1045 *bits |= omap_get_gpio_dataout_multiple(bank, &l);
1046
1047 return 0;
1048 }
1049
1050 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1051 unsigned debounce)
1052 {
1053 struct gpio_bank *bank;
1054 unsigned long flags;
1055 int ret;
1056
1057 bank = gpiochip_get_data(chip);
1058
1059 raw_spin_lock_irqsave(&bank->lock, flags);
1060 ret = omap2_set_gpio_debounce(bank, offset, debounce);
1061 raw_spin_unlock_irqrestore(&bank->lock, flags);
1062
1063 if (ret)
1064 dev_info(chip->parent,
1065 "Could not set line %u debounce to %u microseconds (%d)",
1066 offset, debounce, ret);
1067
1068 return ret;
1069 }
1070
1071 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
1072 unsigned long config)
1073 {
1074 u32 debounce;
1075
1076 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1077 return -ENOTSUPP;
1078
1079 debounce = pinconf_to_config_argument(config);
1080 return omap_gpio_debounce(chip, offset, debounce);
1081 }
1082
1083 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1084 {
1085 struct gpio_bank *bank;
1086 unsigned long flags;
1087
1088 bank = gpiochip_get_data(chip);
1089 raw_spin_lock_irqsave(&bank->lock, flags);
1090 bank->set_dataout(bank, offset, value);
1091 raw_spin_unlock_irqrestore(&bank->lock, flags);
1092 }
1093
1094 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1095 unsigned long *bits)
1096 {
1097 struct gpio_bank *bank = gpiochip_get_data(chip);
1098 unsigned long flags;
1099
1100 raw_spin_lock_irqsave(&bank->lock, flags);
1101 bank->set_dataout_multiple(bank, mask, bits);
1102 raw_spin_unlock_irqrestore(&bank->lock, flags);
1103 }
1104
1105 /*---------------------------------------------------------------------*/
1106
1107 static void omap_gpio_show_rev(struct gpio_bank *bank)
1108 {
1109 static bool called;
1110 u32 rev;
1111
1112 if (called || bank->regs->revision == USHRT_MAX)
1113 return;
1114
1115 rev = readw_relaxed(bank->base + bank->regs->revision);
1116 pr_info("OMAP GPIO hardware version %d.%d\n",
1117 (rev >> 4) & 0x0f, rev & 0x0f);
1118
1119 called = true;
1120 }
1121
1122 static void omap_gpio_mod_init(struct gpio_bank *bank)
1123 {
1124 void __iomem *base = bank->base;
1125 u32 l = 0xffffffff;
1126
1127 if (bank->width == 16)
1128 l = 0xffff;
1129
1130 if (bank->is_mpuio) {
1131 writel_relaxed(l, bank->base + bank->regs->irqenable);
1132 return;
1133 }
1134
1135 omap_gpio_rmw(base, bank->regs->irqenable, l,
1136 bank->regs->irqenable_inv);
1137 omap_gpio_rmw(base, bank->regs->irqstatus, l,
1138 !bank->regs->irqenable_inv);
1139 if (bank->regs->debounce_en)
1140 writel_relaxed(0, base + bank->regs->debounce_en);
1141
1142 /* Save OE default value (0xffffffff) in the context */
1143 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1144 /* Initialize interface clk ungated, module enabled */
1145 if (bank->regs->ctrl)
1146 writel_relaxed(0, base + bank->regs->ctrl);
1147 }
1148
1149 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1150 {
1151 struct gpio_irq_chip *irq;
1152 static int gpio;
1153 const char *label;
1154 int irq_base = 0;
1155 int ret;
1156
1157 /*
1158 * REVISIT eventually switch from OMAP-specific gpio structs
1159 * over to the generic ones
1160 */
1161 bank->chip.request = omap_gpio_request;
1162 bank->chip.free = omap_gpio_free;
1163 bank->chip.get_direction = omap_gpio_get_direction;
1164 bank->chip.direction_input = omap_gpio_input;
1165 bank->chip.get = omap_gpio_get;
1166 bank->chip.get_multiple = omap_gpio_get_multiple;
1167 bank->chip.direction_output = omap_gpio_output;
1168 bank->chip.set_config = omap_gpio_set_config;
1169 bank->chip.set = omap_gpio_set;
1170 bank->chip.set_multiple = omap_gpio_set_multiple;
1171 if (bank->is_mpuio) {
1172 bank->chip.label = "mpuio";
1173 if (bank->regs->wkup_en)
1174 bank->chip.parent = &omap_mpuio_device.dev;
1175 bank->chip.base = OMAP_MPUIO(0);
1176 } else {
1177 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1178 gpio, gpio + bank->width - 1);
1179 if (!label)
1180 return -ENOMEM;
1181 bank->chip.label = label;
1182 bank->chip.base = gpio;
1183 }
1184 bank->chip.ngpio = bank->width;
1185
1186 #ifdef CONFIG_ARCH_OMAP1
1187 /*
1188 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1189 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1190 */
1191 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1192 -1, 0, bank->width, 0);
1193 if (irq_base < 0) {
1194 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1195 return -ENODEV;
1196 }
1197 #endif
1198
1199 /* MPUIO is a bit different, reading IRQ status clears it */
1200 if (bank->is_mpuio) {
1201 irqc->irq_ack = dummy_irq_chip.irq_ack;
1202 if (!bank->regs->wkup_en)
1203 irqc->irq_set_wake = NULL;
1204 }
1205
1206 irq = &bank->chip.irq;
1207 irq->chip = irqc;
1208 irq->handler = handle_bad_irq;
1209 irq->default_type = IRQ_TYPE_NONE;
1210 irq->num_parents = 1;
1211 irq->parents = &bank->irq;
1212 irq->first = irq_base;
1213
1214 ret = gpiochip_add_data(&bank->chip, bank);
1215 if (ret) {
1216 dev_err(bank->chip.parent,
1217 "Could not register gpio chip %d\n", ret);
1218 return ret;
1219 }
1220
1221 ret = devm_request_irq(bank->chip.parent, bank->irq,
1222 omap_gpio_irq_handler,
1223 0, dev_name(bank->chip.parent), bank);
1224 if (ret)
1225 gpiochip_remove(&bank->chip);
1226
1227 if (!bank->is_mpuio)
1228 gpio += bank->width;
1229
1230 return ret;
1231 }
1232
1233 static const struct of_device_id omap_gpio_match[];
1234
1235 static int omap_gpio_probe(struct platform_device *pdev)
1236 {
1237 struct device *dev = &pdev->dev;
1238 struct device_node *node = dev->of_node;
1239 const struct of_device_id *match;
1240 const struct omap_gpio_platform_data *pdata;
1241 struct resource *res;
1242 struct gpio_bank *bank;
1243 struct irq_chip *irqc;
1244 int ret;
1245
1246 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1247
1248 pdata = match ? match->data : dev_get_platdata(dev);
1249 if (!pdata)
1250 return -EINVAL;
1251
1252 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1253 if (!bank)
1254 return -ENOMEM;
1255
1256 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1257 if (!irqc)
1258 return -ENOMEM;
1259
1260 irqc->irq_startup = omap_gpio_irq_startup,
1261 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1262 irqc->irq_ack = omap_gpio_ack_irq,
1263 irqc->irq_mask = omap_gpio_mask_irq,
1264 irqc->irq_unmask = omap_gpio_unmask_irq,
1265 irqc->irq_set_type = omap_gpio_irq_type,
1266 irqc->irq_set_wake = omap_gpio_wake_enable,
1267 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1268 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1269 irqc->name = dev_name(&pdev->dev);
1270 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1271
1272 bank->irq = platform_get_irq(pdev, 0);
1273 if (bank->irq <= 0) {
1274 if (!bank->irq)
1275 bank->irq = -ENXIO;
1276 if (bank->irq != -EPROBE_DEFER)
1277 dev_err(dev,
1278 "can't get irq resource ret=%d\n", bank->irq);
1279 return bank->irq;
1280 }
1281
1282 bank->chip.parent = dev;
1283 bank->chip.owner = THIS_MODULE;
1284 bank->dbck_flag = pdata->dbck_flag;
1285 bank->stride = pdata->bank_stride;
1286 bank->width = pdata->bank_width;
1287 bank->is_mpuio = pdata->is_mpuio;
1288 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1289 bank->regs = pdata->regs;
1290 #ifdef CONFIG_OF_GPIO
1291 bank->chip.of_node = of_node_get(node);
1292 #endif
1293 if (node) {
1294 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1295 bank->loses_context = true;
1296 } else {
1297 bank->loses_context = pdata->loses_context;
1298
1299 if (bank->loses_context)
1300 bank->get_context_loss_count =
1301 pdata->get_context_loss_count;
1302 }
1303
1304 if (bank->regs->set_dataout && bank->regs->clr_dataout) {
1305 bank->set_dataout = omap_set_gpio_dataout_reg;
1306 bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple;
1307 } else {
1308 bank->set_dataout = omap_set_gpio_dataout_mask;
1309 bank->set_dataout_multiple =
1310 omap_set_gpio_dataout_mask_multiple;
1311 }
1312
1313 raw_spin_lock_init(&bank->lock);
1314 raw_spin_lock_init(&bank->wa_lock);
1315
1316 /* Static mapping, never released */
1317 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1318 bank->base = devm_ioremap_resource(dev, res);
1319 if (IS_ERR(bank->base)) {
1320 return PTR_ERR(bank->base);
1321 }
1322
1323 if (bank->dbck_flag) {
1324 bank->dbck = devm_clk_get(dev, "dbclk");
1325 if (IS_ERR(bank->dbck)) {
1326 dev_err(dev,
1327 "Could not get gpio dbck. Disable debounce\n");
1328 bank->dbck_flag = false;
1329 } else {
1330 clk_prepare(bank->dbck);
1331 }
1332 }
1333
1334 platform_set_drvdata(pdev, bank);
1335
1336 pm_runtime_enable(dev);
1337 pm_runtime_irq_safe(dev);
1338 pm_runtime_get_sync(dev);
1339
1340 if (bank->is_mpuio)
1341 omap_mpuio_init(bank);
1342
1343 omap_gpio_mod_init(bank);
1344
1345 ret = omap_gpio_chip_init(bank, irqc);
1346 if (ret) {
1347 pm_runtime_put_sync(dev);
1348 pm_runtime_disable(dev);
1349 if (bank->dbck_flag)
1350 clk_unprepare(bank->dbck);
1351 return ret;
1352 }
1353
1354 omap_gpio_show_rev(bank);
1355
1356 pm_runtime_put(dev);
1357
1358 list_add_tail(&bank->node, &omap_gpio_list);
1359
1360 return 0;
1361 }
1362
1363 static int omap_gpio_remove(struct platform_device *pdev)
1364 {
1365 struct gpio_bank *bank = platform_get_drvdata(pdev);
1366
1367 list_del(&bank->node);
1368 gpiochip_remove(&bank->chip);
1369 pm_runtime_disable(&pdev->dev);
1370 if (bank->dbck_flag)
1371 clk_unprepare(bank->dbck);
1372
1373 return 0;
1374 }
1375
1376 #ifdef CONFIG_ARCH_OMAP2PLUS
1377
1378 #if defined(CONFIG_PM)
1379 static void omap_gpio_restore_context(struct gpio_bank *bank);
1380
1381 static int omap_gpio_runtime_suspend(struct device *dev)
1382 {
1383 struct platform_device *pdev = to_platform_device(dev);
1384 struct gpio_bank *bank = platform_get_drvdata(pdev);
1385 u32 l1 = 0, l2 = 0;
1386 unsigned long flags;
1387 u32 wake_low, wake_hi;
1388
1389 raw_spin_lock_irqsave(&bank->lock, flags);
1390
1391 /*
1392 * Only edges can generate a wakeup event to the PRCM.
1393 *
1394 * Therefore, ensure any wake-up capable GPIOs have
1395 * edge-detection enabled before going idle to ensure a wakeup
1396 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1397 * NDA TRM 25.5.3.1)
1398 *
1399 * The normal values will be restored upon ->runtime_resume()
1400 * by writing back the values saved in bank->context.
1401 */
1402 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1403 if (wake_low)
1404 writel_relaxed(wake_low | bank->context.fallingdetect,
1405 bank->base + bank->regs->fallingdetect);
1406 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1407 if (wake_hi)
1408 writel_relaxed(wake_hi | bank->context.risingdetect,
1409 bank->base + bank->regs->risingdetect);
1410
1411 if (!bank->enabled_non_wakeup_gpios)
1412 goto update_gpio_context_count;
1413
1414 if (bank->power_mode != OFF_MODE) {
1415 bank->power_mode = 0;
1416 goto update_gpio_context_count;
1417 }
1418 /*
1419 * If going to OFF, remove triggering for all
1420 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1421 * generated. See OMAP2420 Errata item 1.101.
1422 */
1423 bank->saved_datain = readl_relaxed(bank->base +
1424 bank->regs->datain);
1425 l1 = bank->context.fallingdetect;
1426 l2 = bank->context.risingdetect;
1427
1428 l1 &= ~bank->enabled_non_wakeup_gpios;
1429 l2 &= ~bank->enabled_non_wakeup_gpios;
1430
1431 writel_relaxed(l1, bank->base + bank->regs->fallingdetect);
1432 writel_relaxed(l2, bank->base + bank->regs->risingdetect);
1433
1434 bank->workaround_enabled = true;
1435
1436 update_gpio_context_count:
1437 if (bank->get_context_loss_count)
1438 bank->context_loss_count =
1439 bank->get_context_loss_count(dev);
1440
1441 omap_gpio_dbck_disable(bank);
1442 raw_spin_unlock_irqrestore(&bank->lock, flags);
1443
1444 return 0;
1445 }
1446
1447 static void omap_gpio_init_context(struct gpio_bank *p);
1448
1449 static int omap_gpio_runtime_resume(struct device *dev)
1450 {
1451 struct platform_device *pdev = to_platform_device(dev);
1452 struct gpio_bank *bank = platform_get_drvdata(pdev);
1453 u32 l = 0, gen, gen0, gen1;
1454 unsigned long flags;
1455 int c;
1456
1457 raw_spin_lock_irqsave(&bank->lock, flags);
1458
1459 /*
1460 * On the first resume during the probe, the context has not
1461 * been initialised and so initialise it now. Also initialise
1462 * the context loss count.
1463 */
1464 if (bank->loses_context && !bank->context_valid) {
1465 omap_gpio_init_context(bank);
1466
1467 if (bank->get_context_loss_count)
1468 bank->context_loss_count =
1469 bank->get_context_loss_count(dev);
1470 }
1471
1472 omap_gpio_dbck_enable(bank);
1473
1474 /*
1475 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1476 * GPIOs were set to edge trigger also in order to be able to
1477 * generate a PRCM wakeup. Here we restore the
1478 * pre-runtime_suspend() values for edge triggering.
1479 */
1480 writel_relaxed(bank->context.fallingdetect,
1481 bank->base + bank->regs->fallingdetect);
1482 writel_relaxed(bank->context.risingdetect,
1483 bank->base + bank->regs->risingdetect);
1484
1485 if (bank->loses_context) {
1486 if (!bank->get_context_loss_count) {
1487 omap_gpio_restore_context(bank);
1488 } else {
1489 c = bank->get_context_loss_count(dev);
1490 if (c != bank->context_loss_count) {
1491 omap_gpio_restore_context(bank);
1492 } else {
1493 raw_spin_unlock_irqrestore(&bank->lock, flags);
1494 return 0;
1495 }
1496 }
1497 }
1498
1499 if (!bank->workaround_enabled) {
1500 raw_spin_unlock_irqrestore(&bank->lock, flags);
1501 return 0;
1502 }
1503
1504 l = readl_relaxed(bank->base + bank->regs->datain);
1505
1506 /*
1507 * Check if any of the non-wakeup interrupt GPIOs have changed
1508 * state. If so, generate an IRQ by software. This is
1509 * horribly racy, but it's the best we can do to work around
1510 * this silicon bug.
1511 */
1512 l ^= bank->saved_datain;
1513 l &= bank->enabled_non_wakeup_gpios;
1514
1515 /*
1516 * No need to generate IRQs for the rising edge for gpio IRQs
1517 * configured with falling edge only; and vice versa.
1518 */
1519 gen0 = l & bank->context.fallingdetect;
1520 gen0 &= bank->saved_datain;
1521
1522 gen1 = l & bank->context.risingdetect;
1523 gen1 &= ~(bank->saved_datain);
1524
1525 /* FIXME: Consider GPIO IRQs with level detections properly! */
1526 gen = l & (~(bank->context.fallingdetect) &
1527 ~(bank->context.risingdetect));
1528 /* Consider all GPIO IRQs needed to be updated */
1529 gen |= gen0 | gen1;
1530
1531 if (gen) {
1532 u32 old0, old1;
1533
1534 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1535 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1536
1537 if (!bank->regs->irqstatus_raw0) {
1538 writel_relaxed(old0 | gen, bank->base +
1539 bank->regs->leveldetect0);
1540 writel_relaxed(old1 | gen, bank->base +
1541 bank->regs->leveldetect1);
1542 }
1543
1544 if (bank->regs->irqstatus_raw0) {
1545 writel_relaxed(old0 | l, bank->base +
1546 bank->regs->leveldetect0);
1547 writel_relaxed(old1 | l, bank->base +
1548 bank->regs->leveldetect1);
1549 }
1550 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1551 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1552 }
1553
1554 bank->workaround_enabled = false;
1555 raw_spin_unlock_irqrestore(&bank->lock, flags);
1556
1557 return 0;
1558 }
1559 #endif /* CONFIG_PM */
1560
1561 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1562 void omap2_gpio_prepare_for_idle(int pwr_mode)
1563 {
1564 struct gpio_bank *bank;
1565
1566 list_for_each_entry(bank, &omap_gpio_list, node) {
1567 if (!BANK_USED(bank) || !bank->loses_context)
1568 continue;
1569
1570 bank->power_mode = pwr_mode;
1571
1572 pm_runtime_put_sync_suspend(bank->chip.parent);
1573 }
1574 }
1575
1576 void omap2_gpio_resume_after_idle(void)
1577 {
1578 struct gpio_bank *bank;
1579
1580 list_for_each_entry(bank, &omap_gpio_list, node) {
1581 if (!BANK_USED(bank) || !bank->loses_context)
1582 continue;
1583
1584 pm_runtime_get_sync(bank->chip.parent);
1585 }
1586 }
1587 #endif
1588
1589 #if defined(CONFIG_PM)
1590 static void omap_gpio_init_context(struct gpio_bank *p)
1591 {
1592 struct omap_gpio_reg_offs *regs = p->regs;
1593 void __iomem *base = p->base;
1594
1595 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1596 p->context.oe = readl_relaxed(base + regs->direction);
1597 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1598 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1599 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1600 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1601 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1602 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1603 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1604
1605 if (regs->set_dataout && p->regs->clr_dataout)
1606 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1607 else
1608 p->context.dataout = readl_relaxed(base + regs->dataout);
1609
1610 p->context_valid = true;
1611 }
1612
1613 static void omap_gpio_restore_context(struct gpio_bank *bank)
1614 {
1615 writel_relaxed(bank->context.wake_en,
1616 bank->base + bank->regs->wkup_en);
1617 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1618 writel_relaxed(bank->context.leveldetect0,
1619 bank->base + bank->regs->leveldetect0);
1620 writel_relaxed(bank->context.leveldetect1,
1621 bank->base + bank->regs->leveldetect1);
1622 writel_relaxed(bank->context.risingdetect,
1623 bank->base + bank->regs->risingdetect);
1624 writel_relaxed(bank->context.fallingdetect,
1625 bank->base + bank->regs->fallingdetect);
1626 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1627 writel_relaxed(bank->context.dataout,
1628 bank->base + bank->regs->set_dataout);
1629 else
1630 writel_relaxed(bank->context.dataout,
1631 bank->base + bank->regs->dataout);
1632 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1633
1634 if (bank->dbck_enable_mask) {
1635 writel_relaxed(bank->context.debounce, bank->base +
1636 bank->regs->debounce);
1637 writel_relaxed(bank->context.debounce_en,
1638 bank->base + bank->regs->debounce_en);
1639 }
1640
1641 writel_relaxed(bank->context.irqenable1,
1642 bank->base + bank->regs->irqenable);
1643 writel_relaxed(bank->context.irqenable2,
1644 bank->base + bank->regs->irqenable2);
1645 }
1646 #endif /* CONFIG_PM */
1647 #else
1648 #define omap_gpio_runtime_suspend NULL
1649 #define omap_gpio_runtime_resume NULL
1650 static inline void omap_gpio_init_context(struct gpio_bank *p) {}
1651 #endif
1652
1653 static const struct dev_pm_ops gpio_pm_ops = {
1654 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1655 NULL)
1656 };
1657
1658 #if defined(CONFIG_OF)
1659 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1660 .revision = OMAP24XX_GPIO_REVISION,
1661 .direction = OMAP24XX_GPIO_OE,
1662 .datain = OMAP24XX_GPIO_DATAIN,
1663 .dataout = OMAP24XX_GPIO_DATAOUT,
1664 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1665 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1666 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1667 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1668 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1669 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1670 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1671 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1672 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1673 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1674 .ctrl = OMAP24XX_GPIO_CTRL,
1675 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1676 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1677 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1678 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1679 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1680 };
1681
1682 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1683 .revision = OMAP4_GPIO_REVISION,
1684 .direction = OMAP4_GPIO_OE,
1685 .datain = OMAP4_GPIO_DATAIN,
1686 .dataout = OMAP4_GPIO_DATAOUT,
1687 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1688 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1689 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1690 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1691 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1692 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1693 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1694 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1695 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1696 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1697 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1698 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1699 .ctrl = OMAP4_GPIO_CTRL,
1700 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1701 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1702 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1703 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1704 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1705 };
1706
1707 static const struct omap_gpio_platform_data omap2_pdata = {
1708 .regs = &omap2_gpio_regs,
1709 .bank_width = 32,
1710 .dbck_flag = false,
1711 };
1712
1713 static const struct omap_gpio_platform_data omap3_pdata = {
1714 .regs = &omap2_gpio_regs,
1715 .bank_width = 32,
1716 .dbck_flag = true,
1717 };
1718
1719 static const struct omap_gpio_platform_data omap4_pdata = {
1720 .regs = &omap4_gpio_regs,
1721 .bank_width = 32,
1722 .dbck_flag = true,
1723 };
1724
1725 static const struct of_device_id omap_gpio_match[] = {
1726 {
1727 .compatible = "ti,omap4-gpio",
1728 .data = &omap4_pdata,
1729 },
1730 {
1731 .compatible = "ti,omap3-gpio",
1732 .data = &omap3_pdata,
1733 },
1734 {
1735 .compatible = "ti,omap2-gpio",
1736 .data = &omap2_pdata,
1737 },
1738 { },
1739 };
1740 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1741 #endif
1742
1743 static struct platform_driver omap_gpio_driver = {
1744 .probe = omap_gpio_probe,
1745 .remove = omap_gpio_remove,
1746 .driver = {
1747 .name = "omap_gpio",
1748 .pm = &gpio_pm_ops,
1749 .of_match_table = of_match_ptr(omap_gpio_match),
1750 },
1751 };
1752
1753 /*
1754 * gpio driver register needs to be done before
1755 * machine_init functions access gpio APIs.
1756 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1757 */
1758 static int __init omap_gpio_drv_reg(void)
1759 {
1760 return platform_driver_register(&omap_gpio_driver);
1761 }
1762 postcore_initcall(omap_gpio_drv_reg);
1763
1764 static void __exit omap_gpio_exit(void)
1765 {
1766 platform_driver_unregister(&omap_gpio_driver);
1767 }
1768 module_exit(omap_gpio_exit);
1769
1770 MODULE_DESCRIPTION("omap gpio driver");
1771 MODULE_ALIAS("platform:gpio-omap");
1772 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support