drivers/gpio/gpio-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Spreadtrum Communications Inc.
   4  * Copyright (C) 2018 Linaro Ltd.
   5  */
   6
   7 #include <linux/bitops.h>
   8 #include <linux/gpio/driver.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/spinlock.h>
  14
  15 /* GPIO registers definition */
  16 #define SPRD_GPIO_DATA          0x0
  17 #define SPRD_GPIO_DMSK          0x4
  18 #define SPRD_GPIO_DIR           0x8
  19 #define SPRD_GPIO_IS            0xc
  20 #define SPRD_GPIO_IBE           0x10
  21 #define SPRD_GPIO_IEV           0x14
  22 #define SPRD_GPIO_IE            0x18
  23 #define SPRD_GPIO_RIS           0x1c
  24 #define SPRD_GPIO_MIS           0x20
  25 #define SPRD_GPIO_IC            0x24
  26 #define SPRD_GPIO_INEN          0x28
  27
  28 /* We have 16 banks GPIOs and each bank contain 16 GPIOs */
  29 #define SPRD_GPIO_BANK_NR       16
  30 #define SPRD_GPIO_NR            256
  31 #define SPRD_GPIO_BANK_SIZE     0x80
  32 #define SPRD_GPIO_BANK_MASK     GENMASK(15, 0)
  33 #define SPRD_GPIO_BIT(x)        ((x) & (SPRD_GPIO_BANK_NR - 1))
  34
  35 struct sprd_gpio {
  36         struct gpio_chip chip;
  37         void __iomem *base;
  38         spinlock_t lock;
  39         int irq;
  40 };
  41
  42 static inline void __iomem *sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio,
  43                                                 unsigned int bank)
  44 {
  45         return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;
  46 }
  47
  48 static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset,
  49                              u16 reg, int val)
  50 {
  51         struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
  52         void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
  53                                                  offset / SPRD_GPIO_BANK_NR);
  54         unsigned long flags;
  55         u32 tmp;
  56
  57         spin_lock_irqsave(&sprd_gpio->lock, flags);
  58         tmp = readl_relaxed(base + reg);
  59
  60         if (val)
  61                 tmp |= BIT(SPRD_GPIO_BIT(offset));
  62         else
  63                 tmp &= ~BIT(SPRD_GPIO_BIT(offset));
  64
  65         writel_relaxed(tmp, base + reg);
  66         spin_unlock_irqrestore(&sprd_gpio->lock, flags);
  67 }
  68
  69 static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
  70 {
  71         struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
  72         void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
  73                                                  offset / SPRD_GPIO_BANK_NR);
  74
  75         return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset)));
  76 }
  77
  78 static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset)
  79 {
  80         sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1);
  81         return 0;
  82 }
  83
  84 static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset)
  85 {
  86         sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0);
  87 }
  88
  89 static int sprd_gpio_direction_input(struct gpio_chip *chip,
  90                                      unsigned int offset)
  91 {
  92         sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0);
  93         sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1);
  94         return 0;
  95 }
  96
  97 static int sprd_gpio_direction_output(struct gpio_chip *chip,
  98                                       unsigned int offset, int value)
  99 {
 100         sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1);
 101         sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0);
 102         sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
 103         return 0;
 104 }
 105
 106 static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset)
 107 {
 108         return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA);
 109 }
 110
 111 static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
 112                           int value)
 113 {
 114         sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
 115 }
 116
 117 static void sprd_gpio_irq_mask(struct irq_data *data)
 118 {
 119         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 120         u32 offset = irqd_to_hwirq(data);
 121
 122         sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0);
 123 }
 124
 125 static void sprd_gpio_irq_ack(struct irq_data *data)
 126 {
 127         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 128         u32 offset = irqd_to_hwirq(data);
 129
 130         sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
 131 }
 132
 133 static void sprd_gpio_irq_unmask(struct irq_data *data)
 134 {
 135         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 136         u32 offset = irqd_to_hwirq(data);
 137
 138         sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1);
 139 }
 140
 141 static int sprd_gpio_irq_set_type(struct irq_data *data,
 142                                   unsigned int flow_type)
 143 {
 144         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 145         u32 offset = irqd_to_hwirq(data);
 146
 147         switch (flow_type) {
 148         case IRQ_TYPE_EDGE_RISING:
 149                 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
 150                 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
 151                 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
 152                 irq_set_handler_locked(data, handle_edge_irq);
 153                 break;
 154         case IRQ_TYPE_EDGE_FALLING:
 155                 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
 156                 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
 157                 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
 158                 irq_set_handler_locked(data, handle_edge_irq);
 159                 break;
 160         case IRQ_TYPE_EDGE_BOTH:
 161                 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
 162                 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1);
 163                 irq_set_handler_locked(data, handle_edge_irq);
 164                 break;
 165         case IRQ_TYPE_LEVEL_HIGH:
 166                 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
 167                 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
 168                 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
 169                 irq_set_handler_locked(data, handle_level_irq);
 170                 break;
 171         case IRQ_TYPE_LEVEL_LOW:
 172                 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
 173                 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
 174                 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
 175                 irq_set_handler_locked(data, handle_level_irq);
 176                 break;
 177         default:
 178                 return -EINVAL;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static void sprd_gpio_irq_handler(struct irq_desc *desc)
 185 {
 186         struct gpio_chip *chip = irq_desc_get_handler_data(desc);
 187         struct irq_chip *ic = irq_desc_get_chip(desc);
 188         struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
 189         u32 bank, n, girq;
 190
 191         chained_irq_enter(ic, desc);
 192
 193         for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
 194                 void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);
 195                 unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
 196                         SPRD_GPIO_BANK_MASK;
 197
 198                 for_each_set_bit(n, &reg, SPRD_GPIO_BANK_NR) {
 199                         girq = irq_find_mapping(chip->irq.domain,
 200                                                 bank * SPRD_GPIO_BANK_NR + n);
 201
 202                         generic_handle_irq(girq);
 203                 }
 204
 205         }
 206         chained_irq_exit(ic, desc);
 207 }
 208
 209 static struct irq_chip sprd_gpio_irqchip = {
 210         .name = "sprd-gpio",
 211         .irq_ack = sprd_gpio_irq_ack,
 212         .irq_mask = sprd_gpio_irq_mask,
 213         .irq_unmask = sprd_gpio_irq_unmask,
 214         .irq_set_type = sprd_gpio_irq_set_type,
 215         .flags = IRQCHIP_SKIP_SET_WAKE,
 216 };
 217
 218 static int sprd_gpio_probe(struct platform_device *pdev)
 219 {
 220         struct gpio_irq_chip *irq;
 221         struct sprd_gpio *sprd_gpio;
 222         struct resource *res;
 223         int ret;
 224
 225         sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL);
 226         if (!sprd_gpio)
 227                 return -ENOMEM;
 228
 229         sprd_gpio->irq = platform_get_irq(pdev, 0);
 230         if (sprd_gpio->irq < 0) {
 231                 dev_err(&pdev->dev, "Failed to get GPIO interrupt.\n");
 232                 return sprd_gpio->irq;
 233         }
 234
 235         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 236         sprd_gpio->base = devm_ioremap_resource(&pdev->dev, res);
 237         if (IS_ERR(sprd_gpio->base))
 238                 return PTR_ERR(sprd_gpio->base);
 239
 240         spin_lock_init(&sprd_gpio->lock);
 241
 242         sprd_gpio->chip.label = dev_name(&pdev->dev);
 243         sprd_gpio->chip.ngpio = SPRD_GPIO_NR;
 244         sprd_gpio->chip.base = -1;
 245         sprd_gpio->chip.parent = &pdev->dev;
 246         sprd_gpio->chip.of_node = pdev->dev.of_node;
 247         sprd_gpio->chip.request = sprd_gpio_request;
 248         sprd_gpio->chip.free = sprd_gpio_free;
 249         sprd_gpio->chip.get = sprd_gpio_get;
 250         sprd_gpio->chip.set = sprd_gpio_set;
 251         sprd_gpio->chip.direction_input = sprd_gpio_direction_input;
 252         sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
 253
 254         irq = &sprd_gpio->chip.irq;
 255         irq->chip = &sprd_gpio_irqchip;
 256         irq->handler = handle_bad_irq;
 257         irq->default_type = IRQ_TYPE_NONE;
 258         irq->parent_handler = sprd_gpio_irq_handler;
 259         irq->parent_handler_data = sprd_gpio;
 260         irq->num_parents = 1;
 261         irq->parents = &sprd_gpio->irq;
 262
 263         ret = devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio);
 264         if (ret < 0) {
 265                 dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret);
 266                 return ret;
 267         }
 268
 269         platform_set_drvdata(pdev, sprd_gpio);
 270         return 0;
 271 }
 272
 273 static const struct of_device_id sprd_gpio_of_match[] = {
 274         { .compatible = "sprd,sc9860-gpio", },
 275         { /* end of list */ }
 276 };
 277 MODULE_DEVICE_TABLE(of, sprd_gpio_of_match);
 278
 279 static struct platform_driver sprd_gpio_driver = {
 280         .probe = sprd_gpio_probe,
 281         .driver = {
 282                 .name = "sprd-gpio",
 283                 .of_match_table = sprd_gpio_of_match,
 284         },
 285 };
 286
 287 module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe);
 288
 289 MODULE_DESCRIPTION("Spreadtrum GPIO driver");
 290 MODULE_LICENSE("GPL v2");