drivers/gpio/gpio-stp-xway.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
   7  *
   8  */
   9
  10 #include <linux/slab.h>
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/types.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/mutex.h>
  16 #include <linux/gpio/driver.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20
  21 #include <lantiq_soc.h>
  22
  23 /*
  24  * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
  25  * peripheral controller used to drive external shift register cascades. At most
  26  * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
  27  * to drive the 2 LSBs of the cascade automatically.
  28  */
  29
  30 /* control register 0 */
  31 #define XWAY_STP_CON0           0x00
  32 /* control register 1 */
  33 #define XWAY_STP_CON1           0x04
  34 /* data register 0 */
  35 #define XWAY_STP_CPU0           0x08
  36 /* data register 1 */
  37 #define XWAY_STP_CPU1           0x0C
  38 /* access register */
  39 #define XWAY_STP_AR             0x10
  40
  41 /* software or hardware update select bit */
  42 #define XWAY_STP_CON_SWU        BIT(31)
  43
  44 /* automatic update rates */
  45 #define XWAY_STP_2HZ            0
  46 #define XWAY_STP_4HZ            BIT(23)
  47 #define XWAY_STP_8HZ            BIT(24)
  48 #define XWAY_STP_10HZ           (BIT(24) | BIT(23))
  49 #define XWAY_STP_SPEED_MASK     (0xf << 23)
  50
  51 /* clock source for automatic update */
  52 #define XWAY_STP_UPD_FPI        BIT(31)
  53 #define XWAY_STP_UPD_MASK       (BIT(31) | BIT(30))
  54
  55 /* let the adsl core drive the 2 LSBs */
  56 #define XWAY_STP_ADSL_SHIFT     24
  57 #define XWAY_STP_ADSL_MASK      0x3
  58
  59 /* 2 groups of 3 bits can be driven by the phys */
  60 #define XWAY_STP_PHY_MASK       0x7
  61 #define XWAY_STP_PHY1_SHIFT     27
  62 #define XWAY_STP_PHY2_SHIFT     15
  63
  64 /* STP has 3 groups of 8 bits */
  65 #define XWAY_STP_GROUP0         BIT(0)
  66 #define XWAY_STP_GROUP1         BIT(1)
  67 #define XWAY_STP_GROUP2         BIT(2)
  68 #define XWAY_STP_GROUP_MASK     (0x7)
  69
  70 /* Edge configuration bits */
  71 #define XWAY_STP_FALLING        BIT(26)
  72 #define XWAY_STP_EDGE_MASK      BIT(26)
  73
  74 #define xway_stp_r32(m, reg)            __raw_readl(m + reg)
  75 #define xway_stp_w32(m, val, reg)       __raw_writel(val, m + reg)
  76 #define xway_stp_w32_mask(m, clear, set, reg) \
  77                 ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \
  78                 m + reg)
  79
  80 struct xway_stp {
  81         struct gpio_chip gc;
  82         void __iomem *virt;
  83         u32 edge;       /* rising or falling edge triggered shift register */
  84         u32 shadow;     /* shadow the shift registers state */
  85         u8 groups;      /* we can drive 1-3 groups of 8bit each */
  86         u8 dsl;         /* the 2 LSBs can be driven by the dsl core */
  87         u8 phy1;        /* 3 bits can be driven by phy1 */
  88         u8 phy2;        /* 3 bits can be driven by phy2 */
  89         u8 reserved;    /* mask out the hw driven bits in gpio_request */
  90 };
  91
  92 /**
  93  * xway_stp_get() - gpio_chip->get - get gpios.
  94  * @gc:     Pointer to gpio_chip device structure.
  95  * @gpio:   GPIO signal number.
  96  *
  97  * Gets the shadow value.
  98  */
  99 static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio)
 100 {
 101         struct xway_stp *chip = gpiochip_get_data(gc);
 102
 103         return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
 104 }
 105
 106 /**
 107  * xway_stp_set() - gpio_chip->set - set gpios.
 108  * @gc:     Pointer to gpio_chip device structure.
 109  * @gpio:   GPIO signal number.
 110  * @val:    Value to be written to specified signal.
 111  *
 112  * Set the shadow value and call ltq_ebu_apply.
 113  */
 114 static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
 115 {
 116         struct xway_stp *chip = gpiochip_get_data(gc);
 117
 118         if (val)
 119                 chip->shadow |= BIT(gpio);
 120         else
 121                 chip->shadow &= ~BIT(gpio);
 122         xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
 123         xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
 124 }
 125
 126 /**
 127  * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
 128  * @gc:     Pointer to gpio_chip device structure.
 129  * @gpio:   GPIO signal number.
 130  * @val:    Value to be written to specified signal.
 131  *
 132  * Same as xway_stp_set, always returns 0.
 133  */
 134 static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
 135 {
 136         xway_stp_set(gc, gpio, val);
 137
 138         return 0;
 139 }
 140
 141 /**
 142  * xway_stp_request() - gpio_chip->request
 143  * @gc:     Pointer to gpio_chip device structure.
 144  * @gpio:   GPIO signal number.
 145  *
 146  * We mask out the HW driven pins
 147  */
 148 static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
 149 {
 150         struct xway_stp *chip = gpiochip_get_data(gc);
 151
 152         if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
 153                 dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
 154                 return -ENODEV;
 155         }
 156
 157         return 0;
 158 }
 159
 160 /**
 161  * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
 162  * @virt: pointer to the remapped register range
 163  */
 164 static int xway_stp_hw_init(struct xway_stp *chip)
 165 {
 166         /* sane defaults */
 167         xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
 168         xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
 169         xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
 170         xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
 171         xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
 172
 173         /* apply edge trigger settings for the shift register */
 174         xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
 175                                 chip->edge, XWAY_STP_CON0);
 176
 177         /* apply led group settings */
 178         xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
 179                                 chip->groups, XWAY_STP_CON1);
 180
 181         /* tell the hardware which pins are controlled by the dsl modem */
 182         xway_stp_w32_mask(chip->virt,
 183                         XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
 184                         chip->dsl << XWAY_STP_ADSL_SHIFT,
 185                         XWAY_STP_CON0);
 186
 187         /* tell the hardware which pins are controlled by the phys */
 188         xway_stp_w32_mask(chip->virt,
 189                         XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
 190                         chip->phy1 << XWAY_STP_PHY1_SHIFT,
 191                         XWAY_STP_CON0);
 192         xway_stp_w32_mask(chip->virt,
 193                         XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
 194                         chip->phy2 << XWAY_STP_PHY2_SHIFT,
 195                         XWAY_STP_CON1);
 196
 197         /* mask out the hw driven bits in gpio_request */
 198         chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;
 199
 200         /*
 201          * if we have pins that are driven by hw, we need to tell the stp what
 202          * clock to use as a timer.
 203          */
 204         if (chip->reserved)
 205                 xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
 206                         XWAY_STP_UPD_FPI, XWAY_STP_CON1);
 207
 208         return 0;
 209 }
 210
 211 static int xway_stp_probe(struct platform_device *pdev)
 212 {
 213         struct resource *res;
 214         u32 shadow, groups, dsl, phy;
 215         struct xway_stp *chip;
 216         struct clk *clk;
 217         int ret = 0;
 218
 219         chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
 220         if (!chip)
 221                 return -ENOMEM;
 222
 223         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 224         chip->virt = devm_ioremap_resource(&pdev->dev, res);
 225         if (IS_ERR(chip->virt))
 226                 return PTR_ERR(chip->virt);
 227
 228         chip->gc.parent = &pdev->dev;
 229         chip->gc.label = "stp-xway";
 230         chip->gc.direction_output = xway_stp_dir_out;
 231         chip->gc.get = xway_stp_get;
 232         chip->gc.set = xway_stp_set;
 233         chip->gc.request = xway_stp_request;
 234         chip->gc.base = -1;
 235         chip->gc.owner = THIS_MODULE;
 236
 237         /* store the shadow value if one was passed by the devicetree */
 238         if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
 239                 chip->shadow = shadow;
 240
 241         /* find out which gpio groups should be enabled */
 242         if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
 243                 chip->groups = groups & XWAY_STP_GROUP_MASK;
 244         else
 245                 chip->groups = XWAY_STP_GROUP0;
 246         chip->gc.ngpio = fls(chip->groups) * 8;
 247
 248         /* find out which gpios are controlled by the dsl core */
 249         if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
 250                 chip->dsl = dsl & XWAY_STP_ADSL_MASK;
 251
 252         /* find out which gpios are controlled by the phys */
 253         if (of_machine_is_compatible("lantiq,ar9") ||
 254                         of_machine_is_compatible("lantiq,gr9") ||
 255                         of_machine_is_compatible("lantiq,vr9")) {
 256                 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
 257                         chip->phy1 = phy & XWAY_STP_PHY_MASK;
 258                 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
 259                         chip->phy2 = phy & XWAY_STP_PHY_MASK;
 260         }
 261
 262         /* check which edge trigger we should use, default to a falling edge */
 263         if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
 264                 chip->edge = XWAY_STP_FALLING;
 265
 266         clk = clk_get(&pdev->dev, NULL);
 267         if (IS_ERR(clk)) {
 268                 dev_err(&pdev->dev, "Failed to get clock\n");
 269                 return PTR_ERR(clk);
 270         }
 271         clk_enable(clk);
 272
 273         ret = xway_stp_hw_init(chip);
 274         if (!ret)
 275                 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
 276
 277         if (!ret)
 278                 dev_info(&pdev->dev, "Init done\n");
 279
 280         return ret;
 281 }
 282
 283 static const struct of_device_id xway_stp_match[] = {
 284         { .compatible = "lantiq,gpio-stp-xway" },
 285         {},
 286 };
 287 MODULE_DEVICE_TABLE(of, xway_stp_match);
 288
 289 static struct platform_driver xway_stp_driver = {
 290         .probe = xway_stp_probe,
 291         .driver = {
 292                 .name = "gpio-stp-xway",
 293                 .of_match_table = xway_stp_match,
 294         },
 295 };
 296
 297 static int __init xway_stp_init(void)
 298 {
 299         return platform_driver_register(&xway_stp_driver);
 300 }
 301
 302 subsys_initcall(xway_stp_init);