drivers/gpio/gpio-xgene-sb.c

   1 /*
   2  * AppliedMicro X-Gene SoC GPIO-Standby Driver
   3  *
   4  * Copyright (c) 2014, Applied Micro Circuits Corporation
   5  * Author:      Tin Huynh <tnhuynh@apm.com>.
   6  *              Y Vo <yvo@apm.com>.
   7  *              Quan Nguyen <qnguyen@apm.com>.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/of_gpio.h>
  27 #include <linux/gpio/driver.h>
  28 #include <linux/acpi.h>
  29
  30 #include "gpiolib.h"
  31
  32 /* Common property names */
  33 #define XGENE_NIRQ_PROPERTY             "apm,nr-irqs"
  34 #define XGENE_NGPIO_PROPERTY            "apm,nr-gpios"
  35 #define XGENE_IRQ_START_PROPERTY        "apm,irq-start"
  36
  37 #define XGENE_DFLT_MAX_NGPIO            22
  38 #define XGENE_DFLT_MAX_NIRQ             6
  39 #define XGENE_DFLT_IRQ_START_PIN        8
  40 #define GPIO_MASK(x)                    (1U << ((x) % 32))
  41
  42 #define MPA_GPIO_INT_LVL                0x0290
  43 #define MPA_GPIO_OE_ADDR                0x029c
  44 #define MPA_GPIO_OUT_ADDR               0x02a0
  45 #define MPA_GPIO_IN_ADDR                0x02a4
  46 #define MPA_GPIO_SEL_LO                 0x0294
  47
  48 #define GPIO_INT_LEVEL_H        0x000001
  49 #define GPIO_INT_LEVEL_L        0x000000
  50
  51 /**
  52  * struct xgene_gpio_sb - GPIO-Standby private data structure.
  53  * @gc:                         memory-mapped GPIO controllers.
  54  * @regs:                       GPIO register base offset
  55  * @irq_domain:                 GPIO interrupt domain
  56  * @irq_start:                  GPIO pin that start support interrupt
  57  * @nirq:                       Number of GPIO pins that supports interrupt
  58  * @parent_irq_base:            Start parent HWIRQ
  59  */
  60 struct xgene_gpio_sb {
  61         struct gpio_chip        gc;
  62         void __iomem            *regs;
  63         struct irq_domain       *irq_domain;
  64         u16                     irq_start;
  65         u16                     nirq;
  66         u16                     parent_irq_base;
  67 };
  68
  69 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
  70 #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
  71
  72 static void xgene_gpio_set_bit(struct gpio_chip *gc,
  73                                 void __iomem *reg, u32 gpio, int val)
  74 {
  75         u32 data;
  76
  77         data = gc->read_reg(reg);
  78         if (val)
  79                 data |= GPIO_MASK(gpio);
  80         else
  81                 data &= ~GPIO_MASK(gpio);
  82         gc->write_reg(reg, data);
  83 }
  84
  85 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
  86 {
  87         struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
  88         int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
  89         int lvl_type = GPIO_INT_LEVEL_H;
  90
  91         switch (type & IRQ_TYPE_SENSE_MASK) {
  92         case IRQ_TYPE_EDGE_RISING:
  93         case IRQ_TYPE_LEVEL_HIGH:
  94                 lvl_type = GPIO_INT_LEVEL_H;
  95                 break;
  96         case IRQ_TYPE_EDGE_FALLING:
  97         case IRQ_TYPE_LEVEL_LOW:
  98                 lvl_type = GPIO_INT_LEVEL_L;
  99                 break;
 100         default:
 101                 break;
 102         }
 103
 104         xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
 105                         gpio * 2, 1);
 106         xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
 107                         d->hwirq, lvl_type);
 108
 109         /* Propagate IRQ type setting to parent */
 110         if (type & IRQ_TYPE_EDGE_BOTH)
 111                 return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
 112         else
 113                 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
 114 }
 115
 116 static struct irq_chip xgene_gpio_sb_irq_chip = {
 117         .name           = "sbgpio",
 118         .irq_eoi        = irq_chip_eoi_parent,
 119         .irq_mask       = irq_chip_mask_parent,
 120         .irq_unmask     = irq_chip_unmask_parent,
 121         .irq_set_type   = xgene_gpio_sb_irq_set_type,
 122 };
 123
 124 static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
 125 {
 126         struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
 127         struct irq_fwspec fwspec;
 128
 129         if ((gpio < priv->irq_start) ||
 130                         (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
 131                 return -ENXIO;
 132
 133         fwspec.fwnode = gc->parent->fwnode;
 134         fwspec.param_count = 2;
 135         fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
 136         fwspec.param[1] = IRQ_TYPE_NONE;
 137         return irq_create_fwspec_mapping(&fwspec);
 138 }
 139
 140 static int xgene_gpio_sb_domain_activate(struct irq_domain *d,
 141                                          struct irq_data *irq_data,
 142                                          bool reserve)
 143 {
 144         struct xgene_gpio_sb *priv = d->host_data;
 145         u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
 146         int ret;
 147
 148         ret = gpiochip_lock_as_irq(&priv->gc, gpio);
 149         if (ret) {
 150                 dev_err(priv->gc.parent,
 151                 "Unable to configure XGene GPIO standby pin %d as IRQ\n",
 152                                 gpio);
 153                 return ret;
 154         }
 155
 156         xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
 157                         gpio * 2, 1);
 158         return 0;
 159 }
 160
 161 static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
 162                 struct irq_data *irq_data)
 163 {
 164         struct xgene_gpio_sb *priv = d->host_data;
 165         u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
 166
 167         gpiochip_unlock_as_irq(&priv->gc, gpio);
 168         xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
 169                         gpio * 2, 0);
 170 }
 171
 172 static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
 173                 struct irq_fwspec *fwspec,
 174                 unsigned long *hwirq,
 175                 unsigned int *type)
 176 {
 177         struct xgene_gpio_sb *priv = d->host_data;
 178
 179         if ((fwspec->param_count != 2) ||
 180                 (fwspec->param[0] >= priv->nirq))
 181                 return -EINVAL;
 182         *hwirq = fwspec->param[0];
 183         *type = fwspec->param[1];
 184         return 0;
 185 }
 186
 187 static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
 188                                         unsigned int virq,
 189                                         unsigned int nr_irqs, void *data)
 190 {
 191         struct irq_fwspec *fwspec = data;
 192         struct irq_fwspec parent_fwspec;
 193         struct xgene_gpio_sb *priv = domain->host_data;
 194         irq_hw_number_t hwirq;
 195         unsigned int i;
 196
 197         hwirq = fwspec->param[0];
 198         for (i = 0; i < nr_irqs; i++)
 199                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 200                                 &xgene_gpio_sb_irq_chip, priv);
 201
 202         parent_fwspec.fwnode = domain->parent->fwnode;
 203         if (is_of_node(parent_fwspec.fwnode)) {
 204                 parent_fwspec.param_count = 3;
 205                 parent_fwspec.param[0] = 0;/* SPI */
 206                 /* Skip SGIs and PPIs*/
 207                 parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
 208                 parent_fwspec.param[2] = fwspec->param[1];
 209         } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
 210                 parent_fwspec.param_count = 2;
 211                 parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
 212                 parent_fwspec.param[1] = fwspec->param[1];
 213         } else
 214                 return -EINVAL;
 215
 216         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
 217                         &parent_fwspec);
 218 }
 219
 220 static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
 221         .translate      = xgene_gpio_sb_domain_translate,
 222         .alloc          = xgene_gpio_sb_domain_alloc,
 223         .free           = irq_domain_free_irqs_common,
 224         .activate       = xgene_gpio_sb_domain_activate,
 225         .deactivate     = xgene_gpio_sb_domain_deactivate,
 226 };
 227
 228 static int xgene_gpio_sb_probe(struct platform_device *pdev)
 229 {
 230         struct xgene_gpio_sb *priv;
 231         int ret;
 232         struct resource *res;
 233         void __iomem *regs;
 234         struct irq_domain *parent_domain = NULL;
 235         u32 val32;
 236
 237         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 238         if (!priv)
 239                 return -ENOMEM;
 240
 241         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 242         regs = devm_ioremap_resource(&pdev->dev, res);
 243         if (IS_ERR(regs))
 244                 return PTR_ERR(regs);
 245
 246         priv->regs = regs;
 247
 248         ret = platform_get_irq(pdev, 0);
 249         if (ret > 0) {
 250                 priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
 251                 parent_domain = irq_get_irq_data(ret)->domain;
 252         }
 253         if (!parent_domain) {
 254                 dev_err(&pdev->dev, "unable to obtain parent domain\n");
 255                 return -ENODEV;
 256         }
 257
 258         ret = bgpio_init(&priv->gc, &pdev->dev, 4,
 259                         regs + MPA_GPIO_IN_ADDR,
 260                         regs + MPA_GPIO_OUT_ADDR, NULL,
 261                         regs + MPA_GPIO_OE_ADDR, NULL, 0);
 262         if (ret)
 263                 return ret;
 264
 265         priv->gc.to_irq = xgene_gpio_sb_to_irq;
 266
 267         /* Retrieve start irq pin, use default if property not found */
 268         priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
 269         if (!device_property_read_u32(&pdev->dev,
 270                                         XGENE_IRQ_START_PROPERTY, &val32))
 271                 priv->irq_start = val32;
 272
 273         /* Retrieve number irqs, use default if property not found */
 274         priv->nirq = XGENE_DFLT_MAX_NIRQ;
 275         if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
 276                 priv->nirq = val32;
 277
 278         /* Retrieve number gpio, use default if property not found */
 279         priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
 280         if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
 281                 priv->gc.ngpio = val32;
 282
 283         dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
 284                         priv->gc.ngpio, priv->nirq, priv->irq_start);
 285
 286         platform_set_drvdata(pdev, priv);
 287
 288         priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
 289                                         0, priv->nirq, pdev->dev.fwnode,
 290                                         &xgene_gpio_sb_domain_ops, priv);
 291         if (!priv->irq_domain)
 292                 return -ENODEV;
 293
 294         priv->gc.irq.domain = priv->irq_domain;
 295
 296         ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
 297         if (ret) {
 298                 dev_err(&pdev->dev,
 299                         "failed to register X-Gene GPIO Standby driver\n");
 300                 irq_domain_remove(priv->irq_domain);
 301                 return ret;
 302         }
 303
 304         dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
 305
 306         if (priv->nirq > 0) {
 307                 /* Register interrupt handlers for gpio signaled acpi events */
 308                 acpi_gpiochip_request_interrupts(&priv->gc);
 309         }
 310
 311         return ret;
 312 }
 313
 314 static int xgene_gpio_sb_remove(struct platform_device *pdev)
 315 {
 316         struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
 317
 318         if (priv->nirq > 0) {
 319                 acpi_gpiochip_free_interrupts(&priv->gc);
 320         }
 321
 322         irq_domain_remove(priv->irq_domain);
 323
 324         return 0;
 325 }
 326
 327 static const struct of_device_id xgene_gpio_sb_of_match[] = {
 328         {.compatible = "apm,xgene-gpio-sb", },
 329         {},
 330 };
 331 MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
 332
 333 #ifdef CONFIG_ACPI
 334 static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
 335         {"APMC0D15", 0},
 336         {},
 337 };
 338 MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
 339 #endif
 340
 341 static struct platform_driver xgene_gpio_sb_driver = {
 342         .driver = {
 343                    .name = "xgene-gpio-sb",
 344                    .of_match_table = xgene_gpio_sb_of_match,
 345                    .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
 346                    },
 347         .probe = xgene_gpio_sb_probe,
 348         .remove = xgene_gpio_sb_remove,
 349 };
 350 module_platform_driver(xgene_gpio_sb_driver);
 351
 352 MODULE_AUTHOR("AppliedMicro");
 353 MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
 354 MODULE_LICENSE("GPL");