drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v6_1.h"
  26
  27 #include "nbio/nbio_6_1_default.h"
  28 #include "nbio/nbio_6_1_offset.h"
  29 #include "nbio/nbio_6_1_sh_mask.h"
  30 #include "vega10_enum.h"
  31
  32 #define smnCPM_CONTROL                                                                                  0x11180460
  33 #define smnPCIE_CNTL2                                                                                   0x11180070
  34 #define smnPCIE_CONFIG_CNTL                                                                             0x11180044
  35
  36 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
  37 {
  38         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  39
  40         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  41         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  42
  43         return tmp;
  44 }
  45
  46 static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
  47 {
  48         if (enable)
  49                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  50                              BIF_FB_EN__FB_READ_EN_MASK |
  51                              BIF_FB_EN__FB_WRITE_EN_MASK);
  52         else
  53                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  54 }
  55
  56 static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
  57                                 struct amdgpu_ring *ring)
  58 {
  59         if (!ring || !ring->funcs->emit_wreg)
  60                 WREG32_SOC15_NO_KIQ(NBIO, 0,
  61                                     mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
  62                                     0);
  63         else
  64                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  65                         NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
  66 }
  67
  68 static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
  69 {
  70         return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
  71 }
  72
  73 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  74                                   bool use_doorbell, int doorbell_index)
  75 {
  76         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  77                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  78
  79         u32 doorbell_range = RREG32(reg);
  80
  81         if (use_doorbell) {
  82                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
  83                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
  84         } else
  85                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
  86
  87         WREG32(reg, doorbell_range);
  88
  89 }
  90
  91 static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
  92                                                bool enable)
  93 {
  94         WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  95 }
  96
  97 static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
  98                                                         bool enable)
  99 {
 100         u32 tmp = 0;
 101
 102         if (enable) {
 103                 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
 104                       REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 105                       REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 106
 107                 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
 108                              lower_32_bits(adev->doorbell.base));
 109                 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 110                              upper_32_bits(adev->doorbell.base));
 111         }
 112
 113         WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
 114 }
 115
 116
 117 static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
 118                                         bool use_doorbell, int doorbell_index)
 119 {
 120         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 121
 122         if (use_doorbell) {
 123                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 124                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 125         } else
 126                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 127
 128         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 129 }
 130
 131 static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
 132 {
 133         u32 interrupt_cntl;
 134
 135         /* setup interrupt control */
 136         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
 137         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 138         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 139          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 140          */
 141         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 142         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 143         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 144         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 145 }
 146
 147 static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 148                                                        bool enable)
 149 {
 150         uint32_t def, data;
 151
 152         def = data = RREG32_PCIE(smnCPM_CONTROL);
 153         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
 154                 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 155                          CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 156                          CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
 157                          CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 158                          CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 159                          CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 160                          CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 161         } else {
 162                 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
 163                           CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
 164                           CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
 165                           CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
 166                           CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
 167                           CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
 168                           CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
 169         }
 170
 171         if (def != data)
 172                 WREG32_PCIE(smnCPM_CONTROL, data);
 173 }
 174
 175 static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 176                                                       bool enable)
 177 {
 178         uint32_t def, data;
 179
 180         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 181         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 182                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 183                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 184                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 185         } else {
 186                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 187                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 188                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 189         }
 190
 191         if (def != data)
 192                 WREG32_PCIE(smnPCIE_CNTL2, data);
 193 }
 194
 195 static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
 196                                             u32 *flags)
 197 {
 198         int data;
 199
 200         /* AMD_CG_SUPPORT_BIF_MGCG */
 201         data = RREG32_PCIE(smnCPM_CONTROL);
 202         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 203                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 204
 205         /* AMD_CG_SUPPORT_BIF_LS */
 206         data = RREG32_PCIE(smnPCIE_CNTL2);
 207         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 208                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 209 }
 210
 211 static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 212 {
 213         return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
 214 }
 215
 216 static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 217 {
 218         return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
 219 }
 220
 221 static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
 222 {
 223         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 224 }
 225
 226 static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
 227 {
 228         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 229 }
 230
 231 static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
 232         .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
 233         .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
 234         .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
 235         .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
 236         .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
 237         .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
 238         .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
 239         .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
 240         .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
 241         .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
 242         .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 243         .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
 244 };
 245
 246 static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
 247 {
 248         uint32_t reg;
 249
 250         reg = RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER);
 251         if (reg & 1)
 252                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 253
 254         if (reg & 0x80000000)
 255                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 256
 257         if (!reg) {
 258                 if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 259                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 260         }
 261 }
 262
 263 static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
 264 {
 265         uint32_t def, data;
 266
 267         def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
 268         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
 269         data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 270
 271         if (def != data)
 272                 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
 273 }
 274
 275 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
 276         .hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
 277         .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
 278         .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
 279         .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
 280         .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
 281         .get_rev_id = nbio_v6_1_get_rev_id,
 282         .mc_access_enable = nbio_v6_1_mc_access_enable,
 283         .hdp_flush = nbio_v6_1_hdp_flush,
 284         .get_memsize = nbio_v6_1_get_memsize,
 285         .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
 286         .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
 287         .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
 288         .ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
 289         .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
 290         .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
 291         .get_clockgating_state = nbio_v6_1_get_clockgating_state,
 292         .ih_control = nbio_v6_1_ih_control,
 293         .init_registers = nbio_v6_1_init_registers,
 294         .detect_hw_virt = nbio_v6_1_detect_hw_virt,
 295 };