drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef _PSP_TEE_GFX_IF_H_
  25 #define _PSP_TEE_GFX_IF_H_
  26
  27 #define PSP_GFX_CMD_BUF_VERSION     0x00000001
  28
  29 #define GFX_CMD_STATUS_MASK         0x0000FFFF
  30 #define GFX_CMD_ID_MASK             0x000F0000
  31 #define GFX_CMD_RESERVED_MASK       0x7FF00000
  32 #define GFX_CMD_RESPONSE_MASK       0x80000000
  33
  34 /* TEE Gfx Command IDs for the register interface.
  35 *  Command ID must be between 0x00010000 and 0x000F0000.
  36 */
  37 enum psp_gfx_crtl_cmd_id
  38 {
  39     GFX_CTRL_CMD_ID_INIT_RBI_RING   = 0x00010000,   /* initialize RBI ring */
  40     GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000,   /* initialize GPCOM ring */
  41     GFX_CTRL_CMD_ID_DESTROY_RINGS   = 0x00030000,   /* destroy rings */
  42     GFX_CTRL_CMD_ID_CAN_INIT_RINGS  = 0x00040000,   /* is it allowed to initialized the rings */
  43     GFX_CTRL_CMD_ID_ENABLE_INT      = 0x00050000,   /* enable PSP-to-Gfx interrupt */
  44     GFX_CTRL_CMD_ID_DISABLE_INT     = 0x00060000,   /* disable PSP-to-Gfx interrupt */
  45     GFX_CTRL_CMD_ID_MODE1_RST       = 0x00070000,   /* trigger the Mode 1 reset */
  46
  47     GFX_CTRL_CMD_ID_MAX             = 0x000F0000,   /* max command ID */
  48 };
  49
  50
  51 /*-----------------------------------------------------------------------------
  52     NOTE:   All physical addresses used in this interface are actually
  53             GPU Virtual Addresses.
  54 */
  55
  56
  57 /* Control registers of the TEE Gfx interface. These are located in
  58 *  SRBM-to-PSP mailbox registers (total 8 registers).
  59 */
  60 struct psp_gfx_ctrl
  61 {
  62     volatile uint32_t   cmd_resp;         /* +0   Command/Response register for Gfx commands */
  63     volatile uint32_t   rbi_wptr;         /* +4   Write pointer (index) of RBI ring */
  64     volatile uint32_t   rbi_rptr;         /* +8   Read pointer (index) of RBI ring */
  65     volatile uint32_t   gpcom_wptr;       /* +12  Write pointer (index) of GPCOM ring */
  66     volatile uint32_t   gpcom_rptr;       /* +16  Read pointer (index) of GPCOM ring */
  67     volatile uint32_t   ring_addr_lo;     /* +20  bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
  68     volatile uint32_t   ring_addr_hi;     /* +24  bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
  69     volatile uint32_t   ring_buf_size;    /* +28  Ring buffer size (in bytes) */
  70
  71 };
  72
  73
  74 /* Response flag is set in the command when command is completed by PSP.
  75 *  Used in the GFX_CTRL.CmdResp.
  76 *  When PSP GFX I/F is initialized, the flag is set.
  77 */
  78 #define GFX_FLAG_RESPONSE               0x80000000
  79
  80
  81 /* TEE Gfx Command IDs for the ring buffer interface. */
  82 enum psp_gfx_cmd_id
  83 {
  84     GFX_CMD_ID_LOAD_TA      = 0x00000001,   /* load TA */
  85     GFX_CMD_ID_UNLOAD_TA    = 0x00000002,   /* unload TA */
  86     GFX_CMD_ID_INVOKE_CMD   = 0x00000003,   /* send command to TA */
  87     GFX_CMD_ID_LOAD_ASD     = 0x00000004,   /* load ASD Driver */
  88     GFX_CMD_ID_SETUP_TMR    = 0x00000005,   /* setup TMR region */
  89     GFX_CMD_ID_LOAD_IP_FW   = 0x00000006,   /* load HW IP FW */
  90     GFX_CMD_ID_DESTROY_TMR  = 0x00000007,   /* destroy TMR region */
  91     GFX_CMD_ID_SAVE_RESTORE = 0x00000008,   /* save/restore HW IP FW */
  92
  93 };
  94
  95
  96 /* Command to load Trusted Application binary into PSP OS. */
  97 struct psp_gfx_cmd_load_ta
  98 {
  99     uint32_t        app_phy_addr_lo;        /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
 100     uint32_t        app_phy_addr_hi;        /* bits [63:32] of the GPU Virtual address of the TA binary */
 101     uint32_t        app_len;                /* length of the TA binary in bytes */
 102     uint32_t        cmd_buf_phy_addr_lo;    /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
 103     uint32_t        cmd_buf_phy_addr_hi;    /* bits [63:32] of the GPU Virtual address of CMD buffer */
 104     uint32_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
 105
 106     /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
 107     *       for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
 108     *       of using global persistent buffer.
 109     */
 110 };
 111
 112
 113 /* Command to Unload Trusted Application binary from PSP OS. */
 114 struct psp_gfx_cmd_unload_ta
 115 {
 116     uint32_t        session_id;          /* Session ID of the loaded TA to be unloaded */
 117
 118 };
 119
 120
 121 /* Shared buffers for InvokeCommand.
 122 */
 123 struct psp_gfx_buf_desc
 124 {
 125     uint32_t        buf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
 126     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of the buffer */
 127     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
 128
 129 };
 130
 131 /* Max number of descriptors for one shared buffer (in how many different
 132 *  physical locations one shared buffer can be stored). If buffer is too much
 133 *  fragmented, error will be returned.
 134 */
 135 #define GFX_BUF_MAX_DESC        64
 136
 137 struct psp_gfx_buf_list
 138 {
 139     uint32_t                num_desc;                    /* number of buffer descriptors in the list */
 140     uint32_t                total_size;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
 141     struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC];  /* list of buffer descriptors */
 142
 143     /* total 776 bytes */
 144 };
 145
 146 /* Command to execute InvokeCommand entry point of the TA. */
 147 struct psp_gfx_cmd_invoke_cmd
 148 {
 149     uint32_t                session_id;           /* Session ID of the TA to be executed */
 150     uint32_t                ta_cmd_id;            /* Command ID to be sent to TA */
 151     struct psp_gfx_buf_list buf;                  /* one indirect buffer (scatter/gather list) */
 152
 153 };
 154
 155
 156 /* Command to setup TMR region. */
 157 struct psp_gfx_cmd_setup_tmr
 158 {
 159     uint32_t        buf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
 160     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of TMR buffer */
 161     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
 162
 163 };
 164
 165
 166 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
 167 enum psp_gfx_fw_type
 168 {
 169     GFX_FW_TYPE_NONE        = 0,
 170     GFX_FW_TYPE_CP_ME       = 1,
 171     GFX_FW_TYPE_CP_PFP      = 2,
 172     GFX_FW_TYPE_CP_CE       = 3,
 173     GFX_FW_TYPE_CP_MEC      = 4,
 174     GFX_FW_TYPE_CP_MEC_ME1  = 5,
 175     GFX_FW_TYPE_CP_MEC_ME2  = 6,
 176     GFX_FW_TYPE_RLC_V       = 7,
 177     GFX_FW_TYPE_RLC_G       = 8,
 178     GFX_FW_TYPE_SDMA0       = 9,
 179     GFX_FW_TYPE_SDMA1       = 10,
 180     GFX_FW_TYPE_DMCU_ERAM   = 11,
 181     GFX_FW_TYPE_DMCU_ISR    = 12,
 182     GFX_FW_TYPE_VCN         = 13,
 183     GFX_FW_TYPE_UVD         = 14,
 184     GFX_FW_TYPE_VCE         = 15,
 185     GFX_FW_TYPE_ISP         = 16,
 186     GFX_FW_TYPE_ACP         = 17,
 187     GFX_FW_TYPE_SMU         = 18,
 188     GFX_FW_TYPE_MMSCH       = 19,
 189     GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM        = 20,
 190     GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM        = 21,
 191     GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL           = 22,
 192     GFX_FW_TYPE_MAX         = 23
 193 };
 194
 195 /* Command to load HW IP FW. */
 196 struct psp_gfx_cmd_load_ip_fw
 197 {
 198     uint32_t                fw_phy_addr_lo;    /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
 199     uint32_t                fw_phy_addr_hi;    /* bits [63:32] of GPU Virtual address of FW location */
 200     uint32_t                fw_size;           /* FW buffer size in bytes */
 201     enum psp_gfx_fw_type    fw_type;           /* FW type */
 202
 203 };
 204
 205 /* Command to save/restore HW IP FW. */
 206 struct psp_gfx_cmd_save_restore_ip_fw
 207 {
 208     uint32_t                save_fw;              /* if set, command is used for saving fw otherwise for resetoring*/
 209     uint32_t                save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
 210     uint32_t                save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
 211     uint32_t                buf_size;             /* Size of the save/restore buffer in bytes */
 212     enum psp_gfx_fw_type    fw_type;              /* FW type */
 213 };
 214
 215 /* All GFX ring buffer commands. */
 216 union psp_gfx_commands
 217 {
 218     struct psp_gfx_cmd_load_ta          cmd_load_ta;
 219     struct psp_gfx_cmd_unload_ta        cmd_unload_ta;
 220     struct psp_gfx_cmd_invoke_cmd       cmd_invoke_cmd;
 221     struct psp_gfx_cmd_setup_tmr        cmd_setup_tmr;
 222     struct psp_gfx_cmd_load_ip_fw       cmd_load_ip_fw;
 223     struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
 224 };
 225
 226
 227 /* Structure of GFX Response buffer.
 228 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
 229 * it is separate buffer.
 230 */
 231 struct psp_gfx_resp
 232 {
 233     uint32_t    status;             /* +0  status of command execution */
 234     uint32_t    session_id;         /* +4  session ID in response to LoadTa command */
 235     uint32_t    fw_addr_lo;         /* +8  bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
 236     uint32_t    fw_addr_hi;         /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
 237
 238     uint32_t    reserved[4];
 239
 240     /* total 32 bytes */
 241 };
 242
 243 /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
 244 *  and psp_gfx_rb_frame.cmd_buf_addr_lo.
 245 */
 246 struct psp_gfx_cmd_resp
 247 {
 248     uint32_t        buf_size;           /* +0  total size of the buffer in bytes */
 249     uint32_t        buf_version;        /* +4  version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
 250     uint32_t        cmd_id;             /* +8  command ID */
 251
 252     /* These fields are used for RBI only. They are all 0 in GPCOM commands
 253     */
 254     uint32_t        resp_buf_addr_lo;   /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
 255     uint32_t        resp_buf_addr_hi;   /* +16 bits [63:32] of GPU Virtual address of response buffer */
 256     uint32_t        resp_offset;        /* +20 offset within response buffer */
 257     uint32_t        resp_buf_size;      /* +24 total size of the response buffer in bytes */
 258
 259     union psp_gfx_commands  cmd;        /* +28 command specific structures */
 260
 261     uint8_t         reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
 262
 263     /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
 264     *        is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
 265     */
 266     struct psp_gfx_resp     resp;       /* +864 response */
 267
 268     uint8_t         reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
 269
 270     /* total size 1024 bytes */
 271 };
 272
 273
 274 #define FRAME_TYPE_DESTROY          1   /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
 275
 276 /* Structure of the Ring Buffer Frame */
 277 struct psp_gfx_rb_frame
 278 {
 279     uint32_t    cmd_buf_addr_lo;    /* +0  bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
 280     uint32_t    cmd_buf_addr_hi;    /* +4  bits [63:32] of GPU Virtual address of command buffer */
 281     uint32_t    cmd_buf_size;       /* +8  command buffer size in bytes */
 282     uint32_t    fence_addr_lo;      /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
 283     uint32_t    fence_addr_hi;      /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
 284     uint32_t    fence_value;        /* +20 Fence value */
 285     uint32_t    sid_lo;             /* +24 bits [31:0] of SID value (used only for RBI frames) */
 286     uint32_t    sid_hi;             /* +28 bits [63:32] of SID value (used only for RBI frames) */
 287     uint8_t     vmid;               /* +32 VMID value used for mapping of all addresses for this frame */
 288     uint8_t     frame_type;         /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
 289     uint8_t     reserved1[2];       /* +34 reserved, must be 0 */
 290     uint32_t    reserved2[7];       /* +36 reserved, must be 0 */
 291                 /* total 64 bytes */
 292 };
 293
 294 #endif /* _PSP_TEE_GFX_IF_H_ */