drivers/gpu/drm/amd/amdgpu/si_ih.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_ih.h"
  26 #include "sid.h"
  27 #include "si_ih.h"
  28
  29 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
  30
  31 static void si_ih_enable_interrupts(struct amdgpu_device *adev)
  32 {
  33         u32 ih_cntl = RREG32(IH_CNTL);
  34         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  35
  36         ih_cntl |= ENABLE_INTR;
  37         ih_rb_cntl |= IH_RB_ENABLE;
  38         WREG32(IH_CNTL, ih_cntl);
  39         WREG32(IH_RB_CNTL, ih_rb_cntl);
  40         adev->irq.ih.enabled = true;
  41 }
  42
  43 static void si_ih_disable_interrupts(struct amdgpu_device *adev)
  44 {
  45         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
  46         u32 ih_cntl = RREG32(IH_CNTL);
  47
  48         ih_rb_cntl &= ~IH_RB_ENABLE;
  49         ih_cntl &= ~ENABLE_INTR;
  50         WREG32(IH_RB_CNTL, ih_rb_cntl);
  51         WREG32(IH_CNTL, ih_cntl);
  52         WREG32(IH_RB_RPTR, 0);
  53         WREG32(IH_RB_WPTR, 0);
  54         adev->irq.ih.enabled = false;
  55         adev->irq.ih.rptr = 0;
  56 }
  57
  58 static int si_ih_irq_init(struct amdgpu_device *adev)
  59 {
  60         int rb_bufsz;
  61         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
  62         u64 wptr_off;
  63
  64         si_ih_disable_interrupts(adev);
  65         /* set dummy read address to dummy page address */
  66         WREG32(INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
  67         interrupt_cntl = RREG32(INTERRUPT_CNTL);
  68         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
  69         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
  70         WREG32(INTERRUPT_CNTL, interrupt_cntl);
  71
  72         WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
  73         rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
  74
  75         ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE |
  76                      IH_WPTR_OVERFLOW_CLEAR |
  77                      (rb_bufsz << 1) |
  78                      IH_WPTR_WRITEBACK_ENABLE;
  79
  80         wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
  81         WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
  82         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
  83         WREG32(IH_RB_CNTL, ih_rb_cntl);
  84         WREG32(IH_RB_RPTR, 0);
  85         WREG32(IH_RB_WPTR, 0);
  86
  87         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
  88         if (adev->irq.msi_enabled)
  89                 ih_cntl |= RPTR_REARM;
  90         WREG32(IH_CNTL, ih_cntl);
  91
  92         pci_set_master(adev->pdev);
  93         si_ih_enable_interrupts(adev);
  94
  95         return 0;
  96 }
  97
  98 static void si_ih_irq_disable(struct amdgpu_device *adev)
  99 {
 100         si_ih_disable_interrupts(adev);
 101         mdelay(1);
 102 }
 103
 104 static u32 si_ih_get_wptr(struct amdgpu_device *adev)
 105 {
 106         u32 wptr, tmp;
 107
 108         wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
 109
 110         if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
 111                 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
 112                 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
 113                         wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
 114                 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
 115                 tmp = RREG32(IH_RB_CNTL);
 116                 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
 117                 WREG32(IH_RB_CNTL, tmp);
 118         }
 119         return (wptr & adev->irq.ih.ptr_mask);
 120 }
 121
 122 /**
 123  * si_ih_prescreen_iv - prescreen an interrupt vector
 124  *
 125  * @adev: amdgpu_device pointer
 126  *
 127  * Returns true if the interrupt vector should be further processed.
 128  */
 129 static bool si_ih_prescreen_iv(struct amdgpu_device *adev)
 130 {
 131         /* Process all interrupts */
 132         return true;
 133 }
 134
 135 static void si_ih_decode_iv(struct amdgpu_device *adev,
 136                              struct amdgpu_iv_entry *entry)
 137 {
 138         u32 ring_index = adev->irq.ih.rptr >> 2;
 139         uint32_t dw[4];
 140
 141         dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
 142         dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
 143         dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
 144         dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
 145
 146         entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
 147         entry->src_id = dw[0] & 0xff;
 148         entry->src_data[0] = dw[1] & 0xfffffff;
 149         entry->ring_id = dw[2] & 0xff;
 150         entry->vmid = (dw[2] >> 8) & 0xff;
 151
 152         adev->irq.ih.rptr += 16;
 153 }
 154
 155 static void si_ih_set_rptr(struct amdgpu_device *adev)
 156 {
 157         WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
 158 }
 159
 160 static int si_ih_early_init(void *handle)
 161 {
 162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 163
 164         si_ih_set_interrupt_funcs(adev);
 165
 166         return 0;
 167 }
 168
 169 static int si_ih_sw_init(void *handle)
 170 {
 171         int r;
 172         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 173
 174         r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
 175         if (r)
 176                 return r;
 177
 178         return amdgpu_irq_init(adev);
 179 }
 180
 181 static int si_ih_sw_fini(void *handle)
 182 {
 183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 184
 185         amdgpu_irq_fini(adev);
 186         amdgpu_ih_ring_fini(adev);
 187
 188         return 0;
 189 }
 190
 191 static int si_ih_hw_init(void *handle)
 192 {
 193         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 194
 195         return si_ih_irq_init(adev);
 196 }
 197
 198 static int si_ih_hw_fini(void *handle)
 199 {
 200         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 201
 202         si_ih_irq_disable(adev);
 203
 204         return 0;
 205 }
 206
 207 static int si_ih_suspend(void *handle)
 208 {
 209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 210
 211         return si_ih_hw_fini(adev);
 212 }
 213
 214 static int si_ih_resume(void *handle)
 215 {
 216         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 217
 218         return si_ih_hw_init(adev);
 219 }
 220
 221 static bool si_ih_is_idle(void *handle)
 222 {
 223         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 224         u32 tmp = RREG32(SRBM_STATUS);
 225
 226         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 227                 return false;
 228
 229         return true;
 230 }
 231
 232 static int si_ih_wait_for_idle(void *handle)
 233 {
 234         unsigned i;
 235         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 236
 237         for (i = 0; i < adev->usec_timeout; i++) {
 238                 if (si_ih_is_idle(handle))
 239                         return 0;
 240                 udelay(1);
 241         }
 242         return -ETIMEDOUT;
 243 }
 244
 245 static int si_ih_soft_reset(void *handle)
 246 {
 247         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 248
 249         u32 srbm_soft_reset = 0;
 250         u32 tmp = RREG32(SRBM_STATUS);
 251
 252         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 253                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
 254
 255         if (srbm_soft_reset) {
 256                 tmp = RREG32(SRBM_SOFT_RESET);
 257                 tmp |= srbm_soft_reset;
 258                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 259                 WREG32(SRBM_SOFT_RESET, tmp);
 260                 tmp = RREG32(SRBM_SOFT_RESET);
 261
 262                 udelay(50);
 263
 264                 tmp &= ~srbm_soft_reset;
 265                 WREG32(SRBM_SOFT_RESET, tmp);
 266                 tmp = RREG32(SRBM_SOFT_RESET);
 267
 268                 udelay(50);
 269         }
 270
 271         return 0;
 272 }
 273
 274 static int si_ih_set_clockgating_state(void *handle,
 275                                           enum amd_clockgating_state state)
 276 {
 277         return 0;
 278 }
 279
 280 static int si_ih_set_powergating_state(void *handle,
 281                                           enum amd_powergating_state state)
 282 {
 283         return 0;
 284 }
 285
 286 static const struct amd_ip_funcs si_ih_ip_funcs = {
 287         .name = "si_ih",
 288         .early_init = si_ih_early_init,
 289         .late_init = NULL,
 290         .sw_init = si_ih_sw_init,
 291         .sw_fini = si_ih_sw_fini,
 292         .hw_init = si_ih_hw_init,
 293         .hw_fini = si_ih_hw_fini,
 294         .suspend = si_ih_suspend,
 295         .resume = si_ih_resume,
 296         .is_idle = si_ih_is_idle,
 297         .wait_for_idle = si_ih_wait_for_idle,
 298         .soft_reset = si_ih_soft_reset,
 299         .set_clockgating_state = si_ih_set_clockgating_state,
 300         .set_powergating_state = si_ih_set_powergating_state,
 301 };
 302
 303 static const struct amdgpu_ih_funcs si_ih_funcs = {
 304         .get_wptr = si_ih_get_wptr,
 305         .prescreen_iv = si_ih_prescreen_iv,
 306         .decode_iv = si_ih_decode_iv,
 307         .set_rptr = si_ih_set_rptr
 308 };
 309
 310 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
 311 {
 312         if (adev->irq.ih_funcs == NULL)
 313                 adev->irq.ih_funcs = &si_ih_funcs;
 314 }
 315
 316 const struct amdgpu_ip_block_version si_ih_ip_block =
 317 {
 318         .type = AMD_IP_BLOCK_TYPE_IH,
 319         .major = 1,
 320         .minor = 0,
 321         .rev = 0,
 322         .funcs = &si_ih_ip_funcs,
 323 };