drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _SMU_HELPER_H_
  24 #define _SMU_HELPER_H_
  25
  26 struct pp_atomctrl_voltage_table;
  27 struct pp_hwmgr;
  28 struct phm_ppt_v1_voltage_lookup_table;
  29 struct Watermarks_t;
  30 struct pp_wm_sets_with_clock_ranges_soc15;
  31
  32 uint8_t convert_to_vid(uint16_t vddc);
  33 uint16_t convert_to_vddc(uint8_t vid);
  34
  35 struct watermark_row_generic_t {
  36         uint16_t MinClock;
  37         uint16_t MaxClock;
  38         uint16_t MinUclk;
  39         uint16_t MaxUclk;
  40
  41         uint8_t  WmSetting;
  42         uint8_t  Padding[3];
  43 };
  44
  45 struct watermarks {
  46         struct watermark_row_generic_t WatermarkRow[2][4];
  47         uint32_t     padding[7];
  48 };
  49
  50 extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
  51                                         uint32_t index,
  52                                         uint32_t value, uint32_t mask);
  53 extern int phm_wait_for_indirect_register_unequal(
  54                                 struct pp_hwmgr *hwmgr,
  55                                 uint32_t indirect_port, uint32_t index,
  56                                 uint32_t value, uint32_t mask);
  57
  58
  59 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
  60 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
  61 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
  62
  63 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
  64 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
  65 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
  66 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
  67 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
  68 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
  69 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
  70 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
  71 extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
  72                 uint32_t voltage);
  73 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
  74 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
  75 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
  76 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
  77                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
  78 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
  79 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
  80 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
  81
  82 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
  83                                 uint32_t sclk, uint16_t id, uint16_t *voltage);
  84
  85 extern uint32_t phm_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size);
  86
  87 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
  88                                 uint32_t value, uint32_t mask);
  89
  90 extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
  91                                 uint32_t indirect_port,
  92                                 uint32_t index,
  93                                 uint32_t value,
  94                                 uint32_t mask);
  95
  96 int phm_irq_process(struct amdgpu_device *adev,
  97                            struct amdgpu_irq_src *source,
  98                            struct amdgpu_iv_entry *entry);
  99
 100 int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr);
 101
 102 void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size,
 103                                                 uint8_t *frev, uint8_t *crev);
 104
 105 int smu_get_voltage_dependency_table_ppt_v1(
 106         const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
 107                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 108
 109 int smu_set_watermarks_for_clocks_ranges(void *wt_table,
 110                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
 111
 112 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 113 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 114
 115 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 116         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 117          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 118
 119 #define PHM_GET_FIELD(value, reg, field)        \
 120         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 121          PHM_FIELD_SHIFT(reg, field))
 122
 123
 124 /* Operations on named fields. */
 125
 126 #define PHM_READ_FIELD(device, reg, field)      \
 127         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 128
 129 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 130         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 131                         reg, field)
 132
 133 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 134         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 135                         reg, field)
 136
 137 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 138         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 139                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 140
 141 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 142         cgs_write_ind_register(device, port, ix##reg,   \
 143                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 144                                 reg, field, fieldval))
 145
 146 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 147         cgs_write_ind_register(device, port, ix##reg,   \
 148                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 149                                 reg, field, fieldval))
 150
 151 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
 152        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 153
 154
 155 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
 156        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 157
 158 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 159         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 160                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 161
 162 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 163                 phm_wait_for_indirect_register_unequal(hwmgr,                   \
 164                                 mm##port##_INDEX, index, value, mask)
 165
 166 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)    \
 167                 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 168
 169 #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)                          \
 170                 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
 171                                 (fieldval) << PHM_FIELD_SHIFT(reg, field), \
 172                                         PHM_FIELD_MASK(reg, field) )
 173
 174
 175 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,      \
 176                                 port, index, value, mask)               \
 177         phm_wait_for_indirect_register_unequal(hwmgr,                   \
 178                 mm##port##_INDEX_11, index, value, mask)
 179
 180 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)     \
 181                 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 182
 183 #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
 184         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg,       \
 185                 (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
 186                 PHM_FIELD_MASK(reg, field))
 187
 188
 189 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,              \
 190                                 port, index, value, mask)               \
 191         phm_wait_on_indirect_register(hwmgr,                            \
 192                 mm##port##_INDEX_11, index, value, mask)
 193
 194 #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
 195         PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 196
 197 #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
 198         PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,               \
 199                 (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
 200                 PHM_FIELD_MASK(reg, field))
 201
 202 #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,         \
 203                                                         index, value, mask) \
 204                 phm_wait_for_register_unequal(hwmgr,            \
 205                                         index, value, mask)
 206
 207 #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)              \
 208         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,                    \
 209                                 mm##reg, value, mask)
 210
 211 #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)             \
 212         PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg,                           \
 213                 (fieldval) << PHM_FIELD_SHIFT(reg, field),              \
 214                 PHM_FIELD_MASK(reg, field))
 215
 216 #endif /* _SMU_HELPER_H_ */