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Linux 4.19.133
[linux/fpc-iii.git] / drivers / gpu / drm / bridge / analogix / analogix_dp_reg.c
bloba5f2763d72e4b404eda77374e88da61806840474
1 /*
2 * Analogix DP (Display port) core register interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18
19 #include <drm/bridge/analogix_dp.h>
20
21 #include "analogix_dp_core.h"
22 #include "analogix_dp_reg.h"
23
24 #define COMMON_INT_MASK_1 0
25 #define COMMON_INT_MASK_2 0
26 #define COMMON_INT_MASK_3 0
27 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
28 #define INT_STA_MASK INT_HPD
29
30 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
31 {
32 u32 reg;
33
34 if (enable) {
35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
36 reg |= HDCP_VIDEO_MUTE;
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
38 } else {
39 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
40 reg &= ~HDCP_VIDEO_MUTE;
41 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
42 }
43 }
44
45 void analogix_dp_stop_video(struct analogix_dp_device *dp)
46 {
47 u32 reg;
48
49 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
50 reg &= ~VIDEO_EN;
51 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
52 }
53
54 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
55 {
56 u32 reg;
57
58 if (enable)
59 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
60 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
61 else
62 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
63 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
64
65 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
66 }
67
68 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
69 {
70 u32 reg;
71
72 reg = TX_TERMINAL_CTRL_50_OHM;
73 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
74
75 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
76 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
77
78 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
79 reg = REF_CLK_24M;
80 if (dp->plat_data->dev_type == RK3288_DP)
81 reg ^= REF_CLK_MASK;
82
83 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
84 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
85 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
86 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
87 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
88 }
89
90 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
91 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
92
93 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
94 TX_CUR1_2X | TX_CUR_16_MA;
95 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
96
97 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
98 CH1_AMP_400_MV | CH0_AMP_400_MV;
99 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
100 }
101
102 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
103 {
104 /* Set interrupt pin assertion polarity as high */
105 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
106
107 /* Clear pending regisers */
108 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
109 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
110 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
111 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
112 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
113
114 /* 0:mask,1: unmask */
115 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
116 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
117 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
118 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
119 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
120 }
121
122 void analogix_dp_reset(struct analogix_dp_device *dp)
123 {
124 u32 reg;
125
126 analogix_dp_stop_video(dp);
127 analogix_dp_enable_video_mute(dp, 0);
128
129 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
130 reg = RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N |
131 SW_FUNC_EN_N;
132 else
133 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
134 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
135 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
136
137 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
138
139 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
140 SERDES_FIFO_FUNC_EN_N |
141 LS_CLK_DOMAIN_FUNC_EN_N;
142 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
143
144 usleep_range(20, 30);
145
146 analogix_dp_lane_swap(dp, 0);
147
148 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
149 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
150 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
151 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
152
153 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
154 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
155
156 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
157 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
158
159 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
160
161 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
162
163 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
164 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
165
166 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
167 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
168
169 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
170 }
171
172 void analogix_dp_swreset(struct analogix_dp_device *dp)
173 {
174 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
175 }
176
177 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
178 {
179 u32 reg;
180
181 /* 0: mask, 1: unmask */
182 reg = COMMON_INT_MASK_1;
183 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
184
185 reg = COMMON_INT_MASK_2;
186 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
187
188 reg = COMMON_INT_MASK_3;
189 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
190
191 reg = COMMON_INT_MASK_4;
192 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
193
194 reg = INT_STA_MASK;
195 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
196 }
197
198 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
199 {
200 u32 reg;
201
202 /* 0: mask, 1: unmask */
203 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
204 reg &= ~COMMON_INT_MASK_4;
205 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
206
207 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
208 reg &= ~INT_STA_MASK;
209 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
210 }
211
212 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
213 {
214 u32 reg;
215
216 /* 0: mask, 1: unmask */
217 reg = COMMON_INT_MASK_4;
218 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
219
220 reg = INT_STA_MASK;
221 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
222 }
223
224 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
225 {
226 u32 reg;
227
228 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
229 if (reg & PLL_LOCK)
230 return PLL_LOCKED;
231 else
232 return PLL_UNLOCKED;
233 }
234
235 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
236 {
237 u32 reg;
238 u32 mask = DP_PLL_PD;
239 u32 pd_addr = ANALOGIX_DP_PLL_CTL;
240
241 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
242 pd_addr = ANALOGIX_DP_PD;
243 mask = RK_PLL_PD;
244 }
245
246 reg = readl(dp->reg_base + pd_addr);
247 if (enable)
248 reg |= mask;
249 else
250 reg &= ~mask;
251 writel(reg, dp->reg_base + pd_addr);
252 }
253
254 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
255 enum analog_power_block block,
256 bool enable)
257 {
258 u32 reg;
259 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
260 u32 mask;
261
262 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
263 phy_pd_addr = ANALOGIX_DP_PD;
264
265 switch (block) {
266 case AUX_BLOCK:
267 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
268 mask = RK_AUX_PD;
269 else
270 mask = AUX_PD;
271
272 reg = readl(dp->reg_base + phy_pd_addr);
273 if (enable)
274 reg |= mask;
275 else
276 reg &= ~mask;
277 writel(reg, dp->reg_base + phy_pd_addr);
278 break;
279 case CH0_BLOCK:
280 mask = CH0_PD;
281 reg = readl(dp->reg_base + phy_pd_addr);
282
283 if (enable)
284 reg |= mask;
285 else
286 reg &= ~mask;
287 writel(reg, dp->reg_base + phy_pd_addr);
288 break;
289 case CH1_BLOCK:
290 mask = CH1_PD;
291 reg = readl(dp->reg_base + phy_pd_addr);
292
293 if (enable)
294 reg |= mask;
295 else
296 reg &= ~mask;
297 writel(reg, dp->reg_base + phy_pd_addr);
298 break;
299 case CH2_BLOCK:
300 mask = CH2_PD;
301 reg = readl(dp->reg_base + phy_pd_addr);
302
303 if (enable)
304 reg |= mask;
305 else
306 reg &= ~mask;
307 writel(reg, dp->reg_base + phy_pd_addr);
308 break;
309 case CH3_BLOCK:
310 mask = CH3_PD;
311 reg = readl(dp->reg_base + phy_pd_addr);
312
313 if (enable)
314 reg |= mask;
315 else
316 reg &= ~mask;
317 writel(reg, dp->reg_base + phy_pd_addr);
318 break;
319 case ANALOG_TOTAL:
320 /*
321 * There is no bit named DP_PHY_PD, so We used DP_INC_BG
322 * to power off everything instead of DP_PHY_PD in
323 * Rockchip
324 */
325 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
326 mask = DP_INC_BG;
327 else
328 mask = DP_PHY_PD;
329
330 reg = readl(dp->reg_base + phy_pd_addr);
331 if (enable)
332 reg |= mask;
333 else
334 reg &= ~mask;
335
336 writel(reg, dp->reg_base + phy_pd_addr);
337 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
338 usleep_range(10, 15);
339 break;
340 case POWER_ALL:
341 if (enable) {
342 reg = DP_ALL_PD;
343 writel(reg, dp->reg_base + phy_pd_addr);
344 } else {
345 reg = DP_ALL_PD;
346 writel(reg, dp->reg_base + phy_pd_addr);
347 usleep_range(10, 15);
348 reg &= ~DP_INC_BG;
349 writel(reg, dp->reg_base + phy_pd_addr);
350 usleep_range(10, 15);
351
352 writel(0x00, dp->reg_base + phy_pd_addr);
353 }
354 break;
355 default:
356 break;
357 }
358 }
359
360 int analogix_dp_init_analog_func(struct analogix_dp_device *dp)
361 {
362 u32 reg;
363 int timeout_loop = 0;
364
365 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
366
367 reg = PLL_LOCK_CHG;
368 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
369
370 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
371 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
372 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
373
374 /* Power up PLL */
375 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
376 analogix_dp_set_pll_power_down(dp, 0);
377
378 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
379 timeout_loop++;
380 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
381 dev_err(dp->dev, "failed to get pll lock status\n");
382 return -ETIMEDOUT;
383 }
384 usleep_range(10, 20);
385 }
386 }
387
388 /* Enable Serdes FIFO function and Link symbol clock domain module */
389 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
390 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
391 | AUX_FUNC_EN_N);
392 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
393 return 0;
394 }
395
396 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
397 {
398 u32 reg;
399
400 if (gpio_is_valid(dp->hpd_gpio))
401 return;
402
403 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
404 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
405
406 reg = INT_HPD;
407 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
408 }
409
410 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
411 {
412 u32 reg;
413
414 if (gpio_is_valid(dp->hpd_gpio))
415 return;
416
417 analogix_dp_clear_hotplug_interrupts(dp);
418
419 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
420 reg &= ~(F_HPD | HPD_CTRL);
421 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
422 }
423
424 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
425 {
426 u32 reg;
427
428 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
429 reg = (F_HPD | HPD_CTRL);
430 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
431 }
432
433 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
434 {
435 u32 reg;
436
437 if (gpio_is_valid(dp->hpd_gpio)) {
438 reg = gpio_get_value(dp->hpd_gpio);
439 if (reg)
440 return DP_IRQ_TYPE_HP_CABLE_IN;
441 else
442 return DP_IRQ_TYPE_HP_CABLE_OUT;
443 } else {
444 /* Parse hotplug interrupt status register */
445 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
446
447 if (reg & PLUG)
448 return DP_IRQ_TYPE_HP_CABLE_IN;
449
450 if (reg & HPD_LOST)
451 return DP_IRQ_TYPE_HP_CABLE_OUT;
452
453 if (reg & HOTPLUG_CHG)
454 return DP_IRQ_TYPE_HP_CHANGE;
455
456 return DP_IRQ_TYPE_UNKNOWN;
457 }
458 }
459
460 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
461 {
462 u32 reg;
463
464 /* Disable AUX channel module */
465 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
466 reg |= AUX_FUNC_EN_N;
467 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
468 }
469
470 void analogix_dp_init_aux(struct analogix_dp_device *dp)
471 {
472 u32 reg;
473
474 /* Clear inerrupts related to AUX channel */
475 reg = RPLY_RECEIV | AUX_ERR;
476 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
477
478 analogix_dp_set_analog_power_down(dp, AUX_BLOCK, true);
479 usleep_range(10, 11);
480 analogix_dp_set_analog_power_down(dp, AUX_BLOCK, false);
481
482 analogix_dp_reset_aux(dp);
483
484 /* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */
485 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
486 reg = 0;
487 else
488 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3);
489
490 /* Disable AUX transaction H/W retry */
491 reg |= AUX_HW_RETRY_COUNT_SEL(0) |
492 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
493
494 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
495
496 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
497 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
498 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
499
500 /* Enable AUX channel module */
501 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
502 reg &= ~AUX_FUNC_EN_N;
503 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
504 }
505
506 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
507 {
508 u32 reg;
509
510 if (gpio_is_valid(dp->hpd_gpio)) {
511 if (gpio_get_value(dp->hpd_gpio))
512 return 0;
513 } else {
514 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
515 if (reg & HPD_STATUS)
516 return 0;
517 }
518
519 return -EINVAL;
520 }
521
522 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
523 {
524 u32 reg;
525
526 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
527 reg &= ~SW_FUNC_EN_N;
528 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
529 }
530
531 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
532 {
533 int reg;
534 int retval = 0;
535 int timeout_loop = 0;
536
537 /* Enable AUX CH operation */
538 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
539 reg |= AUX_EN;
540 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
541
542 /* Is AUX CH command reply received? */
543 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
544 while (!(reg & RPLY_RECEIV)) {
545 timeout_loop++;
546 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
547 dev_err(dp->dev, "AUX CH command reply failed!\n");
548 return -ETIMEDOUT;
549 }
550 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
551 usleep_range(10, 11);
552 }
553
554 /* Clear interrupt source for AUX CH command reply */
555 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
556
557 /* Clear interrupt source for AUX CH access error */
558 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
559 if (reg & AUX_ERR) {
560 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
561 return -EREMOTEIO;
562 }
563
564 /* Check AUX CH error access status */
565 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
566 if ((reg & AUX_STATUS_MASK) != 0) {
567 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
568 reg & AUX_STATUS_MASK);
569 return -EREMOTEIO;
570 }
571
572 return retval;
573 }
574
575 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
576 unsigned int reg_addr,
577 unsigned char data)
578 {
579 u32 reg;
580 int i;
581 int retval;
582
583 for (i = 0; i < 3; i++) {
584 /* Clear AUX CH data buffer */
585 reg = BUF_CLR;
586 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
587
588 /* Select DPCD device address */
589 reg = AUX_ADDR_7_0(reg_addr);
590 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
591 reg = AUX_ADDR_15_8(reg_addr);
592 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
593 reg = AUX_ADDR_19_16(reg_addr);
594 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
595
596 /* Write data buffer */
597 reg = (unsigned int)data;
598 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
599
600 /*
601 * Set DisplayPort transaction and write 1 byte
602 * If bit 3 is 1, DisplayPort transaction.
603 * If Bit 3 is 0, I2C transaction.
604 */
605 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
606 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
607
608 /* Start AUX transaction */
609 retval = analogix_dp_start_aux_transaction(dp);
610 if (retval == 0)
611 break;
612
613 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
614 }
615
616 return retval;
617 }
618
619 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
620 {
621 u32 reg;
622
623 reg = bwtype;
624 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
625 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
626 }
627
628 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
629 {
630 u32 reg;
631
632 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
633 *bwtype = reg;
634 }
635
636 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
637 {
638 u32 reg;
639
640 reg = count;
641 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
642 }
643
644 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
645 {
646 u32 reg;
647
648 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
649 *count = reg;
650 }
651
652 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
653 bool enable)
654 {
655 u32 reg;
656
657 if (enable) {
658 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
659 reg |= ENHANCED;
660 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
661 } else {
662 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
663 reg &= ~ENHANCED;
664 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
665 }
666 }
667
668 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
669 enum pattern_set pattern)
670 {
671 u32 reg;
672
673 switch (pattern) {
674 case PRBS7:
675 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
676 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
677 break;
678 case D10_2:
679 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
680 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
681 break;
682 case TRAINING_PTN1:
683 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
684 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
685 break;
686 case TRAINING_PTN2:
687 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
688 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
689 break;
690 case DP_NONE:
691 reg = SCRAMBLING_ENABLE |
692 LINK_QUAL_PATTERN_SET_DISABLE |
693 SW_TRAINING_PATTERN_SET_NORMAL;
694 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
695 break;
696 default:
697 break;
698 }
699 }
700
701 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
702 u32 level)
703 {
704 u32 reg;
705
706 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
707 reg &= ~PRE_EMPHASIS_SET_MASK;
708 reg |= level << PRE_EMPHASIS_SET_SHIFT;
709 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
710 }
711
712 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
713 u32 level)
714 {
715 u32 reg;
716
717 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
718 reg &= ~PRE_EMPHASIS_SET_MASK;
719 reg |= level << PRE_EMPHASIS_SET_SHIFT;
720 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
721 }
722
723 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
724 u32 level)
725 {
726 u32 reg;
727
728 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
729 reg &= ~PRE_EMPHASIS_SET_MASK;
730 reg |= level << PRE_EMPHASIS_SET_SHIFT;
731 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
732 }
733
734 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
735 u32 level)
736 {
737 u32 reg;
738
739 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
740 reg &= ~PRE_EMPHASIS_SET_MASK;
741 reg |= level << PRE_EMPHASIS_SET_SHIFT;
742 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
743 }
744
745 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
746 u32 training_lane)
747 {
748 u32 reg;
749
750 reg = training_lane;
751 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
752 }
753
754 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
755 u32 training_lane)
756 {
757 u32 reg;
758
759 reg = training_lane;
760 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
761 }
762
763 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
764 u32 training_lane)
765 {
766 u32 reg;
767
768 reg = training_lane;
769 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
770 }
771
772 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
773 u32 training_lane)
774 {
775 u32 reg;
776
777 reg = training_lane;
778 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
779 }
780
781 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
782 {
783 return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
784 }
785
786 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
787 {
788 return readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
789 }
790
791 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
792 {
793 return readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
794 }
795
796 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
797 {
798 return readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
799 }
800
801 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
802 {
803 u32 reg;
804
805 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
806 reg |= MACRO_RST;
807 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
808
809 /* 10 us is the minimum reset time. */
810 usleep_range(10, 20);
811
812 reg &= ~MACRO_RST;
813 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
814 }
815
816 void analogix_dp_init_video(struct analogix_dp_device *dp)
817 {
818 u32 reg;
819
820 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
821 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
822
823 reg = 0x0;
824 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
825
826 reg = CHA_CRI(4) | CHA_CTRL;
827 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
828
829 reg = 0x0;
830 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
831
832 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
833 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
834 }
835
836 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
837 {
838 u32 reg;
839
840 /* Configure the input color depth, color space, dynamic range */
841 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
842 (dp->video_info.color_depth << IN_BPC_SHIFT) |
843 (dp->video_info.color_space << IN_COLOR_F_SHIFT);
844 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
845
846 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
847 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
848 reg &= ~IN_YC_COEFFI_MASK;
849 if (dp->video_info.ycbcr_coeff)
850 reg |= IN_YC_COEFFI_ITU709;
851 else
852 reg |= IN_YC_COEFFI_ITU601;
853 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
854 }
855
856 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
857 {
858 u32 reg;
859
860 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
861 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
862
863 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
864
865 if (!(reg & DET_STA)) {
866 dev_dbg(dp->dev, "Input stream clock not detected.\n");
867 return -EINVAL;
868 }
869
870 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
871 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
872
873 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
874 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
875
876 if (reg & CHA_STA) {
877 dev_dbg(dp->dev, "Input stream clk is changing\n");
878 return -EINVAL;
879 }
880
881 return 0;
882 }
883
884 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
885 enum clock_recovery_m_value_type type,
886 u32 m_value, u32 n_value)
887 {
888 u32 reg;
889
890 if (type == REGISTER_M) {
891 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
892 reg |= FIX_M_VID;
893 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
894 reg = m_value & 0xff;
895 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
896 reg = (m_value >> 8) & 0xff;
897 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
898 reg = (m_value >> 16) & 0xff;
899 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
900
901 reg = n_value & 0xff;
902 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
903 reg = (n_value >> 8) & 0xff;
904 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
905 reg = (n_value >> 16) & 0xff;
906 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
907 } else {
908 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
909 reg &= ~FIX_M_VID;
910 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
911
912 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
913 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
914 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
915 }
916 }
917
918 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
919 {
920 u32 reg;
921
922 if (type == VIDEO_TIMING_FROM_CAPTURE) {
923 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
924 reg &= ~FORMAT_SEL;
925 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
926 } else {
927 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
928 reg |= FORMAT_SEL;
929 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
930 }
931 }
932
933 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
934 {
935 u32 reg;
936
937 if (enable) {
938 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
939 reg &= ~VIDEO_MODE_MASK;
940 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
941 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
942 } else {
943 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
944 reg &= ~VIDEO_MODE_MASK;
945 reg |= VIDEO_MODE_SLAVE_MODE;
946 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
947 }
948 }
949
950 void analogix_dp_start_video(struct analogix_dp_device *dp)
951 {
952 u32 reg;
953
954 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
955 reg |= VIDEO_EN;
956 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
957 }
958
959 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
960 {
961 u32 reg;
962
963 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
964 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
965
966 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
967 if (!(reg & STRM_VALID)) {
968 dev_dbg(dp->dev, "Input video stream is not detected.\n");
969 return -EINVAL;
970 }
971
972 return 0;
973 }
974
975 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
976 {
977 u32 reg;
978
979 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
980 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
981 reg &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
982 } else {
983 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
984 reg |= MASTER_VID_FUNC_EN_N;
985 }
986 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
987
988 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
989 reg &= ~INTERACE_SCAN_CFG;
990 reg |= (dp->video_info.interlaced << 2);
991 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
992
993 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
994 reg &= ~VSYNC_POLARITY_CFG;
995 reg |= (dp->video_info.v_sync_polarity << 1);
996 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
997
998 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
999 reg &= ~HSYNC_POLARITY_CFG;
1000 reg |= (dp->video_info.h_sync_polarity << 0);
1001 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1002
1003 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1004 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1005 }
1006
1007 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
1008 {
1009 u32 reg;
1010
1011 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1012 reg &= ~SCRAMBLING_DISABLE;
1013 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1014 }
1015
1016 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
1017 {
1018 u32 reg;
1019
1020 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1021 reg |= SCRAMBLING_DISABLE;
1022 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1023 }
1024
1025 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp)
1026 {
1027 writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON);
1028 }
1029
1030 static ssize_t analogix_dp_get_psr_status(struct analogix_dp_device *dp)
1031 {
1032 ssize_t val;
1033 u8 status;
1034
1035 val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status);
1036 if (val < 0) {
1037 dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val);
1038 return val;
1039 }
1040 return status;
1041 }
1042
1043 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
1044 struct edp_vsc_psr *vsc, bool blocking)
1045 {
1046 unsigned int val;
1047 int ret;
1048 ssize_t psr_status;
1049
1050 /* don't send info frame */
1051 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1052 val &= ~IF_EN;
1053 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1054
1055 /* configure single frame update mode */
1056 writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE,
1057 dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL);
1058
1059 /* configure VSC HB0~HB3 */
1060 writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0);
1061 writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1);
1062 writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2);
1063 writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3);
1064
1065 /* configure reused VSC PB0~PB3, magic number from vendor */
1066 writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0);
1067 writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1);
1068 writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2);
1069 writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3);
1070
1071 /* configure DB0 / DB1 values */
1072 writel(vsc->DB0, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0);
1073 writel(vsc->DB1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1);
1074
1075 /* set reuse spd inforframe */
1076 val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1077 val |= REUSE_SPD_EN;
1078 writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1079
1080 /* mark info frame update */
1081 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1082 val = (val | IF_UP) & ~IF_EN;
1083 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1084
1085 /* send info frame */
1086 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1087 val |= IF_EN;
1088 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
1089
1090 if (!blocking)
1091 return 0;
1092
1093 ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status,
1094 psr_status >= 0 &&
1095 ((vsc->DB1 && psr_status == DP_PSR_SINK_ACTIVE_RFB) ||
1096 (!vsc->DB1 && psr_status == DP_PSR_SINK_INACTIVE)), 1500,
1097 DP_TIMEOUT_PSR_LOOP_MS * 1000);
1098 if (ret) {
1099 dev_warn(dp->dev, "Failed to apply PSR %d\n", ret);
1100 return ret;
1101 }
1102 return 0;
1103 }
1104
1105 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
1106 struct drm_dp_aux_msg *msg)
1107 {
1108 u32 reg;
1109 u32 status_reg;
1110 u8 *buffer = msg->buffer;
1111 unsigned int i;
1112 int num_transferred = 0;
1113 int ret;
1114
1115 /* Buffer size of AUX CH is 16 bytes */
1116 if (WARN_ON(msg->size > 16))
1117 return -E2BIG;
1118
1119 /* Clear AUX CH data buffer */
1120 reg = BUF_CLR;
1121 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
1122
1123 switch (msg->request & ~DP_AUX_I2C_MOT) {
1124 case DP_AUX_I2C_WRITE:
1125 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION;
1126 if (msg->request & DP_AUX_I2C_MOT)
1127 reg |= AUX_TX_COMM_MOT;
1128 break;
1129
1130 case DP_AUX_I2C_READ:
1131 reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION;
1132 if (msg->request & DP_AUX_I2C_MOT)
1133 reg |= AUX_TX_COMM_MOT;
1134 break;
1135
1136 case DP_AUX_NATIVE_WRITE:
1137 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION;
1138 break;
1139
1140 case DP_AUX_NATIVE_READ:
1141 reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION;
1142 break;
1143
1144 default:
1145 return -EINVAL;
1146 }
1147
1148 reg |= AUX_LENGTH(msg->size);
1149 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
1150
1151 /* Select DPCD device address */
1152 reg = AUX_ADDR_7_0(msg->address);
1153 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
1154 reg = AUX_ADDR_15_8(msg->address);
1155 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
1156 reg = AUX_ADDR_19_16(msg->address);
1157 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
1158
1159 if (!(msg->request & DP_AUX_I2C_READ)) {
1160 for (i = 0; i < msg->size; i++) {
1161 reg = buffer[i];
1162 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1163 4 * i);
1164 num_transferred++;
1165 }
1166 }
1167
1168 /* Enable AUX CH operation */
1169 reg = AUX_EN;
1170
1171 /* Zero-sized messages specify address-only transactions. */
1172 if (msg->size < 1)
1173 reg |= ADDR_ONLY;
1174
1175 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
1176
1177 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2,
1178 reg, !(reg & AUX_EN), 25, 500 * 1000);
1179 if (ret) {
1180 dev_err(dp->dev, "AUX CH enable timeout!\n");
1181 goto aux_error;
1182 }
1183
1184 /* TODO: Wait for an interrupt instead of looping? */
1185 /* Is AUX CH command reply received? */
1186 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA,
1187 reg, reg & RPLY_RECEIV, 10, 20 * 1000);
1188 if (ret) {
1189 dev_err(dp->dev, "AUX CH cmd reply timeout!\n");
1190 goto aux_error;
1191 }
1192
1193 /* Clear interrupt source for AUX CH command reply */
1194 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
1195
1196 /* Clear interrupt source for AUX CH access error */
1197 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
1198 status_reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
1199 if ((reg & AUX_ERR) || (status_reg & AUX_STATUS_MASK)) {
1200 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
1201
1202 dev_warn(dp->dev, "AUX CH error happened: %#x (%d)\n",
1203 status_reg & AUX_STATUS_MASK, !!(reg & AUX_ERR));
1204 goto aux_error;
1205 }
1206
1207 if (msg->request & DP_AUX_I2C_READ) {
1208 for (i = 0; i < msg->size; i++) {
1209 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 +
1210 4 * i);
1211 buffer[i] = (unsigned char)reg;
1212 num_transferred++;
1213 }
1214 }
1215
1216 /* Check if Rx sends defer */
1217 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
1218 if (reg == AUX_RX_COMM_AUX_DEFER)
1219 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1220 else if (reg == AUX_RX_COMM_I2C_DEFER)
1221 msg->reply = DP_AUX_I2C_REPLY_DEFER;
1222 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE ||
1223 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ)
1224 msg->reply = DP_AUX_I2C_REPLY_ACK;
1225 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE ||
1226 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
1227 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1228
1229 return num_transferred > 0 ? num_transferred : -EBUSY;
1230
1231 aux_error:
1232 /* if aux err happen, reset aux */
1233 analogix_dp_init_aux(dp);
1234
1235 return -EREMOTEIO;
1236 }
Linux with added FPC-III support