2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
85 /* Non desktop display (i.e. HMD) */
86 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
88 struct detailed_mode_closure
{
89 struct drm_connector
*connector
;
101 static const struct edid_quirk
{
105 } edid_quirk_list
[] = {
107 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60
},
109 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60
},
111 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED
},
113 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
114 { "AEO", 0, EDID_QUIRK_FORCE_6BPC
},
116 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
117 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC
},
119 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
120 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC
},
122 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
123 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC
},
125 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
126 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC
},
128 /* Belinea 10 15 55 */
129 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60
},
130 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60
},
132 /* Envision Peripherals, Inc. EN-7100e */
133 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH
},
134 /* Envision EN2028 */
135 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60
},
137 /* Funai Electronics PM36B */
138 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75
|
139 EDID_QUIRK_DETAILED_IN_CM
},
141 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
142 { "LGD", 764, EDID_QUIRK_FORCE_10BPC
},
144 /* LG Philips LCD LP154W01-A5 */
145 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE
},
146 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE
},
148 /* Philips 107p5 CRT */
149 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED
},
152 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED
},
154 /* Samsung SyncMaster 205BW. Note: irony */
155 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP
},
156 /* Samsung SyncMaster 22[5-6]BW */
157 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60
},
158 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60
},
160 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
161 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC
},
163 /* ViewSonic VA2026w */
164 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING
},
166 /* Medion MD 30217 PG */
167 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75
},
170 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC
},
172 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
173 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC
},
175 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
176 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC
},
178 /* Valve Index Headset */
179 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP
},
180 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP
},
181 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP
},
182 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP
},
183 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP
},
184 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP
},
185 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP
},
186 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP
},
187 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP
},
188 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP
},
189 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP
},
190 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP
},
191 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP
},
192 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP
},
193 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP
},
194 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP
},
195 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP
},
197 /* HTC Vive and Vive Pro VR Headsets */
198 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP
},
199 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP
},
201 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
202 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP
},
203 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP
},
204 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP
},
205 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP
},
207 /* Windows Mixed Reality Headsets */
208 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP
},
209 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP
},
210 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP
},
211 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP
},
212 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP
},
213 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP
},
214 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP
},
215 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP
},
217 /* Sony PlayStation VR Headset */
218 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP
},
220 /* Sensics VR Headsets */
221 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP
},
223 /* OSVR HDK and HDK2 VR Headsets */
224 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP
},
228 * Autogenerated from the DMT spec.
229 * This table is copied from xfree86/modes/xf86EdidModes.c.
231 static const struct drm_display_mode drm_dmt_modes
[] = {
232 /* 0x01 - 640x350@85Hz */
233 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER
, 31500, 640, 672,
234 736, 832, 0, 350, 382, 385, 445, 0,
235 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
236 /* 0x02 - 640x400@85Hz */
237 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER
, 31500, 640, 672,
238 736, 832, 0, 400, 401, 404, 445, 0,
239 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
240 /* 0x03 - 720x400@85Hz */
241 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 35500, 720, 756,
242 828, 936, 0, 400, 401, 404, 446, 0,
243 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
244 /* 0x04 - 640x480@60Hz */
245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
246 752, 800, 0, 480, 490, 492, 525, 0,
247 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
248 /* 0x05 - 640x480@72Hz */
249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 664,
250 704, 832, 0, 480, 489, 492, 520, 0,
251 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
252 /* 0x06 - 640x480@75Hz */
253 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 656,
254 720, 840, 0, 480, 481, 484, 500, 0,
255 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
256 /* 0x07 - 640x480@85Hz */
257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 36000, 640, 696,
258 752, 832, 0, 480, 481, 484, 509, 0,
259 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
260 /* 0x08 - 800x600@56Hz */
261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 36000, 800, 824,
262 896, 1024, 0, 600, 601, 603, 625, 0,
263 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
264 /* 0x09 - 800x600@60Hz */
265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 40000, 800, 840,
266 968, 1056, 0, 600, 601, 605, 628, 0,
267 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
268 /* 0x0a - 800x600@72Hz */
269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 50000, 800, 856,
270 976, 1040, 0, 600, 637, 643, 666, 0,
271 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
272 /* 0x0b - 800x600@75Hz */
273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 49500, 800, 816,
274 896, 1056, 0, 600, 601, 604, 625, 0,
275 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
276 /* 0x0c - 800x600@85Hz */
277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 56250, 800, 832,
278 896, 1048, 0, 600, 601, 604, 631, 0,
279 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
280 /* 0x0d - 800x600@120Hz RB */
281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 73250, 800, 848,
282 880, 960, 0, 600, 603, 607, 636, 0,
283 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
284 /* 0x0e - 848x480@60Hz */
285 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER
, 33750, 848, 864,
286 976, 1088, 0, 480, 486, 494, 517, 0,
287 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
288 /* 0x0f - 1024x768@43Hz, interlace */
289 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER
, 44900, 1024, 1032,
290 1208, 1264, 0, 768, 768, 776, 817, 0,
291 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
292 DRM_MODE_FLAG_INTERLACE
) },
293 /* 0x10 - 1024x768@60Hz */
294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 65000, 1024, 1048,
295 1184, 1344, 0, 768, 771, 777, 806, 0,
296 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
297 /* 0x11 - 1024x768@70Hz */
298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 75000, 1024, 1048,
299 1184, 1328, 0, 768, 771, 777, 806, 0,
300 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
301 /* 0x12 - 1024x768@75Hz */
302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 78750, 1024, 1040,
303 1136, 1312, 0, 768, 769, 772, 800, 0,
304 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
305 /* 0x13 - 1024x768@85Hz */
306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 94500, 1024, 1072,
307 1168, 1376, 0, 768, 769, 772, 808, 0,
308 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
309 /* 0x14 - 1024x768@120Hz RB */
310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 115500, 1024, 1072,
311 1104, 1184, 0, 768, 771, 775, 813, 0,
312 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
313 /* 0x15 - 1152x864@75Hz */
314 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER
, 108000, 1152, 1216,
315 1344, 1600, 0, 864, 865, 868, 900, 0,
316 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
317 /* 0x55 - 1280x720@60Hz */
318 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1390,
319 1430, 1650, 0, 720, 725, 730, 750, 0,
320 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
321 /* 0x16 - 1280x768@60Hz RB */
322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 68250, 1280, 1328,
323 1360, 1440, 0, 768, 771, 778, 790, 0,
324 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
325 /* 0x17 - 1280x768@60Hz */
326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 79500, 1280, 1344,
327 1472, 1664, 0, 768, 771, 778, 798, 0,
328 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
329 /* 0x18 - 1280x768@75Hz */
330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 102250, 1280, 1360,
331 1488, 1696, 0, 768, 771, 778, 805, 0,
332 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
333 /* 0x19 - 1280x768@85Hz */
334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 117500, 1280, 1360,
335 1496, 1712, 0, 768, 771, 778, 809, 0,
336 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
337 /* 0x1a - 1280x768@120Hz RB */
338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER
, 140250, 1280, 1328,
339 1360, 1440, 0, 768, 771, 778, 813, 0,
340 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
341 /* 0x1b - 1280x800@60Hz RB */
342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 71000, 1280, 1328,
343 1360, 1440, 0, 800, 803, 809, 823, 0,
344 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
345 /* 0x1c - 1280x800@60Hz */
346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 83500, 1280, 1352,
347 1480, 1680, 0, 800, 803, 809, 831, 0,
348 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
349 /* 0x1d - 1280x800@75Hz */
350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 106500, 1280, 1360,
351 1488, 1696, 0, 800, 803, 809, 838, 0,
352 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
353 /* 0x1e - 1280x800@85Hz */
354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 122500, 1280, 1360,
355 1496, 1712, 0, 800, 803, 809, 843, 0,
356 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
357 /* 0x1f - 1280x800@120Hz RB */
358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER
, 146250, 1280, 1328,
359 1360, 1440, 0, 800, 803, 809, 847, 0,
360 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
361 /* 0x20 - 1280x960@60Hz */
362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER
, 108000, 1280, 1376,
363 1488, 1800, 0, 960, 961, 964, 1000, 0,
364 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
365 /* 0x21 - 1280x960@85Hz */
366 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1344,
367 1504, 1728, 0, 960, 961, 964, 1011, 0,
368 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
369 /* 0x22 - 1280x960@120Hz RB */
370 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER
, 175500, 1280, 1328,
371 1360, 1440, 0, 960, 963, 967, 1017, 0,
372 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
373 /* 0x23 - 1280x1024@60Hz */
374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 108000, 1280, 1328,
375 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
376 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
377 /* 0x24 - 1280x1024@75Hz */
378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 135000, 1280, 1296,
379 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
380 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
381 /* 0x25 - 1280x1024@85Hz */
382 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 157500, 1280, 1344,
383 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
384 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
385 /* 0x26 - 1280x1024@120Hz RB */
386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 187250, 1280, 1328,
387 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
388 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
389 /* 0x27 - 1360x768@60Hz */
390 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER
, 85500, 1360, 1424,
391 1536, 1792, 0, 768, 771, 777, 795, 0,
392 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
393 /* 0x28 - 1360x768@120Hz RB */
394 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER
, 148250, 1360, 1408,
395 1440, 1520, 0, 768, 771, 776, 813, 0,
396 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
397 /* 0x51 - 1366x768@60Hz */
398 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER
, 85500, 1366, 1436,
399 1579, 1792, 0, 768, 771, 774, 798, 0,
400 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
401 /* 0x56 - 1366x768@60Hz */
402 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER
, 72000, 1366, 1380,
403 1436, 1500, 0, 768, 769, 772, 800, 0,
404 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
405 /* 0x29 - 1400x1050@60Hz RB */
406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 101000, 1400, 1448,
407 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
408 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
409 /* 0x2a - 1400x1050@60Hz */
410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 121750, 1400, 1488,
411 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
412 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
413 /* 0x2b - 1400x1050@75Hz */
414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 156000, 1400, 1504,
415 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
416 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
417 /* 0x2c - 1400x1050@85Hz */
418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 179500, 1400, 1504,
419 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
420 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
421 /* 0x2d - 1400x1050@120Hz RB */
422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER
, 208000, 1400, 1448,
423 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
424 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
425 /* 0x2e - 1440x900@60Hz RB */
426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 88750, 1440, 1488,
427 1520, 1600, 0, 900, 903, 909, 926, 0,
428 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
429 /* 0x2f - 1440x900@60Hz */
430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 106500, 1440, 1520,
431 1672, 1904, 0, 900, 903, 909, 934, 0,
432 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
433 /* 0x30 - 1440x900@75Hz */
434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 136750, 1440, 1536,
435 1688, 1936, 0, 900, 903, 909, 942, 0,
436 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
437 /* 0x31 - 1440x900@85Hz */
438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 157000, 1440, 1544,
439 1696, 1952, 0, 900, 903, 909, 948, 0,
440 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
441 /* 0x32 - 1440x900@120Hz RB */
442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER
, 182750, 1440, 1488,
443 1520, 1600, 0, 900, 903, 909, 953, 0,
444 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
445 /* 0x53 - 1600x900@60Hz */
446 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER
, 108000, 1600, 1624,
447 1704, 1800, 0, 900, 901, 904, 1000, 0,
448 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
449 /* 0x33 - 1600x1200@60Hz */
450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 162000, 1600, 1664,
451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
452 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
453 /* 0x34 - 1600x1200@65Hz */
454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 175500, 1600, 1664,
455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
456 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
457 /* 0x35 - 1600x1200@70Hz */
458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 189000, 1600, 1664,
459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
460 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
461 /* 0x36 - 1600x1200@75Hz */
462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 202500, 1600, 1664,
463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
464 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
465 /* 0x37 - 1600x1200@85Hz */
466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 229500, 1600, 1664,
467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
468 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
469 /* 0x38 - 1600x1200@120Hz RB */
470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER
, 268250, 1600, 1648,
471 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
472 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
473 /* 0x39 - 1680x1050@60Hz RB */
474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 119000, 1680, 1728,
475 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
476 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
477 /* 0x3a - 1680x1050@60Hz */
478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 146250, 1680, 1784,
479 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
480 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
481 /* 0x3b - 1680x1050@75Hz */
482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 187000, 1680, 1800,
483 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
484 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
485 /* 0x3c - 1680x1050@85Hz */
486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 214750, 1680, 1808,
487 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
488 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
489 /* 0x3d - 1680x1050@120Hz RB */
490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER
, 245500, 1680, 1728,
491 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
492 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
493 /* 0x3e - 1792x1344@60Hz */
494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER
, 204750, 1792, 1920,
495 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
496 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
497 /* 0x3f - 1792x1344@75Hz */
498 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER
, 261000, 1792, 1888,
499 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
500 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
501 /* 0x40 - 1792x1344@120Hz RB */
502 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER
, 333250, 1792, 1840,
503 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
504 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
505 /* 0x41 - 1856x1392@60Hz */
506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER
, 218250, 1856, 1952,
507 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
508 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
509 /* 0x42 - 1856x1392@75Hz */
510 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER
, 288000, 1856, 1984,
511 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
512 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
513 /* 0x43 - 1856x1392@120Hz RB */
514 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER
, 356500, 1856, 1904,
515 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
516 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
517 /* 0x52 - 1920x1080@60Hz */
518 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2008,
519 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
520 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
521 /* 0x44 - 1920x1200@60Hz RB */
522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 154000, 1920, 1968,
523 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
524 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
525 /* 0x45 - 1920x1200@60Hz */
526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 193250, 1920, 2056,
527 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
528 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
529 /* 0x46 - 1920x1200@75Hz */
530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 245250, 1920, 2056,
531 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
532 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
533 /* 0x47 - 1920x1200@85Hz */
534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 281250, 1920, 2064,
535 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
536 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
537 /* 0x48 - 1920x1200@120Hz RB */
538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER
, 317000, 1920, 1968,
539 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
540 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
541 /* 0x49 - 1920x1440@60Hz */
542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER
, 234000, 1920, 2048,
543 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
544 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
545 /* 0x4a - 1920x1440@75Hz */
546 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2064,
547 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
548 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
549 /* 0x4b - 1920x1440@120Hz RB */
550 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER
, 380500, 1920, 1968,
551 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
552 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
553 /* 0x54 - 2048x1152@60Hz */
554 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER
, 162000, 2048, 2074,
555 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
556 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
557 /* 0x4c - 2560x1600@60Hz RB */
558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 268500, 2560, 2608,
559 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
560 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
561 /* 0x4d - 2560x1600@60Hz */
562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 348500, 2560, 2752,
563 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
564 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
565 /* 0x4e - 2560x1600@75Hz */
566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 443250, 2560, 2768,
567 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
568 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
569 /* 0x4f - 2560x1600@85Hz */
570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 505250, 2560, 2768,
571 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
572 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) },
573 /* 0x50 - 2560x1600@120Hz RB */
574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER
, 552750, 2560, 2608,
575 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
576 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
577 /* 0x57 - 4096x2160@60Hz RB */
578 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 556744, 4096, 4104,
579 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
580 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
581 /* 0x58 - 4096x2160@59.94Hz RB */
582 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 556188, 4096, 4104,
583 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
584 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
) },
588 * These more or less come from the DMT spec. The 720x400 modes are
589 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
590 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
591 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
594 * The DMT modes have been fact-checked; the rest are mild guesses.
596 static const struct drm_display_mode edid_est_modes
[] = {
597 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 40000, 800, 840,
598 968, 1056, 0, 600, 601, 605, 628, 0,
599 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@60Hz */
600 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 36000, 800, 824,
601 896, 1024, 0, 600, 601, 603, 625, 0,
602 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@56Hz */
603 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 656,
604 720, 840, 0, 480, 481, 484, 500, 0,
605 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@75Hz */
606 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 31500, 640, 664,
607 704, 832, 0, 480, 489, 492, 520, 0,
608 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@72Hz */
609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 30240, 640, 704,
610 768, 864, 0, 480, 483, 486, 525, 0,
611 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@67Hz */
612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
613 752, 800, 0, 480, 490, 492, 525, 0,
614 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 640x480@60Hz */
615 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 35500, 720, 738,
616 846, 900, 0, 400, 421, 423, 449, 0,
617 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 720x400@88Hz */
618 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER
, 28320, 720, 738,
619 846, 900, 0, 400, 412, 414, 449, 0,
620 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 720x400@70Hz */
621 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER
, 135000, 1280, 1296,
622 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
623 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 1280x1024@75Hz */
624 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 78750, 1024, 1040,
625 1136, 1312, 0, 768, 769, 772, 800, 0,
626 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 1024x768@75Hz */
627 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 75000, 1024, 1048,
628 1184, 1328, 0, 768, 771, 777, 806, 0,
629 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 1024x768@70Hz */
630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER
, 65000, 1024, 1048,
631 1184, 1344, 0, 768, 771, 777, 806, 0,
632 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 1024x768@60Hz */
633 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER
,44900, 1024, 1032,
634 1208, 1264, 0, 768, 768, 776, 817, 0,
635 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_INTERLACE
) }, /* 1024x768@43Hz */
636 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER
, 57284, 832, 864,
637 928, 1152, 0, 624, 625, 628, 667, 0,
638 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
) }, /* 832x624@75Hz */
639 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 49500, 800, 816,
640 896, 1056, 0, 600, 601, 604, 625, 0,
641 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@75Hz */
642 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER
, 50000, 800, 856,
643 976, 1040, 0, 600, 637, 643, 666, 0,
644 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 800x600@72Hz */
645 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER
, 108000, 1152, 1216,
646 1344, 1600, 0, 864, 865, 868, 900, 0,
647 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
) }, /* 1152x864@75Hz */
657 static const struct minimode est3_modes
[] = {
665 { 1024, 768, 85, 0 },
666 { 1152, 864, 75, 0 },
668 { 1280, 768, 60, 1 },
669 { 1280, 768, 60, 0 },
670 { 1280, 768, 75, 0 },
671 { 1280, 768, 85, 0 },
672 { 1280, 960, 60, 0 },
673 { 1280, 960, 85, 0 },
674 { 1280, 1024, 60, 0 },
675 { 1280, 1024, 85, 0 },
677 { 1360, 768, 60, 0 },
678 { 1440, 900, 60, 1 },
679 { 1440, 900, 60, 0 },
680 { 1440, 900, 75, 0 },
681 { 1440, 900, 85, 0 },
682 { 1400, 1050, 60, 1 },
683 { 1400, 1050, 60, 0 },
684 { 1400, 1050, 75, 0 },
686 { 1400, 1050, 85, 0 },
687 { 1680, 1050, 60, 1 },
688 { 1680, 1050, 60, 0 },
689 { 1680, 1050, 75, 0 },
690 { 1680, 1050, 85, 0 },
691 { 1600, 1200, 60, 0 },
692 { 1600, 1200, 65, 0 },
693 { 1600, 1200, 70, 0 },
695 { 1600, 1200, 75, 0 },
696 { 1600, 1200, 85, 0 },
697 { 1792, 1344, 60, 0 },
698 { 1792, 1344, 75, 0 },
699 { 1856, 1392, 60, 0 },
700 { 1856, 1392, 75, 0 },
701 { 1920, 1200, 60, 1 },
702 { 1920, 1200, 60, 0 },
704 { 1920, 1200, 75, 0 },
705 { 1920, 1200, 85, 0 },
706 { 1920, 1440, 60, 0 },
707 { 1920, 1440, 75, 0 },
710 static const struct minimode extra_modes
[] = {
711 { 1024, 576, 60, 0 },
712 { 1366, 768, 60, 0 },
713 { 1600, 900, 60, 0 },
714 { 1680, 945, 60, 0 },
715 { 1920, 1080, 60, 0 },
716 { 2048, 1152, 60, 0 },
717 { 2048, 1536, 60, 0 },
721 * Probably taken from CEA-861 spec.
722 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
724 * Index using the VIC.
726 static const struct drm_display_mode edid_cea_modes
[] = {
727 /* 0 - dummy, VICs start at 1 */
729 /* 1 - 640x480@60Hz 4:3 */
730 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER
, 25175, 640, 656,
731 752, 800, 0, 480, 490, 492, 525, 0,
732 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
733 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
734 /* 2 - 720x480@60Hz 4:3 */
735 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 27000, 720, 736,
736 798, 858, 0, 480, 489, 495, 525, 0,
737 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
738 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
739 /* 3 - 720x480@60Hz 16:9 */
740 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 27000, 720, 736,
741 798, 858, 0, 480, 489, 495, 525, 0,
742 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
743 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
744 /* 4 - 1280x720@60Hz 16:9 */
745 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1390,
746 1430, 1650, 0, 720, 725, 730, 750, 0,
747 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
748 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
749 /* 5 - 1920x1080i@60Hz 16:9 */
750 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2008,
751 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
752 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
753 DRM_MODE_FLAG_INTERLACE
),
754 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
755 /* 6 - 720(1440)x480i@60Hz 4:3 */
756 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
757 801, 858, 0, 480, 488, 494, 525, 0,
758 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
759 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
760 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
761 /* 7 - 720(1440)x480i@60Hz 16:9 */
762 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
763 801, 858, 0, 480, 488, 494, 525, 0,
764 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
765 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
766 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
767 /* 8 - 720(1440)x240@60Hz 4:3 */
768 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
769 801, 858, 0, 240, 244, 247, 262, 0,
770 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
771 DRM_MODE_FLAG_DBLCLK
),
772 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
773 /* 9 - 720(1440)x240@60Hz 16:9 */
774 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER
, 13500, 720, 739,
775 801, 858, 0, 240, 244, 247, 262, 0,
776 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
777 DRM_MODE_FLAG_DBLCLK
),
778 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
779 /* 10 - 2880x480i@60Hz 4:3 */
780 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
781 3204, 3432, 0, 480, 488, 494, 525, 0,
782 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
783 DRM_MODE_FLAG_INTERLACE
),
784 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
785 /* 11 - 2880x480i@60Hz 16:9 */
786 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
787 3204, 3432, 0, 480, 488, 494, 525, 0,
788 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
789 DRM_MODE_FLAG_INTERLACE
),
790 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
791 /* 12 - 2880x240@60Hz 4:3 */
792 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
793 3204, 3432, 0, 240, 244, 247, 262, 0,
794 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
795 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
796 /* 13 - 2880x240@60Hz 16:9 */
797 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2956,
798 3204, 3432, 0, 240, 244, 247, 262, 0,
799 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
800 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
801 /* 14 - 1440x480@60Hz 4:3 */
802 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1472,
803 1596, 1716, 0, 480, 489, 495, 525, 0,
804 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
805 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
806 /* 15 - 1440x480@60Hz 16:9 */
807 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1472,
808 1596, 1716, 0, 480, 489, 495, 525, 0,
809 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
810 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
811 /* 16 - 1920x1080@60Hz 16:9 */
812 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2008,
813 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
814 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
815 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
816 /* 17 - 720x576@50Hz 4:3 */
817 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
818 796, 864, 0, 576, 581, 586, 625, 0,
819 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
820 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
821 /* 18 - 720x576@50Hz 16:9 */
822 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
823 796, 864, 0, 576, 581, 586, 625, 0,
824 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
825 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
826 /* 19 - 1280x720@50Hz 16:9 */
827 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1720,
828 1760, 1980, 0, 720, 725, 730, 750, 0,
829 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
830 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
831 /* 20 - 1920x1080i@50Hz 16:9 */
832 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2448,
833 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
834 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
835 DRM_MODE_FLAG_INTERLACE
),
836 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
837 /* 21 - 720(1440)x576i@50Hz 4:3 */
838 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
839 795, 864, 0, 576, 580, 586, 625, 0,
840 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
841 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
842 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
843 /* 22 - 720(1440)x576i@50Hz 16:9 */
844 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
845 795, 864, 0, 576, 580, 586, 625, 0,
846 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
847 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
848 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
849 /* 23 - 720(1440)x288@50Hz 4:3 */
850 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
851 795, 864, 0, 288, 290, 293, 312, 0,
852 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
853 DRM_MODE_FLAG_DBLCLK
),
854 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
855 /* 24 - 720(1440)x288@50Hz 16:9 */
856 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER
, 13500, 720, 732,
857 795, 864, 0, 288, 290, 293, 312, 0,
858 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
859 DRM_MODE_FLAG_DBLCLK
),
860 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
861 /* 25 - 2880x576i@50Hz 4:3 */
862 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
863 3180, 3456, 0, 576, 580, 586, 625, 0,
864 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
865 DRM_MODE_FLAG_INTERLACE
),
866 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
867 /* 26 - 2880x576i@50Hz 16:9 */
868 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
869 3180, 3456, 0, 576, 580, 586, 625, 0,
870 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
871 DRM_MODE_FLAG_INTERLACE
),
872 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
873 /* 27 - 2880x288@50Hz 4:3 */
874 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
875 3180, 3456, 0, 288, 290, 293, 312, 0,
876 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
877 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
878 /* 28 - 2880x288@50Hz 16:9 */
879 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER
, 54000, 2880, 2928,
880 3180, 3456, 0, 288, 290, 293, 312, 0,
881 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
882 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
883 /* 29 - 1440x576@50Hz 4:3 */
884 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1464,
885 1592, 1728, 0, 576, 581, 586, 625, 0,
886 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
887 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
888 /* 30 - 1440x576@50Hz 16:9 */
889 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER
, 54000, 1440, 1464,
890 1592, 1728, 0, 576, 581, 586, 625, 0,
891 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
892 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
893 /* 31 - 1920x1080@50Hz 16:9 */
894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2448,
895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
896 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
897 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
898 /* 32 - 1920x1080@24Hz 16:9 */
899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2558,
900 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
902 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
903 /* 33 - 1920x1080@25Hz 16:9 */
904 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2448,
905 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
906 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
907 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
908 /* 34 - 1920x1080@30Hz 16:9 */
909 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2008,
910 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
911 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
912 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
913 /* 35 - 2880x480@60Hz 4:3 */
914 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2944,
915 3192, 3432, 0, 480, 489, 495, 525, 0,
916 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
917 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
918 /* 36 - 2880x480@60Hz 16:9 */
919 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2944,
920 3192, 3432, 0, 480, 489, 495, 525, 0,
921 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
922 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
923 /* 37 - 2880x576@50Hz 4:3 */
924 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2928,
925 3184, 3456, 0, 576, 581, 586, 625, 0,
926 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
927 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
928 /* 38 - 2880x576@50Hz 16:9 */
929 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER
, 108000, 2880, 2928,
930 3184, 3456, 0, 576, 581, 586, 625, 0,
931 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
932 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
933 /* 39 - 1920x1080i@50Hz 16:9 */
934 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 72000, 1920, 1952,
935 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
936 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NVSYNC
|
937 DRM_MODE_FLAG_INTERLACE
),
938 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
939 /* 40 - 1920x1080i@100Hz 16:9 */
940 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2448,
941 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
942 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
943 DRM_MODE_FLAG_INTERLACE
),
944 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
945 /* 41 - 1280x720@100Hz 16:9 */
946 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1720,
947 1760, 1980, 0, 720, 725, 730, 750, 0,
948 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
949 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
950 /* 42 - 720x576@100Hz 4:3 */
951 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
952 796, 864, 0, 576, 581, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
954 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
955 /* 43 - 720x576@100Hz 16:9 */
956 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
957 796, 864, 0, 576, 581, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
959 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
960 /* 44 - 720(1440)x576i@100Hz 4:3 */
961 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
962 795, 864, 0, 576, 580, 586, 625, 0,
963 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
964 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
965 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
966 /* 45 - 720(1440)x576i@100Hz 16:9 */
967 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 732,
968 795, 864, 0, 576, 580, 586, 625, 0,
969 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
970 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
971 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
972 /* 46 - 1920x1080i@120Hz 16:9 */
973 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2008,
974 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
975 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
|
976 DRM_MODE_FLAG_INTERLACE
),
977 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
978 /* 47 - 1280x720@120Hz 16:9 */
979 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1390,
980 1430, 1650, 0, 720, 725, 730, 750, 0,
981 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
982 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
983 /* 48 - 720x480@120Hz 4:3 */
984 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 54000, 720, 736,
985 798, 858, 0, 480, 489, 495, 525, 0,
986 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
987 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
988 /* 49 - 720x480@120Hz 16:9 */
989 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 54000, 720, 736,
990 798, 858, 0, 480, 489, 495, 525, 0,
991 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
992 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
993 /* 50 - 720(1440)x480i@120Hz 4:3 */
994 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 739,
995 801, 858, 0, 480, 488, 494, 525, 0,
996 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
997 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
998 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
999 /* 51 - 720(1440)x480i@120Hz 16:9 */
1000 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 27000, 720, 739,
1001 801, 858, 0, 480, 488, 494, 525, 0,
1002 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
1003 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
1004 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1005 /* 52 - 720x576@200Hz 4:3 */
1006 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 108000, 720, 732,
1007 796, 864, 0, 576, 581, 586, 625, 0,
1008 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
1009 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
1010 /* 53 - 720x576@200Hz 16:9 */
1011 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER
, 108000, 720, 732,
1012 796, 864, 0, 576, 581, 586, 625, 0,
1013 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
1014 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1015 /* 54 - 720(1440)x576i@200Hz 4:3 */
1016 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
1017 795, 864, 0, 576, 580, 586, 625, 0,
1018 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
1019 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
1020 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
1021 /* 55 - 720(1440)x576i@200Hz 16:9 */
1022 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 732,
1023 795, 864, 0, 576, 580, 586, 625, 0,
1024 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
1025 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
1026 .vrefresh
= 200, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1027 /* 56 - 720x480@240Hz 4:3 */
1028 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 108000, 720, 736,
1029 798, 858, 0, 480, 489, 495, 525, 0,
1030 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
1031 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
1032 /* 57 - 720x480@240Hz 16:9 */
1033 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER
, 108000, 720, 736,
1034 798, 858, 0, 480, 489, 495, 525, 0,
1035 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
1036 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1037 /* 58 - 720(1440)x480i@240Hz 4:3 */
1038 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 739,
1039 801, 858, 0, 480, 488, 494, 525, 0,
1040 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
1041 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
1042 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_4_3
, },
1043 /* 59 - 720(1440)x480i@240Hz 16:9 */
1044 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER
, 54000, 720, 739,
1045 801, 858, 0, 480, 488, 494, 525, 0,
1046 DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
|
1047 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_DBLCLK
),
1048 .vrefresh
= 240, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1049 /* 60 - 1280x720@24Hz 16:9 */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 59400, 1280, 3040,
1051 3080, 3300, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1053 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1054 /* 61 - 1280x720@25Hz 16:9 */
1055 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 3700,
1056 3740, 3960, 0, 720, 725, 730, 750, 0,
1057 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1058 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1059 /* 62 - 1280x720@30Hz 16:9 */
1060 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 3040,
1061 3080, 3300, 0, 720, 725, 730, 750, 0,
1062 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1063 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1064 /* 63 - 1920x1080@120Hz 16:9 */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2008,
1066 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1068 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1069 /* 64 - 1920x1080@100Hz 16:9 */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2448,
1071 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1073 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1074 /* 65 - 1280x720@24Hz 64:27 */
1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 59400, 1280, 3040,
1076 3080, 3300, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1078 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1079 /* 66 - 1280x720@25Hz 64:27 */
1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 3700,
1081 3740, 3960, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1083 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1084 /* 67 - 1280x720@30Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 3040,
1086 3080, 3300, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1088 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1089 /* 68 - 1280x720@50Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1720,
1091 1760, 1980, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1093 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1094 /* 69 - 1280x720@60Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 74250, 1280, 1390,
1096 1430, 1650, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1098 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1099 /* 70 - 1280x720@100Hz 64:27 */
1100 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1720,
1101 1760, 1980, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1103 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1104 /* 71 - 1280x720@120Hz 64:27 */
1105 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER
, 148500, 1280, 1390,
1106 1430, 1650, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1108 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1109 /* 72 - 1920x1080@24Hz 64:27 */
1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2558,
1111 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1112 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1113 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1114 /* 73 - 1920x1080@25Hz 64:27 */
1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2448,
1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1118 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1119 /* 74 - 1920x1080@30Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 74250, 1920, 2008,
1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1123 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1124 /* 75 - 1920x1080@50Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1128 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1129 /* 76 - 1920x1080@60Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 148500, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1133 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1134 /* 77 - 1920x1080@100Hz 64:27 */
1135 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2448,
1136 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1138 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1139 /* 78 - 1920x1080@120Hz 64:27 */
1140 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER
, 297000, 1920, 2008,
1141 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1142 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1143 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1144 /* 79 - 1680x720@24Hz 64:27 */
1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER
, 59400, 1680, 3040,
1146 3080, 3300, 0, 720, 725, 730, 750, 0,
1147 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1148 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1149 /* 80 - 1680x720@25Hz 64:27 */
1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER
, 59400, 1680, 2908,
1151 2948, 3168, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1153 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1154 /* 81 - 1680x720@30Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER
, 59400, 1680, 2380,
1156 2420, 2640, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1158 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1159 /* 82 - 1680x720@50Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER
, 82500, 1680, 1940,
1161 1980, 2200, 0, 720, 725, 730, 750, 0,
1162 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1163 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1164 /* 83 - 1680x720@60Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER
, 99000, 1680, 1940,
1166 1980, 2200, 0, 720, 725, 730, 750, 0,
1167 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1168 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1169 /* 84 - 1680x720@100Hz 64:27 */
1170 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER
, 165000, 1680, 1740,
1171 1780, 2000, 0, 720, 725, 730, 825, 0,
1172 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1173 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1174 /* 85 - 1680x720@120Hz 64:27 */
1175 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER
, 198000, 1680, 1740,
1176 1780, 2000, 0, 720, 725, 730, 825, 0,
1177 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1178 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1179 /* 86 - 2560x1080@24Hz 64:27 */
1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER
, 99000, 2560, 3558,
1181 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1182 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1183 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1184 /* 87 - 2560x1080@25Hz 64:27 */
1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER
, 90000, 2560, 3008,
1186 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1187 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1188 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1189 /* 88 - 2560x1080@30Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER
, 118800, 2560, 3328,
1191 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1192 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1193 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1194 /* 89 - 2560x1080@50Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER
, 185625, 2560, 3108,
1196 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1197 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1198 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1199 /* 90 - 2560x1080@60Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER
, 198000, 2560, 2808,
1201 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1202 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1203 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1204 /* 91 - 2560x1080@100Hz 64:27 */
1205 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER
, 371250, 2560, 2778,
1206 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1207 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1208 .vrefresh
= 100, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1209 /* 92 - 2560x1080@120Hz 64:27 */
1210 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER
, 495000, 2560, 3108,
1211 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1212 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1213 .vrefresh
= 120, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1214 /* 93 - 3840x2160@24Hz 16:9 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000, 3840, 5116,
1216 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1218 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1219 /* 94 - 3840x2160@25Hz 16:9 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1223 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1224 /* 95 - 3840x2160@30Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1228 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1229 /* 96 - 3840x2160@50Hz 16:9 */
1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 594000, 3840, 4896,
1231 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1233 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1234 /* 97 - 3840x2160@60Hz 16:9 */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 594000, 3840, 4016,
1236 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1238 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_16_9
, },
1239 /* 98 - 4096x2160@24Hz 256:135 */
1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 297000, 4096, 5116,
1241 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1243 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_256_135
, },
1244 /* 99 - 4096x2160@25Hz 256:135 */
1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 297000, 4096, 5064,
1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1248 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_256_135
, },
1249 /* 100 - 4096x2160@30Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 297000, 4096, 4184,
1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1253 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_256_135
, },
1254 /* 101 - 4096x2160@50Hz 256:135 */
1255 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 594000, 4096, 5064,
1256 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1258 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_256_135
, },
1259 /* 102 - 4096x2160@60Hz 256:135 */
1260 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 594000, 4096, 4184,
1261 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1263 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_256_135
, },
1264 /* 103 - 3840x2160@24Hz 64:27 */
1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000, 3840, 5116,
1266 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1268 .vrefresh
= 24, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1269 /* 104 - 3840x2160@25Hz 64:27 */
1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000, 3840, 4896,
1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1273 .vrefresh
= 25, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1274 /* 105 - 3840x2160@30Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000, 3840, 4016,
1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1278 .vrefresh
= 30, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1279 /* 106 - 3840x2160@50Hz 64:27 */
1280 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 594000, 3840, 4896,
1281 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1282 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1283 .vrefresh
= 50, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1284 /* 107 - 3840x2160@60Hz 64:27 */
1285 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 594000, 3840, 4016,
1286 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1287 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1288 .vrefresh
= 60, .picture_aspect_ratio
= HDMI_PICTURE_ASPECT_64_27
, },
1292 * HDMI 1.4 4k modes. Index using the VIC.
1294 static const struct drm_display_mode edid_4k_modes
[] = {
1295 /* 0 - dummy, VICs start at 1 */
1297 /* 1 - 3840x2160@30Hz */
1298 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1299 3840, 4016, 4104, 4400, 0,
1300 2160, 2168, 2178, 2250, 0,
1301 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1303 /* 2 - 3840x2160@25Hz */
1304 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1305 3840, 4896, 4984, 5280, 0,
1306 2160, 2168, 2178, 2250, 0,
1307 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1309 /* 3 - 3840x2160@24Hz */
1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1311 3840, 5116, 5204, 5500, 0,
1312 2160, 2168, 2178, 2250, 0,
1313 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1315 /* 4 - 4096x2160@24Hz (SMPTE) */
1316 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER
, 297000,
1317 4096, 5116, 5204, 5500, 0,
1318 2160, 2168, 2178, 2250, 0,
1319 DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_PVSYNC
),
1323 /*** DDC fetch and block validation ***/
1325 static const u8 edid_header
[] = {
1326 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1330 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1331 * @raw_edid: pointer to raw base EDID block
1333 * Sanity check the header of the base EDID block.
1335 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1337 int drm_edid_header_is_valid(const u8
*raw_edid
)
1341 for (i
= 0; i
< sizeof(edid_header
); i
++)
1342 if (raw_edid
[i
] == edid_header
[i
])
1347 EXPORT_SYMBOL(drm_edid_header_is_valid
);
1349 static int edid_fixup __read_mostly
= 6;
1350 module_param_named(edid_fixup
, edid_fixup
, int, 0400);
1351 MODULE_PARM_DESC(edid_fixup
,
1352 "Minimum number of valid EDID header bytes (0-8, default 6)");
1354 static void drm_get_displayid(struct drm_connector
*connector
,
1356 static int validate_displayid(u8
*displayid
, int length
, int idx
);
1358 static int drm_edid_block_checksum(const u8
*raw_edid
)
1362 for (i
= 0; i
< EDID_LENGTH
; i
++)
1363 csum
+= raw_edid
[i
];
1368 static bool drm_edid_is_zero(const u8
*in_edid
, int length
)
1370 if (memchr_inv(in_edid
, 0, length
))
1377 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1378 * @raw_edid: pointer to raw EDID block
1379 * @block: type of block to validate (0 for base, extension otherwise)
1380 * @print_bad_edid: if true, dump bad EDID blocks to the console
1381 * @edid_corrupt: if true, the header or checksum is invalid
1383 * Validate a base or extension EDID block and optionally dump bad blocks to
1386 * Return: True if the block is valid, false otherwise.
1388 bool drm_edid_block_valid(u8
*raw_edid
, int block
, bool print_bad_edid
,
1392 struct edid
*edid
= (struct edid
*)raw_edid
;
1394 if (WARN_ON(!raw_edid
))
1397 if (edid_fixup
> 8 || edid_fixup
< 0)
1401 int score
= drm_edid_header_is_valid(raw_edid
);
1404 *edid_corrupt
= false;
1405 } else if (score
>= edid_fixup
) {
1406 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1407 * The corrupt flag needs to be set here otherwise, the
1408 * fix-up code here will correct the problem, the
1409 * checksum is correct and the test fails
1412 *edid_corrupt
= true;
1413 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1414 memcpy(raw_edid
, edid_header
, sizeof(edid_header
));
1417 *edid_corrupt
= true;
1422 csum
= drm_edid_block_checksum(raw_edid
);
1425 *edid_corrupt
= true;
1427 /* allow CEA to slide through, switches mangle this */
1428 if (raw_edid
[0] == CEA_EXT
) {
1429 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum
);
1430 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1433 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum
);
1439 /* per-block-type checks */
1440 switch (raw_edid
[0]) {
1442 if (edid
->version
!= 1) {
1443 DRM_NOTE("EDID has major version %d, instead of 1\n", edid
->version
);
1447 if (edid
->revision
> 4)
1448 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1458 if (print_bad_edid
) {
1459 if (drm_edid_is_zero(raw_edid
, EDID_LENGTH
)) {
1460 pr_notice("EDID block is all zeroes\n");
1462 pr_notice("Raw EDID:\n");
1463 print_hex_dump(KERN_NOTICE
,
1464 " \t", DUMP_PREFIX_NONE
, 16, 1,
1465 raw_edid
, EDID_LENGTH
, false);
1470 EXPORT_SYMBOL(drm_edid_block_valid
);
1473 * drm_edid_is_valid - sanity check EDID data
1476 * Sanity-check an entire EDID record (including extensions)
1478 * Return: True if the EDID data is valid, false otherwise.
1480 bool drm_edid_is_valid(struct edid
*edid
)
1483 u8
*raw
= (u8
*)edid
;
1488 for (i
= 0; i
<= edid
->extensions
; i
++)
1489 if (!drm_edid_block_valid(raw
+ i
* EDID_LENGTH
, i
, true, NULL
))
1494 EXPORT_SYMBOL(drm_edid_is_valid
);
1496 #define DDC_SEGMENT_ADDR 0x30
1498 * drm_do_probe_ddc_edid() - get EDID information via I2C
1499 * @data: I2C device adapter
1500 * @buf: EDID data buffer to be filled
1501 * @block: 128 byte EDID block to start fetching from
1502 * @len: EDID data buffer length to fetch
1504 * Try to fetch EDID information by calling I2C driver functions.
1506 * Return: 0 on success or -1 on failure.
1509 drm_do_probe_ddc_edid(void *data
, u8
*buf
, unsigned int block
, size_t len
)
1511 struct i2c_adapter
*adapter
= data
;
1512 unsigned char start
= block
* EDID_LENGTH
;
1513 unsigned char segment
= block
>> 1;
1514 unsigned char xfers
= segment
? 3 : 2;
1515 int ret
, retries
= 5;
1518 * The core I2C driver will automatically retry the transfer if the
1519 * adapter reports EAGAIN. However, we find that bit-banging transfers
1520 * are susceptible to errors under a heavily loaded machine and
1521 * generate spurious NAKs and timeouts. Retrying the transfer
1522 * of the individual block a few times seems to overcome this.
1525 struct i2c_msg msgs
[] = {
1527 .addr
= DDC_SEGMENT_ADDR
,
1545 * Avoid sending the segment addr to not upset non-compliant
1548 ret
= i2c_transfer(adapter
, &msgs
[3 - xfers
], xfers
);
1550 if (ret
== -ENXIO
) {
1551 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1555 } while (ret
!= xfers
&& --retries
);
1557 return ret
== xfers
? 0 : -1;
1560 static void connector_bad_edid(struct drm_connector
*connector
,
1561 u8
*edid
, int num_blocks
)
1565 if (connector
->bad_edid_counter
++ && !(drm_debug
& DRM_UT_KMS
))
1568 dev_warn(connector
->dev
->dev
,
1569 "%s: EDID is invalid:\n",
1571 for (i
= 0; i
< num_blocks
; i
++) {
1572 u8
*block
= edid
+ i
* EDID_LENGTH
;
1575 if (drm_edid_is_zero(block
, EDID_LENGTH
))
1576 sprintf(prefix
, "\t[%02x] ZERO ", i
);
1577 else if (!drm_edid_block_valid(block
, i
, false, NULL
))
1578 sprintf(prefix
, "\t[%02x] BAD ", i
);
1580 sprintf(prefix
, "\t[%02x] GOOD ", i
);
1582 print_hex_dump(KERN_WARNING
,
1583 prefix
, DUMP_PREFIX_NONE
, 16, 1,
1584 block
, EDID_LENGTH
, false);
1588 /* Get override or firmware EDID */
1589 static struct edid
*drm_get_override_edid(struct drm_connector
*connector
)
1591 struct edid
*override
= NULL
;
1593 if (connector
->override_edid
)
1594 override
= drm_edid_duplicate(connector
->edid_blob_ptr
->data
);
1597 override
= drm_load_edid_firmware(connector
);
1599 return IS_ERR(override
) ? NULL
: override
;
1603 * drm_add_override_edid_modes - add modes from override/firmware EDID
1604 * @connector: connector we're probing
1606 * Add modes from the override/firmware EDID, if available. Only to be used from
1607 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1608 * failed during drm_get_edid() and caused the override/firmware EDID to be
1611 * Return: The number of modes added or 0 if we couldn't find any.
1613 int drm_add_override_edid_modes(struct drm_connector
*connector
)
1615 struct edid
*override
;
1618 override
= drm_get_override_edid(connector
);
1620 drm_connector_update_edid_property(connector
, override
);
1621 num_modes
= drm_add_edid_modes(connector
, override
);
1624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1625 connector
->base
.id
, connector
->name
, num_modes
);
1630 EXPORT_SYMBOL(drm_add_override_edid_modes
);
1633 * drm_do_get_edid - get EDID data using a custom EDID block read function
1634 * @connector: connector we're probing
1635 * @get_edid_block: EDID block read function
1636 * @data: private data passed to the block read function
1638 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1639 * exposes a different interface to read EDID blocks this function can be used
1640 * to get EDID data using a custom block read function.
1642 * As in the general case the DDC bus is accessible by the kernel at the I2C
1643 * level, drivers must make all reasonable efforts to expose it as an I2C
1644 * adapter and use drm_get_edid() instead of abusing this function.
1646 * The EDID may be overridden using debugfs override_edid or firmare EDID
1647 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1648 * order. Having either of them bypasses actual EDID reads.
1650 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1652 struct edid
*drm_do_get_edid(struct drm_connector
*connector
,
1653 int (*get_edid_block
)(void *data
, u8
*buf
, unsigned int block
,
1657 int i
, j
= 0, valid_extensions
= 0;
1659 struct edid
*override
;
1661 override
= drm_get_override_edid(connector
);
1665 if ((edid
= kmalloc(EDID_LENGTH
, GFP_KERNEL
)) == NULL
)
1668 /* base block fetch */
1669 for (i
= 0; i
< 4; i
++) {
1670 if (get_edid_block(data
, edid
, 0, EDID_LENGTH
))
1672 if (drm_edid_block_valid(edid
, 0, false,
1673 &connector
->edid_corrupt
))
1675 if (i
== 0 && drm_edid_is_zero(edid
, EDID_LENGTH
)) {
1676 connector
->null_edid_counter
++;
1683 /* if there's no extensions, we're done */
1684 valid_extensions
= edid
[0x7e];
1685 if (valid_extensions
== 0)
1686 return (struct edid
*)edid
;
1688 new = krealloc(edid
, (valid_extensions
+ 1) * EDID_LENGTH
, GFP_KERNEL
);
1693 for (j
= 1; j
<= edid
[0x7e]; j
++) {
1694 u8
*block
= edid
+ j
* EDID_LENGTH
;
1696 for (i
= 0; i
< 4; i
++) {
1697 if (get_edid_block(data
, block
, j
, EDID_LENGTH
))
1699 if (drm_edid_block_valid(block
, j
, false, NULL
))
1707 if (valid_extensions
!= edid
[0x7e]) {
1710 connector_bad_edid(connector
, edid
, edid
[0x7e] + 1);
1712 edid
[EDID_LENGTH
-1] += edid
[0x7e] - valid_extensions
;
1713 edid
[0x7e] = valid_extensions
;
1715 new = kmalloc_array(valid_extensions
+ 1, EDID_LENGTH
,
1721 for (i
= 0; i
<= edid
[0x7e]; i
++) {
1722 u8
*block
= edid
+ i
* EDID_LENGTH
;
1724 if (!drm_edid_block_valid(block
, i
, false, NULL
))
1727 memcpy(base
, block
, EDID_LENGTH
);
1728 base
+= EDID_LENGTH
;
1735 return (struct edid
*)edid
;
1738 connector_bad_edid(connector
, edid
, 1);
1743 EXPORT_SYMBOL_GPL(drm_do_get_edid
);
1746 * drm_probe_ddc() - probe DDC presence
1747 * @adapter: I2C adapter to probe
1749 * Return: True on success, false on failure.
1752 drm_probe_ddc(struct i2c_adapter
*adapter
)
1756 return (drm_do_probe_ddc_edid(adapter
, &out
, 0, 1) == 0);
1758 EXPORT_SYMBOL(drm_probe_ddc
);
1761 * drm_get_edid - get EDID data, if available
1762 * @connector: connector we're probing
1763 * @adapter: I2C adapter to use for DDC
1765 * Poke the given I2C channel to grab EDID data if possible. If found,
1766 * attach it to the connector.
1768 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1770 struct edid
*drm_get_edid(struct drm_connector
*connector
,
1771 struct i2c_adapter
*adapter
)
1775 if (connector
->force
== DRM_FORCE_OFF
)
1778 if (connector
->force
== DRM_FORCE_UNSPECIFIED
&& !drm_probe_ddc(adapter
))
1781 edid
= drm_do_get_edid(connector
, drm_do_probe_ddc_edid
, adapter
);
1783 drm_get_displayid(connector
, edid
);
1786 EXPORT_SYMBOL(drm_get_edid
);
1789 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1790 * @connector: connector we're probing
1791 * @adapter: I2C adapter to use for DDC
1793 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1794 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1795 * switch DDC to the GPU which is retrieving EDID.
1797 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1799 struct edid
*drm_get_edid_switcheroo(struct drm_connector
*connector
,
1800 struct i2c_adapter
*adapter
)
1802 struct pci_dev
*pdev
= connector
->dev
->pdev
;
1805 vga_switcheroo_lock_ddc(pdev
);
1806 edid
= drm_get_edid(connector
, adapter
);
1807 vga_switcheroo_unlock_ddc(pdev
);
1811 EXPORT_SYMBOL(drm_get_edid_switcheroo
);
1814 * drm_edid_duplicate - duplicate an EDID and the extensions
1815 * @edid: EDID to duplicate
1817 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1819 struct edid
*drm_edid_duplicate(const struct edid
*edid
)
1821 return kmemdup(edid
, (edid
->extensions
+ 1) * EDID_LENGTH
, GFP_KERNEL
);
1823 EXPORT_SYMBOL(drm_edid_duplicate
);
1825 /*** EDID parsing ***/
1828 * edid_vendor - match a string against EDID's obfuscated vendor field
1829 * @edid: EDID to match
1830 * @vendor: vendor string
1832 * Returns true if @vendor is in @edid, false otherwise
1834 static bool edid_vendor(const struct edid
*edid
, const char *vendor
)
1836 char edid_vendor
[3];
1838 edid_vendor
[0] = ((edid
->mfg_id
[0] & 0x7c) >> 2) + '@';
1839 edid_vendor
[1] = (((edid
->mfg_id
[0] & 0x3) << 3) |
1840 ((edid
->mfg_id
[1] & 0xe0) >> 5)) + '@';
1841 edid_vendor
[2] = (edid
->mfg_id
[1] & 0x1f) + '@';
1843 return !strncmp(edid_vendor
, vendor
, 3);
1847 * edid_get_quirks - return quirk flags for a given EDID
1848 * @edid: EDID to process
1850 * This tells subsequent routines what fixes they need to apply.
1852 static u32
edid_get_quirks(const struct edid
*edid
)
1854 const struct edid_quirk
*quirk
;
1857 for (i
= 0; i
< ARRAY_SIZE(edid_quirk_list
); i
++) {
1858 quirk
= &edid_quirk_list
[i
];
1860 if (edid_vendor(edid
, quirk
->vendor
) &&
1861 (EDID_PRODUCT_ID(edid
) == quirk
->product_id
))
1862 return quirk
->quirks
;
1868 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1869 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1872 * edid_fixup_preferred - set preferred modes based on quirk list
1873 * @connector: has mode list to fix up
1874 * @quirks: quirks list
1876 * Walk the mode list for @connector, clearing the preferred status
1877 * on existing modes and setting it anew for the right mode ala @quirks.
1879 static void edid_fixup_preferred(struct drm_connector
*connector
,
1882 struct drm_display_mode
*t
, *cur_mode
, *preferred_mode
;
1883 int target_refresh
= 0;
1884 int cur_vrefresh
, preferred_vrefresh
;
1886 if (list_empty(&connector
->probed_modes
))
1889 if (quirks
& EDID_QUIRK_PREFER_LARGE_60
)
1890 target_refresh
= 60;
1891 if (quirks
& EDID_QUIRK_PREFER_LARGE_75
)
1892 target_refresh
= 75;
1894 preferred_mode
= list_first_entry(&connector
->probed_modes
,
1895 struct drm_display_mode
, head
);
1897 list_for_each_entry_safe(cur_mode
, t
, &connector
->probed_modes
, head
) {
1898 cur_mode
->type
&= ~DRM_MODE_TYPE_PREFERRED
;
1900 if (cur_mode
== preferred_mode
)
1903 /* Largest mode is preferred */
1904 if (MODE_SIZE(cur_mode
) > MODE_SIZE(preferred_mode
))
1905 preferred_mode
= cur_mode
;
1907 cur_vrefresh
= cur_mode
->vrefresh
?
1908 cur_mode
->vrefresh
: drm_mode_vrefresh(cur_mode
);
1909 preferred_vrefresh
= preferred_mode
->vrefresh
?
1910 preferred_mode
->vrefresh
: drm_mode_vrefresh(preferred_mode
);
1911 /* At a given size, try to get closest to target refresh */
1912 if ((MODE_SIZE(cur_mode
) == MODE_SIZE(preferred_mode
)) &&
1913 MODE_REFRESH_DIFF(cur_vrefresh
, target_refresh
) <
1914 MODE_REFRESH_DIFF(preferred_vrefresh
, target_refresh
)) {
1915 preferred_mode
= cur_mode
;
1919 preferred_mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
1923 mode_is_rb(const struct drm_display_mode
*mode
)
1925 return (mode
->htotal
- mode
->hdisplay
== 160) &&
1926 (mode
->hsync_end
- mode
->hdisplay
== 80) &&
1927 (mode
->hsync_end
- mode
->hsync_start
== 32) &&
1928 (mode
->vsync_start
- mode
->vdisplay
== 3);
1932 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1933 * @dev: Device to duplicate against
1934 * @hsize: Mode width
1935 * @vsize: Mode height
1936 * @fresh: Mode refresh rate
1937 * @rb: Mode reduced-blanking-ness
1939 * Walk the DMT mode list looking for a match for the given parameters.
1941 * Return: A newly allocated copy of the mode, or NULL if not found.
1943 struct drm_display_mode
*drm_mode_find_dmt(struct drm_device
*dev
,
1944 int hsize
, int vsize
, int fresh
,
1949 for (i
= 0; i
< ARRAY_SIZE(drm_dmt_modes
); i
++) {
1950 const struct drm_display_mode
*ptr
= &drm_dmt_modes
[i
];
1951 if (hsize
!= ptr
->hdisplay
)
1953 if (vsize
!= ptr
->vdisplay
)
1955 if (fresh
!= drm_mode_vrefresh(ptr
))
1957 if (rb
!= mode_is_rb(ptr
))
1960 return drm_mode_duplicate(dev
, ptr
);
1965 EXPORT_SYMBOL(drm_mode_find_dmt
);
1967 typedef void detailed_cb(struct detailed_timing
*timing
, void *closure
);
1970 cea_for_each_detailed_block(u8
*ext
, detailed_cb
*cb
, void *closure
)
1974 u8
*det_base
= ext
+ d
;
1977 for (i
= 0; i
< n
; i
++)
1978 cb((struct detailed_timing
*)(det_base
+ 18 * i
), closure
);
1982 vtb_for_each_detailed_block(u8
*ext
, detailed_cb
*cb
, void *closure
)
1984 unsigned int i
, n
= min((int)ext
[0x02], 6);
1985 u8
*det_base
= ext
+ 5;
1988 return; /* unknown version */
1990 for (i
= 0; i
< n
; i
++)
1991 cb((struct detailed_timing
*)(det_base
+ 18 * i
), closure
);
1995 drm_for_each_detailed_block(u8
*raw_edid
, detailed_cb
*cb
, void *closure
)
1998 struct edid
*edid
= (struct edid
*)raw_edid
;
2003 for (i
= 0; i
< EDID_DETAILED_TIMINGS
; i
++)
2004 cb(&(edid
->detailed_timings
[i
]), closure
);
2006 for (i
= 1; i
<= raw_edid
[0x7e]; i
++) {
2007 u8
*ext
= raw_edid
+ (i
* EDID_LENGTH
);
2010 cea_for_each_detailed_block(ext
, cb
, closure
);
2013 vtb_for_each_detailed_block(ext
, cb
, closure
);
2022 is_rb(struct detailed_timing
*t
, void *data
)
2025 if (r
[3] == EDID_DETAIL_MONITOR_RANGE
)
2027 *(bool *)data
= true;
2030 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2032 drm_monitor_supports_rb(struct edid
*edid
)
2034 if (edid
->revision
>= 4) {
2036 drm_for_each_detailed_block((u8
*)edid
, is_rb
, &ret
);
2040 return ((edid
->input
& DRM_EDID_INPUT_DIGITAL
) != 0);
2044 find_gtf2(struct detailed_timing
*t
, void *data
)
2047 if (r
[3] == EDID_DETAIL_MONITOR_RANGE
&& r
[10] == 0x02)
2051 /* Secondary GTF curve kicks in above some break frequency */
2053 drm_gtf2_hbreak(struct edid
*edid
)
2056 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
2057 return r
? (r
[12] * 2) : 0;
2061 drm_gtf2_2c(struct edid
*edid
)
2064 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
2065 return r
? r
[13] : 0;
2069 drm_gtf2_m(struct edid
*edid
)
2072 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
2073 return r
? (r
[15] << 8) + r
[14] : 0;
2077 drm_gtf2_k(struct edid
*edid
)
2080 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
2081 return r
? r
[16] : 0;
2085 drm_gtf2_2j(struct edid
*edid
)
2088 drm_for_each_detailed_block((u8
*)edid
, find_gtf2
, &r
);
2089 return r
? r
[17] : 0;
2093 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2094 * @edid: EDID block to scan
2096 static int standard_timing_level(struct edid
*edid
)
2098 if (edid
->revision
>= 2) {
2099 if (edid
->revision
>= 4 && (edid
->features
& DRM_EDID_FEATURE_DEFAULT_GTF
))
2101 if (drm_gtf2_hbreak(edid
))
2109 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2110 * monitors fill with ascii space (0x20) instead.
2113 bad_std_timing(u8 a
, u8 b
)
2115 return (a
== 0x00 && b
== 0x00) ||
2116 (a
== 0x01 && b
== 0x01) ||
2117 (a
== 0x20 && b
== 0x20);
2121 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2122 * @connector: connector of for the EDID block
2123 * @edid: EDID block to scan
2124 * @t: standard timing params
2126 * Take the standard timing params (in this case width, aspect, and refresh)
2127 * and convert them into a real mode using CVT/GTF/DMT.
2129 static struct drm_display_mode
*
2130 drm_mode_std(struct drm_connector
*connector
, struct edid
*edid
,
2131 struct std_timing
*t
)
2133 struct drm_device
*dev
= connector
->dev
;
2134 struct drm_display_mode
*m
, *mode
= NULL
;
2137 unsigned aspect_ratio
= (t
->vfreq_aspect
& EDID_TIMING_ASPECT_MASK
)
2138 >> EDID_TIMING_ASPECT_SHIFT
;
2139 unsigned vfreq
= (t
->vfreq_aspect
& EDID_TIMING_VFREQ_MASK
)
2140 >> EDID_TIMING_VFREQ_SHIFT
;
2141 int timing_level
= standard_timing_level(edid
);
2143 if (bad_std_timing(t
->hsize
, t
->vfreq_aspect
))
2146 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2147 hsize
= t
->hsize
* 8 + 248;
2148 /* vrefresh_rate = vfreq + 60 */
2149 vrefresh_rate
= vfreq
+ 60;
2150 /* the vdisplay is calculated based on the aspect ratio */
2151 if (aspect_ratio
== 0) {
2152 if (edid
->revision
< 3)
2155 vsize
= (hsize
* 10) / 16;
2156 } else if (aspect_ratio
== 1)
2157 vsize
= (hsize
* 3) / 4;
2158 else if (aspect_ratio
== 2)
2159 vsize
= (hsize
* 4) / 5;
2161 vsize
= (hsize
* 9) / 16;
2163 /* HDTV hack, part 1 */
2164 if (vrefresh_rate
== 60 &&
2165 ((hsize
== 1360 && vsize
== 765) ||
2166 (hsize
== 1368 && vsize
== 769))) {
2172 * If this connector already has a mode for this size and refresh
2173 * rate (because it came from detailed or CVT info), use that
2174 * instead. This way we don't have to guess at interlace or
2177 list_for_each_entry(m
, &connector
->probed_modes
, head
)
2178 if (m
->hdisplay
== hsize
&& m
->vdisplay
== vsize
&&
2179 drm_mode_vrefresh(m
) == vrefresh_rate
)
2182 /* HDTV hack, part 2 */
2183 if (hsize
== 1366 && vsize
== 768 && vrefresh_rate
== 60) {
2184 mode
= drm_cvt_mode(dev
, 1366, 768, vrefresh_rate
, 0, 0,
2188 mode
->hdisplay
= 1366;
2189 mode
->hsync_start
= mode
->hsync_start
- 1;
2190 mode
->hsync_end
= mode
->hsync_end
- 1;
2194 /* check whether it can be found in default mode table */
2195 if (drm_monitor_supports_rb(edid
)) {
2196 mode
= drm_mode_find_dmt(dev
, hsize
, vsize
, vrefresh_rate
,
2201 mode
= drm_mode_find_dmt(dev
, hsize
, vsize
, vrefresh_rate
, false);
2205 /* okay, generate it */
2206 switch (timing_level
) {
2210 mode
= drm_gtf_mode(dev
, hsize
, vsize
, vrefresh_rate
, 0, 0);
2214 * This is potentially wrong if there's ever a monitor with
2215 * more than one ranges section, each claiming a different
2216 * secondary GTF curve. Please don't do that.
2218 mode
= drm_gtf_mode(dev
, hsize
, vsize
, vrefresh_rate
, 0, 0);
2221 if (drm_mode_hsync(mode
) > drm_gtf2_hbreak(edid
)) {
2222 drm_mode_destroy(dev
, mode
);
2223 mode
= drm_gtf_mode_complex(dev
, hsize
, vsize
,
2224 vrefresh_rate
, 0, 0,
2232 mode
= drm_cvt_mode(dev
, hsize
, vsize
, vrefresh_rate
, 0, 0,
2240 * EDID is delightfully ambiguous about how interlaced modes are to be
2241 * encoded. Our internal representation is of frame height, but some
2242 * HDTV detailed timings are encoded as field height.
2244 * The format list here is from CEA, in frame size. Technically we
2245 * should be checking refresh rate too. Whatever.
2248 drm_mode_do_interlace_quirk(struct drm_display_mode
*mode
,
2249 struct detailed_pixel_timing
*pt
)
2252 static const struct {
2254 } cea_interlaced
[] = {
2264 if (!(pt
->misc
& DRM_EDID_PT_INTERLACED
))
2267 for (i
= 0; i
< ARRAY_SIZE(cea_interlaced
); i
++) {
2268 if ((mode
->hdisplay
== cea_interlaced
[i
].w
) &&
2269 (mode
->vdisplay
== cea_interlaced
[i
].h
/ 2)) {
2270 mode
->vdisplay
*= 2;
2271 mode
->vsync_start
*= 2;
2272 mode
->vsync_end
*= 2;
2278 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
2282 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2283 * @dev: DRM device (needed to create new mode)
2285 * @timing: EDID detailed timing info
2286 * @quirks: quirks to apply
2288 * An EDID detailed timing block contains enough info for us to create and
2289 * return a new struct drm_display_mode.
2291 static struct drm_display_mode
*drm_mode_detailed(struct drm_device
*dev
,
2293 struct detailed_timing
*timing
,
2296 struct drm_display_mode
*mode
;
2297 struct detailed_pixel_timing
*pt
= &timing
->data
.pixel_data
;
2298 unsigned hactive
= (pt
->hactive_hblank_hi
& 0xf0) << 4 | pt
->hactive_lo
;
2299 unsigned vactive
= (pt
->vactive_vblank_hi
& 0xf0) << 4 | pt
->vactive_lo
;
2300 unsigned hblank
= (pt
->hactive_hblank_hi
& 0xf) << 8 | pt
->hblank_lo
;
2301 unsigned vblank
= (pt
->vactive_vblank_hi
& 0xf) << 8 | pt
->vblank_lo
;
2302 unsigned hsync_offset
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0xc0) << 2 | pt
->hsync_offset_lo
;
2303 unsigned hsync_pulse_width
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0x30) << 4 | pt
->hsync_pulse_width_lo
;
2304 unsigned vsync_offset
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0xc) << 2 | pt
->vsync_offset_pulse_width_lo
>> 4;
2305 unsigned vsync_pulse_width
= (pt
->hsync_vsync_offset_pulse_width_hi
& 0x3) << 4 | (pt
->vsync_offset_pulse_width_lo
& 0xf);
2307 /* ignore tiny modes */
2308 if (hactive
< 64 || vactive
< 64)
2311 if (pt
->misc
& DRM_EDID_PT_STEREO
) {
2312 DRM_DEBUG_KMS("stereo mode not supported\n");
2315 if (!(pt
->misc
& DRM_EDID_PT_SEPARATE_SYNC
)) {
2316 DRM_DEBUG_KMS("composite sync not supported\n");
2319 /* it is incorrect if hsync/vsync width is zero */
2320 if (!hsync_pulse_width
|| !vsync_pulse_width
) {
2321 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2322 "Wrong Hsync/Vsync pulse width\n");
2326 if (quirks
& EDID_QUIRK_FORCE_REDUCED_BLANKING
) {
2327 mode
= drm_cvt_mode(dev
, hactive
, vactive
, 60, true, false, false);
2334 mode
= drm_mode_create(dev
);
2338 if (quirks
& EDID_QUIRK_135_CLOCK_TOO_HIGH
)
2339 timing
->pixel_clock
= cpu_to_le16(1088);
2341 mode
->clock
= le16_to_cpu(timing
->pixel_clock
) * 10;
2343 mode
->hdisplay
= hactive
;
2344 mode
->hsync_start
= mode
->hdisplay
+ hsync_offset
;
2345 mode
->hsync_end
= mode
->hsync_start
+ hsync_pulse_width
;
2346 mode
->htotal
= mode
->hdisplay
+ hblank
;
2348 mode
->vdisplay
= vactive
;
2349 mode
->vsync_start
= mode
->vdisplay
+ vsync_offset
;
2350 mode
->vsync_end
= mode
->vsync_start
+ vsync_pulse_width
;
2351 mode
->vtotal
= mode
->vdisplay
+ vblank
;
2353 /* Some EDIDs have bogus h/vtotal values */
2354 if (mode
->hsync_end
> mode
->htotal
)
2355 mode
->htotal
= mode
->hsync_end
+ 1;
2356 if (mode
->vsync_end
> mode
->vtotal
)
2357 mode
->vtotal
= mode
->vsync_end
+ 1;
2359 drm_mode_do_interlace_quirk(mode
, pt
);
2361 if (quirks
& EDID_QUIRK_DETAILED_SYNC_PP
) {
2362 pt
->misc
|= DRM_EDID_PT_HSYNC_POSITIVE
| DRM_EDID_PT_VSYNC_POSITIVE
;
2365 mode
->flags
|= (pt
->misc
& DRM_EDID_PT_HSYNC_POSITIVE
) ?
2366 DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
2367 mode
->flags
|= (pt
->misc
& DRM_EDID_PT_VSYNC_POSITIVE
) ?
2368 DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
2371 mode
->width_mm
= pt
->width_mm_lo
| (pt
->width_height_mm_hi
& 0xf0) << 4;
2372 mode
->height_mm
= pt
->height_mm_lo
| (pt
->width_height_mm_hi
& 0xf) << 8;
2374 if (quirks
& EDID_QUIRK_DETAILED_IN_CM
) {
2375 mode
->width_mm
*= 10;
2376 mode
->height_mm
*= 10;
2379 if (quirks
& EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE
) {
2380 mode
->width_mm
= edid
->width_cm
* 10;
2381 mode
->height_mm
= edid
->height_cm
* 10;
2384 mode
->type
= DRM_MODE_TYPE_DRIVER
;
2385 mode
->vrefresh
= drm_mode_vrefresh(mode
);
2386 drm_mode_set_name(mode
);
2392 mode_in_hsync_range(const struct drm_display_mode
*mode
,
2393 struct edid
*edid
, u8
*t
)
2395 int hsync
, hmin
, hmax
;
2398 if (edid
->revision
>= 4)
2399 hmin
+= ((t
[4] & 0x04) ? 255 : 0);
2401 if (edid
->revision
>= 4)
2402 hmax
+= ((t
[4] & 0x08) ? 255 : 0);
2403 hsync
= drm_mode_hsync(mode
);
2405 return (hsync
<= hmax
&& hsync
>= hmin
);
2409 mode_in_vsync_range(const struct drm_display_mode
*mode
,
2410 struct edid
*edid
, u8
*t
)
2412 int vsync
, vmin
, vmax
;
2415 if (edid
->revision
>= 4)
2416 vmin
+= ((t
[4] & 0x01) ? 255 : 0);
2418 if (edid
->revision
>= 4)
2419 vmax
+= ((t
[4] & 0x02) ? 255 : 0);
2420 vsync
= drm_mode_vrefresh(mode
);
2422 return (vsync
<= vmax
&& vsync
>= vmin
);
2426 range_pixel_clock(struct edid
*edid
, u8
*t
)
2429 if (t
[9] == 0 || t
[9] == 255)
2432 /* 1.4 with CVT support gives us real precision, yay */
2433 if (edid
->revision
>= 4 && t
[10] == 0x04)
2434 return (t
[9] * 10000) - ((t
[12] >> 2) * 250);
2436 /* 1.3 is pathetic, so fuzz up a bit */
2437 return t
[9] * 10000 + 5001;
2441 mode_in_range(const struct drm_display_mode
*mode
, struct edid
*edid
,
2442 struct detailed_timing
*timing
)
2445 u8
*t
= (u8
*)timing
;
2447 if (!mode_in_hsync_range(mode
, edid
, t
))
2450 if (!mode_in_vsync_range(mode
, edid
, t
))
2453 if ((max_clock
= range_pixel_clock(edid
, t
)))
2454 if (mode
->clock
> max_clock
)
2457 /* 1.4 max horizontal check */
2458 if (edid
->revision
>= 4 && t
[10] == 0x04)
2459 if (t
[13] && mode
->hdisplay
> 8 * (t
[13] + (256 * (t
[12]&0x3))))
2462 if (mode_is_rb(mode
) && !drm_monitor_supports_rb(edid
))
2468 static bool valid_inferred_mode(const struct drm_connector
*connector
,
2469 const struct drm_display_mode
*mode
)
2471 const struct drm_display_mode
*m
;
2474 list_for_each_entry(m
, &connector
->probed_modes
, head
) {
2475 if (mode
->hdisplay
== m
->hdisplay
&&
2476 mode
->vdisplay
== m
->vdisplay
&&
2477 drm_mode_vrefresh(mode
) == drm_mode_vrefresh(m
))
2478 return false; /* duplicated */
2479 if (mode
->hdisplay
<= m
->hdisplay
&&
2480 mode
->vdisplay
<= m
->vdisplay
)
2487 drm_dmt_modes_for_range(struct drm_connector
*connector
, struct edid
*edid
,
2488 struct detailed_timing
*timing
)
2491 struct drm_display_mode
*newmode
;
2492 struct drm_device
*dev
= connector
->dev
;
2494 for (i
= 0; i
< ARRAY_SIZE(drm_dmt_modes
); i
++) {
2495 if (mode_in_range(drm_dmt_modes
+ i
, edid
, timing
) &&
2496 valid_inferred_mode(connector
, drm_dmt_modes
+ i
)) {
2497 newmode
= drm_mode_duplicate(dev
, &drm_dmt_modes
[i
]);
2499 drm_mode_probed_add(connector
, newmode
);
2508 /* fix up 1366x768 mode from 1368x768;
2509 * GFT/CVT can't express 1366 width which isn't dividable by 8
2511 void drm_mode_fixup_1366x768(struct drm_display_mode
*mode
)
2513 if (mode
->hdisplay
== 1368 && mode
->vdisplay
== 768) {
2514 mode
->hdisplay
= 1366;
2515 mode
->hsync_start
--;
2517 drm_mode_set_name(mode
);
2522 drm_gtf_modes_for_range(struct drm_connector
*connector
, struct edid
*edid
,
2523 struct detailed_timing
*timing
)
2526 struct drm_display_mode
*newmode
;
2527 struct drm_device
*dev
= connector
->dev
;
2529 for (i
= 0; i
< ARRAY_SIZE(extra_modes
); i
++) {
2530 const struct minimode
*m
= &extra_modes
[i
];
2531 newmode
= drm_gtf_mode(dev
, m
->w
, m
->h
, m
->r
, 0, 0);
2535 drm_mode_fixup_1366x768(newmode
);
2536 if (!mode_in_range(newmode
, edid
, timing
) ||
2537 !valid_inferred_mode(connector
, newmode
)) {
2538 drm_mode_destroy(dev
, newmode
);
2542 drm_mode_probed_add(connector
, newmode
);
2550 drm_cvt_modes_for_range(struct drm_connector
*connector
, struct edid
*edid
,
2551 struct detailed_timing
*timing
)
2554 struct drm_display_mode
*newmode
;
2555 struct drm_device
*dev
= connector
->dev
;
2556 bool rb
= drm_monitor_supports_rb(edid
);
2558 for (i
= 0; i
< ARRAY_SIZE(extra_modes
); i
++) {
2559 const struct minimode
*m
= &extra_modes
[i
];
2560 newmode
= drm_cvt_mode(dev
, m
->w
, m
->h
, m
->r
, rb
, 0, 0);
2564 drm_mode_fixup_1366x768(newmode
);
2565 if (!mode_in_range(newmode
, edid
, timing
) ||
2566 !valid_inferred_mode(connector
, newmode
)) {
2567 drm_mode_destroy(dev
, newmode
);
2571 drm_mode_probed_add(connector
, newmode
);
2579 do_inferred_modes(struct detailed_timing
*timing
, void *c
)
2581 struct detailed_mode_closure
*closure
= c
;
2582 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2583 struct detailed_data_monitor_range
*range
= &data
->data
.range
;
2585 if (data
->type
!= EDID_DETAIL_MONITOR_RANGE
)
2588 closure
->modes
+= drm_dmt_modes_for_range(closure
->connector
,
2592 if (!version_greater(closure
->edid
, 1, 1))
2593 return; /* GTF not defined yet */
2595 switch (range
->flags
) {
2596 case 0x02: /* secondary gtf, XXX could do more */
2597 case 0x00: /* default gtf */
2598 closure
->modes
+= drm_gtf_modes_for_range(closure
->connector
,
2602 case 0x04: /* cvt, only in 1.4+ */
2603 if (!version_greater(closure
->edid
, 1, 3))
2606 closure
->modes
+= drm_cvt_modes_for_range(closure
->connector
,
2610 case 0x01: /* just the ranges, no formula */
2617 add_inferred_modes(struct drm_connector
*connector
, struct edid
*edid
)
2619 struct detailed_mode_closure closure
= {
2620 .connector
= connector
,
2624 if (version_greater(edid
, 1, 0))
2625 drm_for_each_detailed_block((u8
*)edid
, do_inferred_modes
,
2628 return closure
.modes
;
2632 drm_est3_modes(struct drm_connector
*connector
, struct detailed_timing
*timing
)
2634 int i
, j
, m
, modes
= 0;
2635 struct drm_display_mode
*mode
;
2636 u8
*est
= ((u8
*)timing
) + 6;
2638 for (i
= 0; i
< 6; i
++) {
2639 for (j
= 7; j
>= 0; j
--) {
2640 m
= (i
* 8) + (7 - j
);
2641 if (m
>= ARRAY_SIZE(est3_modes
))
2643 if (est
[i
] & (1 << j
)) {
2644 mode
= drm_mode_find_dmt(connector
->dev
,
2650 drm_mode_probed_add(connector
, mode
);
2661 do_established_modes(struct detailed_timing
*timing
, void *c
)
2663 struct detailed_mode_closure
*closure
= c
;
2664 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2666 if (data
->type
== EDID_DETAIL_EST_TIMINGS
)
2667 closure
->modes
+= drm_est3_modes(closure
->connector
, timing
);
2671 * add_established_modes - get est. modes from EDID and add them
2672 * @connector: connector to add mode(s) to
2673 * @edid: EDID block to scan
2675 * Each EDID block contains a bitmap of the supported "established modes" list
2676 * (defined above). Tease them out and add them to the global modes list.
2679 add_established_modes(struct drm_connector
*connector
, struct edid
*edid
)
2681 struct drm_device
*dev
= connector
->dev
;
2682 unsigned long est_bits
= edid
->established_timings
.t1
|
2683 (edid
->established_timings
.t2
<< 8) |
2684 ((edid
->established_timings
.mfg_rsvd
& 0x80) << 9);
2686 struct detailed_mode_closure closure
= {
2687 .connector
= connector
,
2691 for (i
= 0; i
<= EDID_EST_TIMINGS
; i
++) {
2692 if (est_bits
& (1<<i
)) {
2693 struct drm_display_mode
*newmode
;
2694 newmode
= drm_mode_duplicate(dev
, &edid_est_modes
[i
]);
2696 drm_mode_probed_add(connector
, newmode
);
2702 if (version_greater(edid
, 1, 0))
2703 drm_for_each_detailed_block((u8
*)edid
,
2704 do_established_modes
, &closure
);
2706 return modes
+ closure
.modes
;
2710 do_standard_modes(struct detailed_timing
*timing
, void *c
)
2712 struct detailed_mode_closure
*closure
= c
;
2713 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2714 struct drm_connector
*connector
= closure
->connector
;
2715 struct edid
*edid
= closure
->edid
;
2717 if (data
->type
== EDID_DETAIL_STD_MODES
) {
2719 for (i
= 0; i
< 6; i
++) {
2720 struct std_timing
*std
;
2721 struct drm_display_mode
*newmode
;
2723 std
= &data
->data
.timings
[i
];
2724 newmode
= drm_mode_std(connector
, edid
, std
);
2726 drm_mode_probed_add(connector
, newmode
);
2734 * add_standard_modes - get std. modes from EDID and add them
2735 * @connector: connector to add mode(s) to
2736 * @edid: EDID block to scan
2738 * Standard modes can be calculated using the appropriate standard (DMT,
2739 * GTF or CVT. Grab them from @edid and add them to the list.
2742 add_standard_modes(struct drm_connector
*connector
, struct edid
*edid
)
2745 struct detailed_mode_closure closure
= {
2746 .connector
= connector
,
2750 for (i
= 0; i
< EDID_STD_TIMINGS
; i
++) {
2751 struct drm_display_mode
*newmode
;
2753 newmode
= drm_mode_std(connector
, edid
,
2754 &edid
->standard_timings
[i
]);
2756 drm_mode_probed_add(connector
, newmode
);
2761 if (version_greater(edid
, 1, 0))
2762 drm_for_each_detailed_block((u8
*)edid
, do_standard_modes
,
2765 /* XXX should also look for standard codes in VTB blocks */
2767 return modes
+ closure
.modes
;
2770 static int drm_cvt_modes(struct drm_connector
*connector
,
2771 struct detailed_timing
*timing
)
2773 int i
, j
, modes
= 0;
2774 struct drm_display_mode
*newmode
;
2775 struct drm_device
*dev
= connector
->dev
;
2776 struct cvt_timing
*cvt
;
2777 const int rates
[] = { 60, 85, 75, 60, 50 };
2778 const u8 empty
[3] = { 0, 0, 0 };
2780 for (i
= 0; i
< 4; i
++) {
2781 int uninitialized_var(width
), height
;
2782 cvt
= &(timing
->data
.other_data
.data
.cvt
[i
]);
2784 if (!memcmp(cvt
->code
, empty
, 3))
2787 height
= (cvt
->code
[0] + ((cvt
->code
[1] & 0xf0) << 4) + 1) * 2;
2788 switch (cvt
->code
[1] & 0x0c) {
2790 width
= height
* 4 / 3;
2793 width
= height
* 16 / 9;
2796 width
= height
* 16 / 10;
2799 width
= height
* 15 / 9;
2803 for (j
= 1; j
< 5; j
++) {
2804 if (cvt
->code
[2] & (1 << j
)) {
2805 newmode
= drm_cvt_mode(dev
, width
, height
,
2809 drm_mode_probed_add(connector
, newmode
);
2820 do_cvt_mode(struct detailed_timing
*timing
, void *c
)
2822 struct detailed_mode_closure
*closure
= c
;
2823 struct detailed_non_pixel
*data
= &timing
->data
.other_data
;
2825 if (data
->type
== EDID_DETAIL_CVT_3BYTE
)
2826 closure
->modes
+= drm_cvt_modes(closure
->connector
, timing
);
2830 add_cvt_modes(struct drm_connector
*connector
, struct edid
*edid
)
2832 struct detailed_mode_closure closure
= {
2833 .connector
= connector
,
2837 if (version_greater(edid
, 1, 2))
2838 drm_for_each_detailed_block((u8
*)edid
, do_cvt_mode
, &closure
);
2840 /* XXX should also look for CVT codes in VTB blocks */
2842 return closure
.modes
;
2845 static void fixup_detailed_cea_mode_clock(struct drm_display_mode
*mode
);
2848 do_detailed_mode(struct detailed_timing
*timing
, void *c
)
2850 struct detailed_mode_closure
*closure
= c
;
2851 struct drm_display_mode
*newmode
;
2853 if (timing
->pixel_clock
) {
2854 newmode
= drm_mode_detailed(closure
->connector
->dev
,
2855 closure
->edid
, timing
,
2860 if (closure
->preferred
)
2861 newmode
->type
|= DRM_MODE_TYPE_PREFERRED
;
2864 * Detailed modes are limited to 10kHz pixel clock resolution,
2865 * so fix up anything that looks like CEA/HDMI mode, but the clock
2866 * is just slightly off.
2868 fixup_detailed_cea_mode_clock(newmode
);
2870 drm_mode_probed_add(closure
->connector
, newmode
);
2872 closure
->preferred
= false;
2877 * add_detailed_modes - Add modes from detailed timings
2878 * @connector: attached connector
2879 * @edid: EDID block to scan
2880 * @quirks: quirks to apply
2883 add_detailed_modes(struct drm_connector
*connector
, struct edid
*edid
,
2886 struct detailed_mode_closure closure
= {
2887 .connector
= connector
,
2893 if (closure
.preferred
&& !version_greater(edid
, 1, 3))
2895 (edid
->features
& DRM_EDID_FEATURE_PREFERRED_TIMING
);
2897 drm_for_each_detailed_block((u8
*)edid
, do_detailed_mode
, &closure
);
2899 return closure
.modes
;
2902 #define AUDIO_BLOCK 0x01
2903 #define VIDEO_BLOCK 0x02
2904 #define VENDOR_BLOCK 0x03
2905 #define SPEAKER_BLOCK 0x04
2906 #define USE_EXTENDED_TAG 0x07
2907 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2908 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2909 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2910 #define EDID_BASIC_AUDIO (1 << 6)
2911 #define EDID_CEA_YCRCB444 (1 << 5)
2912 #define EDID_CEA_YCRCB422 (1 << 4)
2913 #define EDID_CEA_VCDB_QS (1 << 6)
2916 * Search EDID for CEA extension block.
2918 static u8
*drm_find_edid_extension(const struct edid
*edid
, int ext_id
)
2920 u8
*edid_ext
= NULL
;
2923 /* No EDID or EDID extensions */
2924 if (edid
== NULL
|| edid
->extensions
== 0)
2927 /* Find CEA extension */
2928 for (i
= 0; i
< edid
->extensions
; i
++) {
2929 edid_ext
= (u8
*)edid
+ EDID_LENGTH
* (i
+ 1);
2930 if (edid_ext
[0] == ext_id
)
2934 if (i
== edid
->extensions
)
2941 static u8
*drm_find_displayid_extension(const struct edid
*edid
)
2943 return drm_find_edid_extension(edid
, DISPLAYID_EXT
);
2946 static u8
*drm_find_cea_extension(const struct edid
*edid
)
2950 int length
= EDID_LENGTH
;
2951 struct displayid_block
*block
;
2955 /* Look for a top level CEA extension block */
2956 cea
= drm_find_edid_extension(edid
, CEA_EXT
);
2960 /* CEA blocks can also be found embedded in a DisplayID block */
2961 displayid
= drm_find_displayid_extension(edid
);
2965 ret
= validate_displayid(displayid
, length
, idx
);
2969 idx
+= sizeof(struct displayid_hdr
);
2970 for_each_displayid_db(displayid
, block
, idx
, length
) {
2971 if (block
->tag
== DATA_BLOCK_CTA
) {
2981 * Calculate the alternate clock for the CEA mode
2982 * (60Hz vs. 59.94Hz etc.)
2985 cea_mode_alternate_clock(const struct drm_display_mode
*cea_mode
)
2987 unsigned int clock
= cea_mode
->clock
;
2989 if (cea_mode
->vrefresh
% 6 != 0)
2993 * edid_cea_modes contains the 59.94Hz
2994 * variant for 240 and 480 line modes,
2995 * and the 60Hz variant otherwise.
2997 if (cea_mode
->vdisplay
== 240 || cea_mode
->vdisplay
== 480)
2998 clock
= DIV_ROUND_CLOSEST(clock
* 1001, 1000);
3000 clock
= DIV_ROUND_CLOSEST(clock
* 1000, 1001);
3006 cea_mode_alternate_timings(u8 vic
, struct drm_display_mode
*mode
)
3009 * For certain VICs the spec allows the vertical
3010 * front porch to vary by one or two lines.
3012 * cea_modes[] stores the variant with the shortest
3013 * vertical front porch. We can adjust the mode to
3014 * get the other variants by simply increasing the
3015 * vertical front porch length.
3017 BUILD_BUG_ON(edid_cea_modes
[8].vtotal
!= 262 ||
3018 edid_cea_modes
[9].vtotal
!= 262 ||
3019 edid_cea_modes
[12].vtotal
!= 262 ||
3020 edid_cea_modes
[13].vtotal
!= 262 ||
3021 edid_cea_modes
[23].vtotal
!= 312 ||
3022 edid_cea_modes
[24].vtotal
!= 312 ||
3023 edid_cea_modes
[27].vtotal
!= 312 ||
3024 edid_cea_modes
[28].vtotal
!= 312);
3026 if (((vic
== 8 || vic
== 9 ||
3027 vic
== 12 || vic
== 13) && mode
->vtotal
< 263) ||
3028 ((vic
== 23 || vic
== 24 ||
3029 vic
== 27 || vic
== 28) && mode
->vtotal
< 314)) {
3030 mode
->vsync_start
++;
3040 static u8
drm_match_cea_mode_clock_tolerance(const struct drm_display_mode
*to_match
,
3041 unsigned int clock_tolerance
)
3043 unsigned int match_flags
= DRM_MODE_MATCH_TIMINGS
| DRM_MODE_MATCH_FLAGS
;
3046 if (!to_match
->clock
)
3049 if (to_match
->picture_aspect_ratio
)
3050 match_flags
|= DRM_MODE_MATCH_ASPECT_RATIO
;
3052 for (vic
= 1; vic
< ARRAY_SIZE(edid_cea_modes
); vic
++) {
3053 struct drm_display_mode cea_mode
= edid_cea_modes
[vic
];
3054 unsigned int clock1
, clock2
;
3056 /* Check both 60Hz and 59.94Hz */
3057 clock1
= cea_mode
.clock
;
3058 clock2
= cea_mode_alternate_clock(&cea_mode
);
3060 if (abs(to_match
->clock
- clock1
) > clock_tolerance
&&
3061 abs(to_match
->clock
- clock2
) > clock_tolerance
)
3065 if (drm_mode_match(to_match
, &cea_mode
, match_flags
))
3067 } while (cea_mode_alternate_timings(vic
, &cea_mode
));
3074 * drm_match_cea_mode - look for a CEA mode matching given mode
3075 * @to_match: display mode
3077 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3080 u8
drm_match_cea_mode(const struct drm_display_mode
*to_match
)
3082 unsigned int match_flags
= DRM_MODE_MATCH_TIMINGS
| DRM_MODE_MATCH_FLAGS
;
3085 if (!to_match
->clock
)
3088 if (to_match
->picture_aspect_ratio
)
3089 match_flags
|= DRM_MODE_MATCH_ASPECT_RATIO
;
3091 for (vic
= 1; vic
< ARRAY_SIZE(edid_cea_modes
); vic
++) {
3092 struct drm_display_mode cea_mode
= edid_cea_modes
[vic
];
3093 unsigned int clock1
, clock2
;
3095 /* Check both 60Hz and 59.94Hz */
3096 clock1
= cea_mode
.clock
;
3097 clock2
= cea_mode_alternate_clock(&cea_mode
);
3099 if (KHZ2PICOS(to_match
->clock
) != KHZ2PICOS(clock1
) &&
3100 KHZ2PICOS(to_match
->clock
) != KHZ2PICOS(clock2
))
3104 if (drm_mode_match(to_match
, &cea_mode
, match_flags
))
3106 } while (cea_mode_alternate_timings(vic
, &cea_mode
));
3111 EXPORT_SYMBOL(drm_match_cea_mode
);
3113 static bool drm_valid_cea_vic(u8 vic
)
3115 return vic
> 0 && vic
< ARRAY_SIZE(edid_cea_modes
);
3119 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
3120 * the input VIC from the CEA mode list
3121 * @video_code: ID given to each of the CEA modes
3123 * Returns picture aspect ratio
3125 enum hdmi_picture_aspect
drm_get_cea_aspect_ratio(const u8 video_code
)
3127 return edid_cea_modes
[video_code
].picture_aspect_ratio
;
3129 EXPORT_SYMBOL(drm_get_cea_aspect_ratio
);
3132 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3135 * It's almost like cea_mode_alternate_clock(), we just need to add an
3136 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3140 hdmi_mode_alternate_clock(const struct drm_display_mode
*hdmi_mode
)
3142 if (hdmi_mode
->vdisplay
== 4096 && hdmi_mode
->hdisplay
== 2160)
3143 return hdmi_mode
->clock
;
3145 return cea_mode_alternate_clock(hdmi_mode
);
3148 static u8
drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode
*to_match
,
3149 unsigned int clock_tolerance
)
3151 unsigned int match_flags
= DRM_MODE_MATCH_TIMINGS
| DRM_MODE_MATCH_FLAGS
;
3154 if (!to_match
->clock
)
3157 for (vic
= 1; vic
< ARRAY_SIZE(edid_4k_modes
); vic
++) {
3158 const struct drm_display_mode
*hdmi_mode
= &edid_4k_modes
[vic
];
3159 unsigned int clock1
, clock2
;
3161 /* Make sure to also match alternate clocks */
3162 clock1
= hdmi_mode
->clock
;
3163 clock2
= hdmi_mode_alternate_clock(hdmi_mode
);
3165 if (abs(to_match
->clock
- clock1
) > clock_tolerance
&&
3166 abs(to_match
->clock
- clock2
) > clock_tolerance
)
3169 if (drm_mode_match(to_match
, hdmi_mode
, match_flags
))
3177 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3178 * @to_match: display mode
3180 * An HDMI mode is one defined in the HDMI vendor specific block.
3182 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3184 static u8
drm_match_hdmi_mode(const struct drm_display_mode
*to_match
)
3186 unsigned int match_flags
= DRM_MODE_MATCH_TIMINGS
| DRM_MODE_MATCH_FLAGS
;
3189 if (!to_match
->clock
)
3192 for (vic
= 1; vic
< ARRAY_SIZE(edid_4k_modes
); vic
++) {
3193 const struct drm_display_mode
*hdmi_mode
= &edid_4k_modes
[vic
];
3194 unsigned int clock1
, clock2
;
3196 /* Make sure to also match alternate clocks */
3197 clock1
= hdmi_mode
->clock
;
3198 clock2
= hdmi_mode_alternate_clock(hdmi_mode
);
3200 if ((KHZ2PICOS(to_match
->clock
) == KHZ2PICOS(clock1
) ||
3201 KHZ2PICOS(to_match
->clock
) == KHZ2PICOS(clock2
)) &&
3202 drm_mode_match(to_match
, hdmi_mode
, match_flags
))
3208 static bool drm_valid_hdmi_vic(u8 vic
)
3210 return vic
> 0 && vic
< ARRAY_SIZE(edid_4k_modes
);
3214 add_alternate_cea_modes(struct drm_connector
*connector
, struct edid
*edid
)
3216 struct drm_device
*dev
= connector
->dev
;
3217 struct drm_display_mode
*mode
, *tmp
;
3221 /* Don't add CEA modes if the CEA extension block is missing */
3222 if (!drm_find_cea_extension(edid
))
3226 * Go through all probed modes and create a new mode
3227 * with the alternate clock for certain CEA modes.
3229 list_for_each_entry(mode
, &connector
->probed_modes
, head
) {
3230 const struct drm_display_mode
*cea_mode
= NULL
;
3231 struct drm_display_mode
*newmode
;
3232 u8 vic
= drm_match_cea_mode(mode
);
3233 unsigned int clock1
, clock2
;
3235 if (drm_valid_cea_vic(vic
)) {
3236 cea_mode
= &edid_cea_modes
[vic
];
3237 clock2
= cea_mode_alternate_clock(cea_mode
);
3239 vic
= drm_match_hdmi_mode(mode
);
3240 if (drm_valid_hdmi_vic(vic
)) {
3241 cea_mode
= &edid_4k_modes
[vic
];
3242 clock2
= hdmi_mode_alternate_clock(cea_mode
);
3249 clock1
= cea_mode
->clock
;
3251 if (clock1
== clock2
)
3254 if (mode
->clock
!= clock1
&& mode
->clock
!= clock2
)
3257 newmode
= drm_mode_duplicate(dev
, cea_mode
);
3261 /* Carry over the stereo flags */
3262 newmode
->flags
|= mode
->flags
& DRM_MODE_FLAG_3D_MASK
;
3265 * The current mode could be either variant. Make
3266 * sure to pick the "other" clock for the new mode.
3268 if (mode
->clock
!= clock1
)
3269 newmode
->clock
= clock1
;
3271 newmode
->clock
= clock2
;
3273 list_add_tail(&newmode
->head
, &list
);
3276 list_for_each_entry_safe(mode
, tmp
, &list
, head
) {
3277 list_del(&mode
->head
);
3278 drm_mode_probed_add(connector
, mode
);
3285 static u8
svd_to_vic(u8 svd
)
3287 /* 0-6 bit vic, 7th bit native mode indicator */
3288 if ((svd
>= 1 && svd
<= 64) || (svd
>= 129 && svd
<= 192))
3294 static struct drm_display_mode
*
3295 drm_display_mode_from_vic_index(struct drm_connector
*connector
,
3296 const u8
*video_db
, u8 video_len
,
3299 struct drm_device
*dev
= connector
->dev
;
3300 struct drm_display_mode
*newmode
;
3303 if (video_db
== NULL
|| video_index
>= video_len
)
3306 /* CEA modes are numbered 1..127 */
3307 vic
= svd_to_vic(video_db
[video_index
]);
3308 if (!drm_valid_cea_vic(vic
))
3311 newmode
= drm_mode_duplicate(dev
, &edid_cea_modes
[vic
]);
3315 newmode
->vrefresh
= 0;
3321 * do_y420vdb_modes - Parse YCBCR 420 only modes
3322 * @connector: connector corresponding to the HDMI sink
3323 * @svds: start of the data block of CEA YCBCR 420 VDB
3324 * @len: length of the CEA YCBCR 420 VDB
3326 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3327 * which contains modes which can be supported in YCBCR 420
3328 * output format only.
3330 static int do_y420vdb_modes(struct drm_connector
*connector
,
3331 const u8
*svds
, u8 svds_len
)
3334 struct drm_device
*dev
= connector
->dev
;
3335 struct drm_display_info
*info
= &connector
->display_info
;
3336 struct drm_hdmi_info
*hdmi
= &info
->hdmi
;
3338 for (i
= 0; i
< svds_len
; i
++) {
3339 u8 vic
= svd_to_vic(svds
[i
]);
3340 struct drm_display_mode
*newmode
;
3342 if (!drm_valid_cea_vic(vic
))
3345 newmode
= drm_mode_duplicate(dev
, &edid_cea_modes
[vic
]);
3348 bitmap_set(hdmi
->y420_vdb_modes
, vic
, 1);
3349 drm_mode_probed_add(connector
, newmode
);
3354 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB420
;
3359 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3360 * @connector: connector corresponding to the HDMI sink
3361 * @vic: CEA vic for the video mode to be added in the map
3363 * Makes an entry for a videomode in the YCBCR 420 bitmap
3366 drm_add_cmdb_modes(struct drm_connector
*connector
, u8 svd
)
3368 u8 vic
= svd_to_vic(svd
);
3369 struct drm_hdmi_info
*hdmi
= &connector
->display_info
.hdmi
;
3371 if (!drm_valid_cea_vic(vic
))
3374 bitmap_set(hdmi
->y420_cmdb_modes
, vic
, 1);
3378 do_cea_modes(struct drm_connector
*connector
, const u8
*db
, u8 len
)
3381 struct drm_hdmi_info
*hdmi
= &connector
->display_info
.hdmi
;
3383 for (i
= 0; i
< len
; i
++) {
3384 struct drm_display_mode
*mode
;
3385 mode
= drm_display_mode_from_vic_index(connector
, db
, len
, i
);
3388 * YCBCR420 capability block contains a bitmap which
3389 * gives the index of CEA modes from CEA VDB, which
3390 * can support YCBCR 420 sampling output also (apart
3391 * from RGB/YCBCR444 etc).
3392 * For example, if the bit 0 in bitmap is set,
3393 * first mode in VDB can support YCBCR420 output too.
3394 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3396 if (i
< 64 && hdmi
->y420_cmdb_map
& (1ULL << i
))
3397 drm_add_cmdb_modes(connector
, db
[i
]);
3399 drm_mode_probed_add(connector
, mode
);
3407 struct stereo_mandatory_mode
{
3408 int width
, height
, vrefresh
;
3412 static const struct stereo_mandatory_mode stereo_mandatory_modes
[] = {
3413 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
},
3414 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING
},
3416 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
},
3418 DRM_MODE_FLAG_INTERLACE
| DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
},
3419 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
},
3420 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING
},
3421 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
},
3422 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING
}
3426 stereo_match_mandatory(const struct drm_display_mode
*mode
,
3427 const struct stereo_mandatory_mode
*stereo_mode
)
3429 unsigned int interlaced
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
3431 return mode
->hdisplay
== stereo_mode
->width
&&
3432 mode
->vdisplay
== stereo_mode
->height
&&
3433 interlaced
== (stereo_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) &&
3434 drm_mode_vrefresh(mode
) == stereo_mode
->vrefresh
;
3437 static int add_hdmi_mandatory_stereo_modes(struct drm_connector
*connector
)
3439 struct drm_device
*dev
= connector
->dev
;
3440 const struct drm_display_mode
*mode
;
3441 struct list_head stereo_modes
;
3444 INIT_LIST_HEAD(&stereo_modes
);
3446 list_for_each_entry(mode
, &connector
->probed_modes
, head
) {
3447 for (i
= 0; i
< ARRAY_SIZE(stereo_mandatory_modes
); i
++) {
3448 const struct stereo_mandatory_mode
*mandatory
;
3449 struct drm_display_mode
*new_mode
;
3451 if (!stereo_match_mandatory(mode
,
3452 &stereo_mandatory_modes
[i
]))
3455 mandatory
= &stereo_mandatory_modes
[i
];
3456 new_mode
= drm_mode_duplicate(dev
, mode
);
3460 new_mode
->flags
|= mandatory
->flags
;
3461 list_add_tail(&new_mode
->head
, &stereo_modes
);
3466 list_splice_tail(&stereo_modes
, &connector
->probed_modes
);
3471 static int add_hdmi_mode(struct drm_connector
*connector
, u8 vic
)
3473 struct drm_device
*dev
= connector
->dev
;
3474 struct drm_display_mode
*newmode
;
3476 if (!drm_valid_hdmi_vic(vic
)) {
3477 DRM_ERROR("Unknown HDMI VIC: %d\n", vic
);
3481 newmode
= drm_mode_duplicate(dev
, &edid_4k_modes
[vic
]);
3485 drm_mode_probed_add(connector
, newmode
);
3490 static int add_3d_struct_modes(struct drm_connector
*connector
, u16 structure
,
3491 const u8
*video_db
, u8 video_len
, u8 video_index
)
3493 struct drm_display_mode
*newmode
;
3496 if (structure
& (1 << 0)) {
3497 newmode
= drm_display_mode_from_vic_index(connector
, video_db
,
3501 newmode
->flags
|= DRM_MODE_FLAG_3D_FRAME_PACKING
;
3502 drm_mode_probed_add(connector
, newmode
);
3506 if (structure
& (1 << 6)) {
3507 newmode
= drm_display_mode_from_vic_index(connector
, video_db
,
3511 newmode
->flags
|= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
;
3512 drm_mode_probed_add(connector
, newmode
);
3516 if (structure
& (1 << 8)) {
3517 newmode
= drm_display_mode_from_vic_index(connector
, video_db
,
3521 newmode
->flags
|= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
;
3522 drm_mode_probed_add(connector
, newmode
);
3531 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3532 * @connector: connector corresponding to the HDMI sink
3533 * @db: start of the CEA vendor specific block
3534 * @len: length of the CEA block payload, ie. one can access up to db[len]
3536 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3537 * also adds the stereo 3d modes when applicable.
3540 do_hdmi_vsdb_modes(struct drm_connector
*connector
, const u8
*db
, u8 len
,
3541 const u8
*video_db
, u8 video_len
)
3543 struct drm_display_info
*info
= &connector
->display_info
;
3544 int modes
= 0, offset
= 0, i
, multi_present
= 0, multi_len
;
3545 u8 vic_len
, hdmi_3d_len
= 0;
3552 /* no HDMI_Video_Present */
3553 if (!(db
[8] & (1 << 5)))
3556 /* Latency_Fields_Present */
3557 if (db
[8] & (1 << 7))
3560 /* I_Latency_Fields_Present */
3561 if (db
[8] & (1 << 6))
3564 /* the declared length is not long enough for the 2 first bytes
3565 * of additional video format capabilities */
3566 if (len
< (8 + offset
+ 2))
3571 if (db
[8 + offset
] & (1 << 7)) {
3572 modes
+= add_hdmi_mandatory_stereo_modes(connector
);
3574 /* 3D_Multi_present */
3575 multi_present
= (db
[8 + offset
] & 0x60) >> 5;
3579 vic_len
= db
[8 + offset
] >> 5;
3580 hdmi_3d_len
= db
[8 + offset
] & 0x1f;
3582 for (i
= 0; i
< vic_len
&& len
>= (9 + offset
+ i
); i
++) {
3585 vic
= db
[9 + offset
+ i
];
3586 modes
+= add_hdmi_mode(connector
, vic
);
3588 offset
+= 1 + vic_len
;
3590 if (multi_present
== 1)
3592 else if (multi_present
== 2)
3597 if (len
< (8 + offset
+ hdmi_3d_len
- 1))
3600 if (hdmi_3d_len
< multi_len
)
3603 if (multi_present
== 1 || multi_present
== 2) {
3604 /* 3D_Structure_ALL */
3605 structure_all
= (db
[8 + offset
] << 8) | db
[9 + offset
];
3607 /* check if 3D_MASK is present */
3608 if (multi_present
== 2)
3609 mask
= (db
[10 + offset
] << 8) | db
[11 + offset
];
3613 for (i
= 0; i
< 16; i
++) {
3614 if (mask
& (1 << i
))
3615 modes
+= add_3d_struct_modes(connector
,
3622 offset
+= multi_len
;
3624 for (i
= 0; i
< (hdmi_3d_len
- multi_len
); i
++) {
3626 struct drm_display_mode
*newmode
= NULL
;
3627 unsigned int newflag
= 0;
3628 bool detail_present
;
3630 detail_present
= ((db
[8 + offset
+ i
] & 0x0f) > 7);
3632 if (detail_present
&& (i
+ 1 == hdmi_3d_len
- multi_len
))
3635 /* 2D_VIC_order_X */
3636 vic_index
= db
[8 + offset
+ i
] >> 4;
3638 /* 3D_Structure_X */
3639 switch (db
[8 + offset
+ i
] & 0x0f) {
3641 newflag
= DRM_MODE_FLAG_3D_FRAME_PACKING
;
3644 newflag
= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
;
3648 if ((db
[9 + offset
+ i
] >> 4) == 1)
3649 newflag
= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
;
3654 newmode
= drm_display_mode_from_vic_index(connector
,
3660 newmode
->flags
|= newflag
;
3661 drm_mode_probed_add(connector
, newmode
);
3672 info
->has_hdmi_infoframe
= true;
3677 cea_db_payload_len(const u8
*db
)
3679 return db
[0] & 0x1f;
3683 cea_db_extended_tag(const u8
*db
)
3689 cea_db_tag(const u8
*db
)
3695 cea_revision(const u8
*cea
)
3701 cea_db_offsets(const u8
*cea
, int *start
, int *end
)
3703 /* DisplayID CTA extension blocks and top-level CEA EDID
3704 * block header definitions differ in the following bytes:
3705 * 1) Byte 2 of the header specifies length differently,
3706 * 2) Byte 3 is only present in the CEA top level block.
3708 * The different definitions for byte 2 follow.
3710 * DisplayID CTA extension block defines byte 2 as:
3711 * Number of payload bytes
3713 * CEA EDID block defines byte 2 as:
3714 * Byte number (decimal) within this block where the 18-byte
3715 * DTDs begin. If no non-DTD data is present in this extension
3716 * block, the value should be set to 04h (the byte after next).
3717 * If set to 00h, there are no DTDs present in this block and
3720 if (cea
[0] == DATA_BLOCK_CTA
) {
3722 *end
= *start
+ cea
[2];
3723 } else if (cea
[0] == CEA_EXT
) {
3724 /* Data block offset in CEA extension block */
3729 if (*end
< 4 || *end
> 127)
3738 static bool cea_db_is_hdmi_vsdb(const u8
*db
)
3742 if (cea_db_tag(db
) != VENDOR_BLOCK
)
3745 if (cea_db_payload_len(db
) < 5)
3748 hdmi_id
= db
[1] | (db
[2] << 8) | (db
[3] << 16);
3750 return hdmi_id
== HDMI_IEEE_OUI
;
3753 static bool cea_db_is_hdmi_forum_vsdb(const u8
*db
)
3757 if (cea_db_tag(db
) != VENDOR_BLOCK
)
3760 if (cea_db_payload_len(db
) < 7)
3763 oui
= db
[3] << 16 | db
[2] << 8 | db
[1];
3765 return oui
== HDMI_FORUM_IEEE_OUI
;
3768 static bool cea_db_is_y420cmdb(const u8
*db
)
3770 if (cea_db_tag(db
) != USE_EXTENDED_TAG
)
3773 if (!cea_db_payload_len(db
))
3776 if (cea_db_extended_tag(db
) != EXT_VIDEO_CAP_BLOCK_Y420CMDB
)
3782 static bool cea_db_is_y420vdb(const u8
*db
)
3784 if (cea_db_tag(db
) != USE_EXTENDED_TAG
)
3787 if (!cea_db_payload_len(db
))
3790 if (cea_db_extended_tag(db
) != EXT_VIDEO_DATA_BLOCK_420
)
3796 #define for_each_cea_db(cea, i, start, end) \
3797 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3799 static void drm_parse_y420cmdb_bitmap(struct drm_connector
*connector
,
3802 struct drm_display_info
*info
= &connector
->display_info
;
3803 struct drm_hdmi_info
*hdmi
= &info
->hdmi
;
3804 u8 map_len
= cea_db_payload_len(db
) - 1;
3809 /* All CEA modes support ycbcr420 sampling also.*/
3810 hdmi
->y420_cmdb_map
= U64_MAX
;
3811 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB420
;
3816 * This map indicates which of the existing CEA block modes
3817 * from VDB can support YCBCR420 output too. So if bit=0 is
3818 * set, first mode from VDB can support YCBCR420 output too.
3819 * We will parse and keep this map, before parsing VDB itself
3820 * to avoid going through the same block again and again.
3822 * Spec is not clear about max possible size of this block.
3823 * Clamping max bitmap block size at 8 bytes. Every byte can
3824 * address 8 CEA modes, in this way this map can address
3825 * 8*8 = first 64 SVDs.
3827 if (WARN_ON_ONCE(map_len
> 8))
3830 for (count
= 0; count
< map_len
; count
++)
3831 map
|= (u64
)db
[2 + count
] << (8 * count
);
3834 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB420
;
3836 hdmi
->y420_cmdb_map
= map
;
3840 add_cea_modes(struct drm_connector
*connector
, struct edid
*edid
)
3842 const u8
*cea
= drm_find_cea_extension(edid
);
3843 const u8
*db
, *hdmi
= NULL
, *video
= NULL
;
3844 u8 dbl
, hdmi_len
, video_len
= 0;
3847 if (cea
&& cea_revision(cea
) >= 3) {
3850 if (cea_db_offsets(cea
, &start
, &end
))
3853 for_each_cea_db(cea
, i
, start
, end
) {
3855 dbl
= cea_db_payload_len(db
);
3857 if (cea_db_tag(db
) == VIDEO_BLOCK
) {
3860 modes
+= do_cea_modes(connector
, video
, dbl
);
3861 } else if (cea_db_is_hdmi_vsdb(db
)) {
3864 } else if (cea_db_is_y420vdb(db
)) {
3865 const u8
*vdb420
= &db
[2];
3867 /* Add 4:2:0(only) modes present in EDID */
3868 modes
+= do_y420vdb_modes(connector
,
3876 * We parse the HDMI VSDB after having added the cea modes as we will
3877 * be patching their flags when the sink supports stereo 3D.
3880 modes
+= do_hdmi_vsdb_modes(connector
, hdmi
, hdmi_len
, video
,
3886 static void fixup_detailed_cea_mode_clock(struct drm_display_mode
*mode
)
3888 const struct drm_display_mode
*cea_mode
;
3889 int clock1
, clock2
, clock
;
3894 * allow 5kHz clock difference either way to account for
3895 * the 10kHz clock resolution limit of detailed timings.
3897 vic
= drm_match_cea_mode_clock_tolerance(mode
, 5);
3898 if (drm_valid_cea_vic(vic
)) {
3900 cea_mode
= &edid_cea_modes
[vic
];
3901 clock1
= cea_mode
->clock
;
3902 clock2
= cea_mode_alternate_clock(cea_mode
);
3904 vic
= drm_match_hdmi_mode_clock_tolerance(mode
, 5);
3905 if (drm_valid_hdmi_vic(vic
)) {
3907 cea_mode
= &edid_4k_modes
[vic
];
3908 clock1
= cea_mode
->clock
;
3909 clock2
= hdmi_mode_alternate_clock(cea_mode
);
3915 /* pick whichever is closest */
3916 if (abs(mode
->clock
- clock1
) < abs(mode
->clock
- clock2
))
3921 if (mode
->clock
== clock
)
3924 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3925 type
, vic
, mode
->clock
, clock
);
3926 mode
->clock
= clock
;
3930 drm_parse_hdmi_vsdb_audio(struct drm_connector
*connector
, const u8
*db
)
3932 u8 len
= cea_db_payload_len(db
);
3934 if (len
>= 6 && (db
[6] & (1 << 7)))
3935 connector
->eld
[DRM_ELD_SAD_COUNT_CONN_TYPE
] |= DRM_ELD_SUPPORTS_AI
;
3937 connector
->latency_present
[0] = db
[8] >> 7;
3938 connector
->latency_present
[1] = (db
[8] >> 6) & 1;
3941 connector
->video_latency
[0] = db
[9];
3943 connector
->audio_latency
[0] = db
[10];
3945 connector
->video_latency
[1] = db
[11];
3947 connector
->audio_latency
[1] = db
[12];
3949 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3950 "video latency %d %d, "
3951 "audio latency %d %d\n",
3952 connector
->latency_present
[0],
3953 connector
->latency_present
[1],
3954 connector
->video_latency
[0],
3955 connector
->video_latency
[1],
3956 connector
->audio_latency
[0],
3957 connector
->audio_latency
[1]);
3961 monitor_name(struct detailed_timing
*t
, void *data
)
3963 if (t
->data
.other_data
.type
== EDID_DETAIL_MONITOR_NAME
)
3964 *(u8
**)data
= t
->data
.other_data
.data
.str
.str
;
3967 static int get_monitor_name(struct edid
*edid
, char name
[13])
3969 char *edid_name
= NULL
;
3975 drm_for_each_detailed_block((u8
*)edid
, monitor_name
, &edid_name
);
3976 for (mnl
= 0; edid_name
&& mnl
< 13; mnl
++) {
3977 if (edid_name
[mnl
] == 0x0a)
3980 name
[mnl
] = edid_name
[mnl
];
3987 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3988 * @edid: monitor EDID information
3989 * @name: pointer to a character array to hold the name of the monitor
3990 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3993 void drm_edid_get_monitor_name(struct edid
*edid
, char *name
, int bufsize
)
4001 name_length
= min(get_monitor_name(edid
, buf
), bufsize
- 1);
4002 memcpy(name
, buf
, name_length
);
4003 name
[name_length
] = '\0';
4005 EXPORT_SYMBOL(drm_edid_get_monitor_name
);
4007 static void clear_eld(struct drm_connector
*connector
)
4009 memset(connector
->eld
, 0, sizeof(connector
->eld
));
4011 connector
->latency_present
[0] = false;
4012 connector
->latency_present
[1] = false;
4013 connector
->video_latency
[0] = 0;
4014 connector
->audio_latency
[0] = 0;
4015 connector
->video_latency
[1] = 0;
4016 connector
->audio_latency
[1] = 0;
4020 * drm_edid_to_eld - build ELD from EDID
4021 * @connector: connector corresponding to the HDMI/DP sink
4022 * @edid: EDID to parse
4024 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4025 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4027 static void drm_edid_to_eld(struct drm_connector
*connector
, struct edid
*edid
)
4029 uint8_t *eld
= connector
->eld
;
4032 int total_sad_count
= 0;
4036 clear_eld(connector
);
4041 cea
= drm_find_cea_extension(edid
);
4043 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4047 mnl
= get_monitor_name(edid
, &eld
[DRM_ELD_MONITOR_NAME_STRING
]);
4048 DRM_DEBUG_KMS("ELD monitor %s\n", &eld
[DRM_ELD_MONITOR_NAME_STRING
]);
4050 eld
[DRM_ELD_CEA_EDID_VER_MNL
] = cea
[1] << DRM_ELD_CEA_EDID_VER_SHIFT
;
4051 eld
[DRM_ELD_CEA_EDID_VER_MNL
] |= mnl
;
4053 eld
[DRM_ELD_VER
] = DRM_ELD_VER_CEA861D
;
4055 eld
[DRM_ELD_MANUFACTURER_NAME0
] = edid
->mfg_id
[0];
4056 eld
[DRM_ELD_MANUFACTURER_NAME1
] = edid
->mfg_id
[1];
4057 eld
[DRM_ELD_PRODUCT_CODE0
] = edid
->prod_code
[0];
4058 eld
[DRM_ELD_PRODUCT_CODE1
] = edid
->prod_code
[1];
4060 if (cea_revision(cea
) >= 3) {
4063 if (cea_db_offsets(cea
, &start
, &end
)) {
4068 for_each_cea_db(cea
, i
, start
, end
) {
4070 dbl
= cea_db_payload_len(db
);
4072 switch (cea_db_tag(db
)) {
4076 /* Audio Data Block, contains SADs */
4077 sad_count
= min(dbl
/ 3, 15 - total_sad_count
);
4079 memcpy(&eld
[DRM_ELD_CEA_SAD(mnl
, total_sad_count
)],
4080 &db
[1], sad_count
* 3);
4081 total_sad_count
+= sad_count
;
4084 /* Speaker Allocation Data Block */
4086 eld
[DRM_ELD_SPEAKER
] = db
[1];
4089 /* HDMI Vendor-Specific Data Block */
4090 if (cea_db_is_hdmi_vsdb(db
))
4091 drm_parse_hdmi_vsdb_audio(connector
, db
);
4098 eld
[DRM_ELD_SAD_COUNT_CONN_TYPE
] |= total_sad_count
<< DRM_ELD_SAD_COUNT_SHIFT
;
4100 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
4101 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
4102 eld
[DRM_ELD_SAD_COUNT_CONN_TYPE
] |= DRM_ELD_CONN_TYPE_DP
;
4104 eld
[DRM_ELD_SAD_COUNT_CONN_TYPE
] |= DRM_ELD_CONN_TYPE_HDMI
;
4106 eld
[DRM_ELD_BASELINE_ELD_LEN
] =
4107 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld
), 4);
4109 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4110 drm_eld_size(eld
), total_sad_count
);
4114 * drm_edid_to_sad - extracts SADs from EDID
4115 * @edid: EDID to parse
4116 * @sads: pointer that will be set to the extracted SADs
4118 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4120 * Note: The returned pointer needs to be freed using kfree().
4122 * Return: The number of found SADs or negative number on error.
4124 int drm_edid_to_sad(struct edid
*edid
, struct cea_sad
**sads
)
4127 int i
, start
, end
, dbl
;
4130 cea
= drm_find_cea_extension(edid
);
4132 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4136 if (cea_revision(cea
) < 3) {
4137 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4141 if (cea_db_offsets(cea
, &start
, &end
)) {
4142 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4146 for_each_cea_db(cea
, i
, start
, end
) {
4149 if (cea_db_tag(db
) == AUDIO_BLOCK
) {
4151 dbl
= cea_db_payload_len(db
);
4153 count
= dbl
/ 3; /* SAD is 3B */
4154 *sads
= kcalloc(count
, sizeof(**sads
), GFP_KERNEL
);
4157 for (j
= 0; j
< count
; j
++) {
4158 u8
*sad
= &db
[1 + j
* 3];
4160 (*sads
)[j
].format
= (sad
[0] & 0x78) >> 3;
4161 (*sads
)[j
].channels
= sad
[0] & 0x7;
4162 (*sads
)[j
].freq
= sad
[1] & 0x7F;
4163 (*sads
)[j
].byte2
= sad
[2];
4171 EXPORT_SYMBOL(drm_edid_to_sad
);
4174 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4175 * @edid: EDID to parse
4176 * @sadb: pointer to the speaker block
4178 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4180 * Note: The returned pointer needs to be freed using kfree().
4182 * Return: The number of found Speaker Allocation Blocks or negative number on
4185 int drm_edid_to_speaker_allocation(struct edid
*edid
, u8
**sadb
)
4188 int i
, start
, end
, dbl
;
4191 cea
= drm_find_cea_extension(edid
);
4193 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4197 if (cea_revision(cea
) < 3) {
4198 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4202 if (cea_db_offsets(cea
, &start
, &end
)) {
4203 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4207 for_each_cea_db(cea
, i
, start
, end
) {
4208 const u8
*db
= &cea
[i
];
4210 if (cea_db_tag(db
) == SPEAKER_BLOCK
) {
4211 dbl
= cea_db_payload_len(db
);
4213 /* Speaker Allocation Data Block */
4215 *sadb
= kmemdup(&db
[1], dbl
, GFP_KERNEL
);
4226 EXPORT_SYMBOL(drm_edid_to_speaker_allocation
);
4229 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4230 * @connector: connector associated with the HDMI/DP sink
4231 * @mode: the display mode
4233 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4234 * the sink doesn't support audio or video.
4236 int drm_av_sync_delay(struct drm_connector
*connector
,
4237 const struct drm_display_mode
*mode
)
4239 int i
= !!(mode
->flags
& DRM_MODE_FLAG_INTERLACE
);
4242 if (!connector
->latency_present
[0])
4244 if (!connector
->latency_present
[1])
4247 a
= connector
->audio_latency
[i
];
4248 v
= connector
->video_latency
[i
];
4251 * HDMI/DP sink doesn't support audio or video?
4253 if (a
== 255 || v
== 255)
4257 * Convert raw EDID values to millisecond.
4258 * Treat unknown latency as 0ms.
4261 a
= min(2 * (a
- 1), 500);
4263 v
= min(2 * (v
- 1), 500);
4265 return max(v
- a
, 0);
4267 EXPORT_SYMBOL(drm_av_sync_delay
);
4270 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4271 * @edid: monitor EDID information
4273 * Parse the CEA extension according to CEA-861-B.
4275 * Return: True if the monitor is HDMI, false if not or unknown.
4277 bool drm_detect_hdmi_monitor(struct edid
*edid
)
4281 int start_offset
, end_offset
;
4283 edid_ext
= drm_find_cea_extension(edid
);
4287 if (cea_db_offsets(edid_ext
, &start_offset
, &end_offset
))
4291 * Because HDMI identifier is in Vendor Specific Block,
4292 * search it from all data blocks of CEA extension.
4294 for_each_cea_db(edid_ext
, i
, start_offset
, end_offset
) {
4295 if (cea_db_is_hdmi_vsdb(&edid_ext
[i
]))
4301 EXPORT_SYMBOL(drm_detect_hdmi_monitor
);
4304 * drm_detect_monitor_audio - check monitor audio capability
4305 * @edid: EDID block to scan
4307 * Monitor should have CEA extension block.
4308 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4309 * audio' only. If there is any audio extension block and supported
4310 * audio format, assume at least 'basic audio' support, even if 'basic
4311 * audio' is not defined in EDID.
4313 * Return: True if the monitor supports audio, false otherwise.
4315 bool drm_detect_monitor_audio(struct edid
*edid
)
4319 bool has_audio
= false;
4320 int start_offset
, end_offset
;
4322 edid_ext
= drm_find_cea_extension(edid
);
4326 has_audio
= ((edid_ext
[3] & EDID_BASIC_AUDIO
) != 0);
4329 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4333 if (cea_db_offsets(edid_ext
, &start_offset
, &end_offset
))
4336 for_each_cea_db(edid_ext
, i
, start_offset
, end_offset
) {
4337 if (cea_db_tag(&edid_ext
[i
]) == AUDIO_BLOCK
) {
4339 for (j
= 1; j
< cea_db_payload_len(&edid_ext
[i
]) + 1; j
+= 3)
4340 DRM_DEBUG_KMS("CEA audio format %d\n",
4341 (edid_ext
[i
+ j
] >> 3) & 0xf);
4348 EXPORT_SYMBOL(drm_detect_monitor_audio
);
4351 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4352 * @edid: EDID block to scan
4354 * Check whether the monitor reports the RGB quantization range selection
4355 * as supported. The AVI infoframe can then be used to inform the monitor
4356 * which quantization range (full or limited) is used.
4358 * Return: True if the RGB quantization range is selectable, false otherwise.
4360 bool drm_rgb_quant_range_selectable(struct edid
*edid
)
4365 edid_ext
= drm_find_cea_extension(edid
);
4369 if (cea_db_offsets(edid_ext
, &start
, &end
))
4372 for_each_cea_db(edid_ext
, i
, start
, end
) {
4373 if (cea_db_tag(&edid_ext
[i
]) == USE_EXTENDED_TAG
&&
4374 cea_db_payload_len(&edid_ext
[i
]) == 2 &&
4375 cea_db_extended_tag(&edid_ext
[i
]) ==
4376 EXT_VIDEO_CAPABILITY_BLOCK
) {
4377 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext
[i
+ 2]);
4378 return edid_ext
[i
+ 2] & EDID_CEA_VCDB_QS
;
4384 EXPORT_SYMBOL(drm_rgb_quant_range_selectable
);
4387 * drm_default_rgb_quant_range - default RGB quantization range
4388 * @mode: display mode
4390 * Determine the default RGB quantization range for the mode,
4391 * as specified in CEA-861.
4393 * Return: The default RGB quantization range for the mode
4395 enum hdmi_quantization_range
4396 drm_default_rgb_quant_range(const struct drm_display_mode
*mode
)
4398 /* All CEA modes other than VIC 1 use limited quantization range. */
4399 return drm_match_cea_mode(mode
) > 1 ?
4400 HDMI_QUANTIZATION_RANGE_LIMITED
:
4401 HDMI_QUANTIZATION_RANGE_FULL
;
4403 EXPORT_SYMBOL(drm_default_rgb_quant_range
);
4405 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector
*connector
,
4409 struct drm_hdmi_info
*hdmi
= &connector
->display_info
.hdmi
;
4411 dc_mask
= db
[7] & DRM_EDID_YCBCR420_DC_MASK
;
4412 hdmi
->y420_dc_modes
= dc_mask
;
4415 static void drm_parse_hdmi_forum_vsdb(struct drm_connector
*connector
,
4418 struct drm_display_info
*display
= &connector
->display_info
;
4419 struct drm_hdmi_info
*hdmi
= &display
->hdmi
;
4421 display
->has_hdmi_infoframe
= true;
4423 if (hf_vsdb
[6] & 0x80) {
4424 hdmi
->scdc
.supported
= true;
4425 if (hf_vsdb
[6] & 0x40)
4426 hdmi
->scdc
.read_request
= true;
4430 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4431 * And as per the spec, three factors confirm this:
4432 * * Availability of a HF-VSDB block in EDID (check)
4433 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4434 * * SCDC support available (let's check)
4435 * Lets check it out.
4439 /* max clock is 5000 KHz times block value */
4440 u32 max_tmds_clock
= hf_vsdb
[5] * 5000;
4441 struct drm_scdc
*scdc
= &hdmi
->scdc
;
4443 if (max_tmds_clock
> 340000) {
4444 display
->max_tmds_clock
= max_tmds_clock
;
4445 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4446 display
->max_tmds_clock
);
4449 if (scdc
->supported
) {
4450 scdc
->scrambling
.supported
= true;
4452 /* Few sinks support scrambling for cloks < 340M */
4453 if ((hf_vsdb
[6] & 0x8))
4454 scdc
->scrambling
.low_rates
= true;
4458 drm_parse_ycbcr420_deep_color_info(connector
, hf_vsdb
);
4461 static void drm_parse_hdmi_deep_color_info(struct drm_connector
*connector
,
4464 struct drm_display_info
*info
= &connector
->display_info
;
4465 unsigned int dc_bpc
= 0;
4467 /* HDMI supports at least 8 bpc */
4470 if (cea_db_payload_len(hdmi
) < 6)
4473 if (hdmi
[6] & DRM_EDID_HDMI_DC_30
) {
4475 info
->edid_hdmi_dc_modes
|= DRM_EDID_HDMI_DC_30
;
4476 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4480 if (hdmi
[6] & DRM_EDID_HDMI_DC_36
) {
4482 info
->edid_hdmi_dc_modes
|= DRM_EDID_HDMI_DC_36
;
4483 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4487 if (hdmi
[6] & DRM_EDID_HDMI_DC_48
) {
4489 info
->edid_hdmi_dc_modes
|= DRM_EDID_HDMI_DC_48
;
4490 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4495 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4500 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4501 connector
->name
, dc_bpc
);
4505 * Deep color support mandates RGB444 support for all video
4506 * modes and forbids YCRCB422 support for all video modes per
4509 info
->color_formats
= DRM_COLOR_FORMAT_RGB444
;
4511 /* YCRCB444 is optional according to spec. */
4512 if (hdmi
[6] & DRM_EDID_HDMI_DC_Y444
) {
4513 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB444
;
4514 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4519 * Spec says that if any deep color mode is supported at all,
4520 * then deep color 36 bit must be supported.
4522 if (!(hdmi
[6] & DRM_EDID_HDMI_DC_36
)) {
4523 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4529 drm_parse_hdmi_vsdb_video(struct drm_connector
*connector
, const u8
*db
)
4531 struct drm_display_info
*info
= &connector
->display_info
;
4532 u8 len
= cea_db_payload_len(db
);
4535 info
->dvi_dual
= db
[6] & 1;
4537 info
->max_tmds_clock
= db
[7] * 5000;
4539 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4540 "max TMDS clock %d kHz\n",
4542 info
->max_tmds_clock
);
4544 drm_parse_hdmi_deep_color_info(connector
, db
);
4547 static void drm_parse_cea_ext(struct drm_connector
*connector
,
4548 const struct edid
*edid
)
4550 struct drm_display_info
*info
= &connector
->display_info
;
4554 edid_ext
= drm_find_cea_extension(edid
);
4558 info
->cea_rev
= edid_ext
[1];
4560 /* The existence of a CEA block should imply RGB support */
4561 info
->color_formats
= DRM_COLOR_FORMAT_RGB444
;
4562 if (edid_ext
[3] & EDID_CEA_YCRCB444
)
4563 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB444
;
4564 if (edid_ext
[3] & EDID_CEA_YCRCB422
)
4565 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB422
;
4567 if (cea_db_offsets(edid_ext
, &start
, &end
))
4570 for_each_cea_db(edid_ext
, i
, start
, end
) {
4571 const u8
*db
= &edid_ext
[i
];
4573 if (cea_db_is_hdmi_vsdb(db
))
4574 drm_parse_hdmi_vsdb_video(connector
, db
);
4575 if (cea_db_is_hdmi_forum_vsdb(db
))
4576 drm_parse_hdmi_forum_vsdb(connector
, db
);
4577 if (cea_db_is_y420cmdb(db
))
4578 drm_parse_y420cmdb_bitmap(connector
, db
);
4582 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4583 * all of the values which would have been set from EDID
4586 drm_reset_display_info(struct drm_connector
*connector
)
4588 struct drm_display_info
*info
= &connector
->display_info
;
4591 info
->height_mm
= 0;
4594 info
->color_formats
= 0;
4596 info
->max_tmds_clock
= 0;
4597 info
->dvi_dual
= false;
4598 info
->has_hdmi_infoframe
= false;
4599 memset(&info
->hdmi
, 0, sizeof(info
->hdmi
));
4601 info
->non_desktop
= 0;
4604 u32
drm_add_display_info(struct drm_connector
*connector
, const struct edid
*edid
)
4606 struct drm_display_info
*info
= &connector
->display_info
;
4608 u32 quirks
= edid_get_quirks(edid
);
4610 drm_reset_display_info(connector
);
4612 info
->width_mm
= edid
->width_cm
* 10;
4613 info
->height_mm
= edid
->height_cm
* 10;
4615 info
->non_desktop
= !!(quirks
& EDID_QUIRK_NON_DESKTOP
);
4617 DRM_DEBUG_KMS("non_desktop set to %d\n", info
->non_desktop
);
4619 if (edid
->revision
< 3)
4622 if (!(edid
->input
& DRM_EDID_INPUT_DIGITAL
))
4625 drm_parse_cea_ext(connector
, edid
);
4628 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4630 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4631 * tells us to assume 8 bpc color depth if the EDID doesn't have
4632 * extensions which tell otherwise.
4634 if ((info
->bpc
== 0) && (edid
->revision
< 4) &&
4635 (edid
->input
& DRM_EDID_DIGITAL_TYPE_DVI
)) {
4637 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4638 connector
->name
, info
->bpc
);
4641 /* Only defined for 1.4 with digital displays */
4642 if (edid
->revision
< 4)
4645 switch (edid
->input
& DRM_EDID_DIGITAL_DEPTH_MASK
) {
4646 case DRM_EDID_DIGITAL_DEPTH_6
:
4649 case DRM_EDID_DIGITAL_DEPTH_8
:
4652 case DRM_EDID_DIGITAL_DEPTH_10
:
4655 case DRM_EDID_DIGITAL_DEPTH_12
:
4658 case DRM_EDID_DIGITAL_DEPTH_14
:
4661 case DRM_EDID_DIGITAL_DEPTH_16
:
4664 case DRM_EDID_DIGITAL_DEPTH_UNDEF
:
4670 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4671 connector
->name
, info
->bpc
);
4673 info
->color_formats
|= DRM_COLOR_FORMAT_RGB444
;
4674 if (edid
->features
& DRM_EDID_FEATURE_RGB_YCRCB444
)
4675 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB444
;
4676 if (edid
->features
& DRM_EDID_FEATURE_RGB_YCRCB422
)
4677 info
->color_formats
|= DRM_COLOR_FORMAT_YCRCB422
;
4681 static int validate_displayid(u8
*displayid
, int length
, int idx
)
4685 struct displayid_hdr
*base
;
4687 base
= (struct displayid_hdr
*)&displayid
[idx
];
4689 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4690 base
->rev
, base
->bytes
, base
->prod_id
, base
->ext_count
);
4692 if (base
->bytes
+ 5 > length
- idx
)
4694 for (i
= idx
; i
<= base
->bytes
+ 5; i
++) {
4695 csum
+= displayid
[i
];
4698 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum
);
4704 static struct drm_display_mode
*drm_mode_displayid_detailed(struct drm_device
*dev
,
4705 struct displayid_detailed_timings_1
*timings
)
4707 struct drm_display_mode
*mode
;
4708 unsigned pixel_clock
= (timings
->pixel_clock
[0] |
4709 (timings
->pixel_clock
[1] << 8) |
4710 (timings
->pixel_clock
[2] << 16)) + 1;
4711 unsigned hactive
= (timings
->hactive
[0] | timings
->hactive
[1] << 8) + 1;
4712 unsigned hblank
= (timings
->hblank
[0] | timings
->hblank
[1] << 8) + 1;
4713 unsigned hsync
= (timings
->hsync
[0] | (timings
->hsync
[1] & 0x7f) << 8) + 1;
4714 unsigned hsync_width
= (timings
->hsw
[0] | timings
->hsw
[1] << 8) + 1;
4715 unsigned vactive
= (timings
->vactive
[0] | timings
->vactive
[1] << 8) + 1;
4716 unsigned vblank
= (timings
->vblank
[0] | timings
->vblank
[1] << 8) + 1;
4717 unsigned vsync
= (timings
->vsync
[0] | (timings
->vsync
[1] & 0x7f) << 8) + 1;
4718 unsigned vsync_width
= (timings
->vsw
[0] | timings
->vsw
[1] << 8) + 1;
4719 bool hsync_positive
= (timings
->hsync
[1] >> 7) & 0x1;
4720 bool vsync_positive
= (timings
->vsync
[1] >> 7) & 0x1;
4721 mode
= drm_mode_create(dev
);
4725 mode
->clock
= pixel_clock
* 10;
4726 mode
->hdisplay
= hactive
;
4727 mode
->hsync_start
= mode
->hdisplay
+ hsync
;
4728 mode
->hsync_end
= mode
->hsync_start
+ hsync_width
;
4729 mode
->htotal
= mode
->hdisplay
+ hblank
;
4731 mode
->vdisplay
= vactive
;
4732 mode
->vsync_start
= mode
->vdisplay
+ vsync
;
4733 mode
->vsync_end
= mode
->vsync_start
+ vsync_width
;
4734 mode
->vtotal
= mode
->vdisplay
+ vblank
;
4737 mode
->flags
|= hsync_positive
? DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
4738 mode
->flags
|= vsync_positive
? DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
4739 mode
->type
= DRM_MODE_TYPE_DRIVER
;
4741 if (timings
->flags
& 0x80)
4742 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4743 mode
->vrefresh
= drm_mode_vrefresh(mode
);
4744 drm_mode_set_name(mode
);
4749 static int add_displayid_detailed_1_modes(struct drm_connector
*connector
,
4750 struct displayid_block
*block
)
4752 struct displayid_detailed_timing_block
*det
= (struct displayid_detailed_timing_block
*)block
;
4755 struct drm_display_mode
*newmode
;
4757 /* blocks must be multiple of 20 bytes length */
4758 if (block
->num_bytes
% 20)
4761 num_timings
= block
->num_bytes
/ 20;
4762 for (i
= 0; i
< num_timings
; i
++) {
4763 struct displayid_detailed_timings_1
*timings
= &det
->timings
[i
];
4765 newmode
= drm_mode_displayid_detailed(connector
->dev
, timings
);
4769 drm_mode_probed_add(connector
, newmode
);
4775 static int add_displayid_detailed_modes(struct drm_connector
*connector
,
4781 int length
= EDID_LENGTH
;
4782 struct displayid_block
*block
;
4785 displayid
= drm_find_displayid_extension(edid
);
4789 ret
= validate_displayid(displayid
, length
, idx
);
4793 idx
+= sizeof(struct displayid_hdr
);
4794 while (block
= (struct displayid_block
*)&displayid
[idx
],
4795 idx
+ sizeof(struct displayid_block
) <= length
&&
4796 idx
+ sizeof(struct displayid_block
) + block
->num_bytes
<= length
&&
4797 block
->num_bytes
> 0) {
4798 idx
+= block
->num_bytes
+ sizeof(struct displayid_block
);
4799 switch (block
->tag
) {
4800 case DATA_BLOCK_TYPE_1_DETAILED_TIMING
:
4801 num_modes
+= add_displayid_detailed_1_modes(connector
, block
);
4809 * drm_add_edid_modes - add modes from EDID data, if available
4810 * @connector: connector we're probing
4813 * Add the specified modes to the connector's mode list. Also fills out the
4814 * &drm_display_info structure and ELD in @connector with any information which
4815 * can be derived from the edid.
4817 * Return: The number of modes added or 0 if we couldn't find any.
4819 int drm_add_edid_modes(struct drm_connector
*connector
, struct edid
*edid
)
4825 clear_eld(connector
);
4828 if (!drm_edid_is_valid(edid
)) {
4829 clear_eld(connector
);
4830 dev_warn(connector
->dev
->dev
, "%s: EDID invalid.\n",
4835 drm_edid_to_eld(connector
, edid
);
4838 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4839 * To avoid multiple parsing of same block, lets parse that map
4840 * from sink info, before parsing CEA modes.
4842 quirks
= drm_add_display_info(connector
, edid
);
4845 * EDID spec says modes should be preferred in this order:
4846 * - preferred detailed mode
4847 * - other detailed modes from base block
4848 * - detailed modes from extension blocks
4849 * - CVT 3-byte code modes
4850 * - standard timing codes
4851 * - established timing codes
4852 * - modes inferred from GTF or CVT range information
4854 * We get this pretty much right.
4856 * XXX order for additional mode types in extension blocks?
4858 num_modes
+= add_detailed_modes(connector
, edid
, quirks
);
4859 num_modes
+= add_cvt_modes(connector
, edid
);
4860 num_modes
+= add_standard_modes(connector
, edid
);
4861 num_modes
+= add_established_modes(connector
, edid
);
4862 num_modes
+= add_cea_modes(connector
, edid
);
4863 num_modes
+= add_alternate_cea_modes(connector
, edid
);
4864 num_modes
+= add_displayid_detailed_modes(connector
, edid
);
4865 if (edid
->features
& DRM_EDID_FEATURE_DEFAULT_GTF
)
4866 num_modes
+= add_inferred_modes(connector
, edid
);
4868 if (quirks
& (EDID_QUIRK_PREFER_LARGE_60
| EDID_QUIRK_PREFER_LARGE_75
))
4869 edid_fixup_preferred(connector
, quirks
);
4871 if (quirks
& EDID_QUIRK_FORCE_6BPC
)
4872 connector
->display_info
.bpc
= 6;
4874 if (quirks
& EDID_QUIRK_FORCE_8BPC
)
4875 connector
->display_info
.bpc
= 8;
4877 if (quirks
& EDID_QUIRK_FORCE_10BPC
)
4878 connector
->display_info
.bpc
= 10;
4880 if (quirks
& EDID_QUIRK_FORCE_12BPC
)
4881 connector
->display_info
.bpc
= 12;
4885 EXPORT_SYMBOL(drm_add_edid_modes
);
4888 * drm_add_modes_noedid - add modes for the connectors without EDID
4889 * @connector: connector we're probing
4890 * @hdisplay: the horizontal display limit
4891 * @vdisplay: the vertical display limit
4893 * Add the specified modes to the connector's mode list. Only when the
4894 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4896 * Return: The number of modes added or 0 if we couldn't find any.
4898 int drm_add_modes_noedid(struct drm_connector
*connector
,
4899 int hdisplay
, int vdisplay
)
4901 int i
, count
, num_modes
= 0;
4902 struct drm_display_mode
*mode
;
4903 struct drm_device
*dev
= connector
->dev
;
4905 count
= ARRAY_SIZE(drm_dmt_modes
);
4911 for (i
= 0; i
< count
; i
++) {
4912 const struct drm_display_mode
*ptr
= &drm_dmt_modes
[i
];
4913 if (hdisplay
&& vdisplay
) {
4915 * Only when two are valid, they will be used to check
4916 * whether the mode should be added to the mode list of
4919 if (ptr
->hdisplay
> hdisplay
||
4920 ptr
->vdisplay
> vdisplay
)
4923 if (drm_mode_vrefresh(ptr
) > 61)
4925 mode
= drm_mode_duplicate(dev
, ptr
);
4927 drm_mode_probed_add(connector
, mode
);
4933 EXPORT_SYMBOL(drm_add_modes_noedid
);
4936 * drm_set_preferred_mode - Sets the preferred mode of a connector
4937 * @connector: connector whose mode list should be processed
4938 * @hpref: horizontal resolution of preferred mode
4939 * @vpref: vertical resolution of preferred mode
4941 * Marks a mode as preferred if it matches the resolution specified by @hpref
4944 void drm_set_preferred_mode(struct drm_connector
*connector
,
4945 int hpref
, int vpref
)
4947 struct drm_display_mode
*mode
;
4949 list_for_each_entry(mode
, &connector
->probed_modes
, head
) {
4950 if (mode
->hdisplay
== hpref
&&
4951 mode
->vdisplay
== vpref
)
4952 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
4955 EXPORT_SYMBOL(drm_set_preferred_mode
);
4958 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4959 * data from a DRM display mode
4960 * @frame: HDMI AVI infoframe
4961 * @mode: DRM display mode
4962 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4964 * Return: 0 on success or a negative error code on failure.
4967 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe
*frame
,
4968 const struct drm_display_mode
*mode
,
4971 enum hdmi_picture_aspect picture_aspect
;
4974 if (!frame
|| !mode
)
4977 err
= hdmi_avi_infoframe_init(frame
);
4981 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
4982 frame
->pixel_repeat
= 1;
4984 frame
->video_code
= drm_match_cea_mode(mode
);
4987 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4988 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4989 * have to make sure we dont break HDMI 1.4 sinks.
4991 if (!is_hdmi2_sink
&& frame
->video_code
> 64)
4992 frame
->video_code
= 0;
4995 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4996 * we should send its VIC in vendor infoframes, else send the
4997 * VIC in AVI infoframes. Lets check if this mode is present in
4998 * HDMI 1.4b 4K modes
5000 if (frame
->video_code
) {
5001 u8 vendor_if_vic
= drm_match_hdmi_mode(mode
);
5002 bool is_s3d
= mode
->flags
& DRM_MODE_FLAG_3D_MASK
;
5004 if (drm_valid_hdmi_vic(vendor_if_vic
) && !is_s3d
)
5005 frame
->video_code
= 0;
5008 frame
->picture_aspect
= HDMI_PICTURE_ASPECT_NONE
;
5011 * As some drivers don't support atomic, we can't use connector state.
5012 * So just initialize the frame with default values, just the same way
5013 * as it's done with other properties here.
5015 frame
->content_type
= HDMI_CONTENT_TYPE_GRAPHICS
;
5019 * Populate picture aspect ratio from either
5020 * user input (if specified) or from the CEA mode list.
5022 picture_aspect
= mode
->picture_aspect_ratio
;
5023 if (picture_aspect
== HDMI_PICTURE_ASPECT_NONE
)
5024 picture_aspect
= drm_get_cea_aspect_ratio(frame
->video_code
);
5027 * The infoframe can't convey anything but none, 4:3
5028 * and 16:9, so if the user has asked for anything else
5029 * we can only satisfy it by specifying the right VIC.
5031 if (picture_aspect
> HDMI_PICTURE_ASPECT_16_9
) {
5032 if (picture_aspect
!=
5033 drm_get_cea_aspect_ratio(frame
->video_code
))
5035 picture_aspect
= HDMI_PICTURE_ASPECT_NONE
;
5038 frame
->picture_aspect
= picture_aspect
;
5039 frame
->active_aspect
= HDMI_ACTIVE_ASPECT_PICTURE
;
5040 frame
->scan_mode
= HDMI_SCAN_MODE_UNDERSCAN
;
5044 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode
);
5047 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5048 * quantization range information
5049 * @frame: HDMI AVI infoframe
5050 * @mode: DRM display mode
5051 * @rgb_quant_range: RGB quantization range (Q)
5052 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
5053 * @is_hdmi2_sink: HDMI 2.0 sink, which has different default recommendations
5055 * Note that @is_hdmi2_sink can be derived by looking at the
5056 * &drm_scdc.supported flag stored in &drm_hdmi_info.scdc,
5057 * &drm_display_info.hdmi, which can be found in &drm_connector.display_info.
5060 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe
*frame
,
5061 const struct drm_display_mode
*mode
,
5062 enum hdmi_quantization_range rgb_quant_range
,
5063 bool rgb_quant_range_selectable
,
5068 * "A Source shall not send a non-zero Q value that does not correspond
5069 * to the default RGB Quantization Range for the transmitted Picture
5070 * unless the Sink indicates support for the Q bit in a Video
5071 * Capabilities Data Block."
5073 * HDMI 2.0 recommends sending non-zero Q when it does match the
5074 * default RGB quantization range for the mode, even when QS=0.
5076 if (rgb_quant_range_selectable
||
5077 rgb_quant_range
== drm_default_rgb_quant_range(mode
))
5078 frame
->quantization_range
= rgb_quant_range
;
5080 frame
->quantization_range
= HDMI_QUANTIZATION_RANGE_DEFAULT
;
5084 * "When transmitting any RGB colorimetry, the Source should set the
5085 * YQ-field to match the RGB Quantization Range being transmitted
5086 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5087 * set YQ=1) and the Sink shall ignore the YQ-field."
5089 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5090 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5091 * good way to tell which version of CEA-861 the sink supports, so
5092 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5095 if (!is_hdmi2_sink
||
5096 rgb_quant_range
== HDMI_QUANTIZATION_RANGE_LIMITED
)
5097 frame
->ycc_quantization_range
=
5098 HDMI_YCC_QUANTIZATION_RANGE_LIMITED
;
5100 frame
->ycc_quantization_range
=
5101 HDMI_YCC_QUANTIZATION_RANGE_FULL
;
5103 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range
);
5105 static enum hdmi_3d_structure
5106 s3d_structure_from_display_mode(const struct drm_display_mode
*mode
)
5108 u32 layout
= mode
->flags
& DRM_MODE_FLAG_3D_MASK
;
5111 case DRM_MODE_FLAG_3D_FRAME_PACKING
:
5112 return HDMI_3D_STRUCTURE_FRAME_PACKING
;
5113 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE
:
5114 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE
;
5115 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE
:
5116 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE
;
5117 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL
:
5118 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL
;
5119 case DRM_MODE_FLAG_3D_L_DEPTH
:
5120 return HDMI_3D_STRUCTURE_L_DEPTH
;
5121 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH
:
5122 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH
;
5123 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM
:
5124 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM
;
5125 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
:
5126 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF
;
5128 return HDMI_3D_STRUCTURE_INVALID
;
5133 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5134 * data from a DRM display mode
5135 * @frame: HDMI vendor infoframe
5136 * @connector: the connector
5137 * @mode: DRM display mode
5139 * Note that there's is a need to send HDMI vendor infoframes only when using a
5140 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5141 * function will return -EINVAL, error that can be safely ignored.
5143 * Return: 0 on success or a negative error code on failure.
5146 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe
*frame
,
5147 struct drm_connector
*connector
,
5148 const struct drm_display_mode
*mode
)
5151 * FIXME: sil-sii8620 doesn't have a connector around when
5152 * we need one, so we have to be prepared for a NULL connector.
5154 bool has_hdmi_infoframe
= connector
?
5155 connector
->display_info
.has_hdmi_infoframe
: false;
5160 if (!frame
|| !mode
)
5163 if (!has_hdmi_infoframe
)
5166 vic
= drm_match_hdmi_mode(mode
);
5167 s3d_flags
= mode
->flags
& DRM_MODE_FLAG_3D_MASK
;
5170 * Even if it's not absolutely necessary to send the infoframe
5171 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5172 * know that the sink can handle it. This is based on a
5173 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5174 * have trouble realizing that they shuld switch from 3D to 2D
5175 * mode if the source simply stops sending the infoframe when
5176 * it wants to switch from 3D to 2D.
5179 if (vic
&& s3d_flags
)
5182 err
= hdmi_vendor_infoframe_init(frame
);
5187 frame
->s3d_struct
= s3d_structure_from_display_mode(mode
);
5191 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode
);
5193 static int drm_parse_tiled_block(struct drm_connector
*connector
,
5194 struct displayid_block
*block
)
5196 struct displayid_tiled_block
*tile
= (struct displayid_tiled_block
*)block
;
5198 u8 tile_v_loc
, tile_h_loc
;
5199 u8 num_v_tile
, num_h_tile
;
5200 struct drm_tile_group
*tg
;
5202 w
= tile
->tile_size
[0] | tile
->tile_size
[1] << 8;
5203 h
= tile
->tile_size
[2] | tile
->tile_size
[3] << 8;
5205 num_v_tile
= (tile
->topo
[0] & 0xf) | (tile
->topo
[2] & 0x30);
5206 num_h_tile
= (tile
->topo
[0] >> 4) | ((tile
->topo
[2] >> 2) & 0x30);
5207 tile_v_loc
= (tile
->topo
[1] & 0xf) | ((tile
->topo
[2] & 0x3) << 4);
5208 tile_h_loc
= (tile
->topo
[1] >> 4) | (((tile
->topo
[2] >> 2) & 0x3) << 4);
5210 connector
->has_tile
= true;
5211 if (tile
->tile_cap
& 0x80)
5212 connector
->tile_is_single_monitor
= true;
5214 connector
->num_h_tile
= num_h_tile
+ 1;
5215 connector
->num_v_tile
= num_v_tile
+ 1;
5216 connector
->tile_h_loc
= tile_h_loc
;
5217 connector
->tile_v_loc
= tile_v_loc
;
5218 connector
->tile_h_size
= w
+ 1;
5219 connector
->tile_v_size
= h
+ 1;
5221 DRM_DEBUG_KMS("tile cap 0x%x\n", tile
->tile_cap
);
5222 DRM_DEBUG_KMS("tile_size %d x %d\n", w
+ 1, h
+ 1);
5223 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5224 num_h_tile
+ 1, num_v_tile
+ 1, tile_h_loc
, tile_v_loc
);
5225 DRM_DEBUG_KMS("vend %c%c%c\n", tile
->topology_id
[0], tile
->topology_id
[1], tile
->topology_id
[2]);
5227 tg
= drm_mode_get_tile_group(connector
->dev
, tile
->topology_id
);
5229 tg
= drm_mode_create_tile_group(connector
->dev
, tile
->topology_id
);
5234 if (connector
->tile_group
!= tg
) {
5235 /* if we haven't got a pointer,
5236 take the reference, drop ref to old tile group */
5237 if (connector
->tile_group
) {
5238 drm_mode_put_tile_group(connector
->dev
, connector
->tile_group
);
5240 connector
->tile_group
= tg
;
5242 /* if same tile group, then release the ref we just took. */
5243 drm_mode_put_tile_group(connector
->dev
, tg
);
5247 static int drm_parse_display_id(struct drm_connector
*connector
,
5248 u8
*displayid
, int length
,
5249 bool is_edid_extension
)
5251 /* if this is an EDID extension the first byte will be 0x70 */
5253 struct displayid_block
*block
;
5256 if (is_edid_extension
)
5259 ret
= validate_displayid(displayid
, length
, idx
);
5263 idx
+= sizeof(struct displayid_hdr
);
5264 while (block
= (struct displayid_block
*)&displayid
[idx
],
5265 idx
+ sizeof(struct displayid_block
) <= length
&&
5266 idx
+ sizeof(struct displayid_block
) + block
->num_bytes
<= length
&&
5267 block
->num_bytes
> 0) {
5268 idx
+= block
->num_bytes
+ sizeof(struct displayid_block
);
5269 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5270 block
->tag
, block
->rev
, block
->num_bytes
);
5272 switch (block
->tag
) {
5273 case DATA_BLOCK_TILED_DISPLAY
:
5274 ret
= drm_parse_tiled_block(connector
, block
);
5278 case DATA_BLOCK_TYPE_1_DETAILED_TIMING
:
5279 /* handled in mode gathering code. */
5281 case DATA_BLOCK_CTA
:
5282 /* handled in the cea parser code. */
5285 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block
->tag
);
5292 static void drm_get_displayid(struct drm_connector
*connector
,
5295 void *displayid
= NULL
;
5297 connector
->has_tile
= false;
5298 displayid
= drm_find_displayid_extension(edid
);
5300 /* drop reference to any tile group we had */
5304 ret
= drm_parse_display_id(connector
, displayid
, EDID_LENGTH
, true);
5307 if (!connector
->has_tile
)
5311 if (connector
->tile_group
) {
5312 drm_mode_put_tile_group(connector
->dev
, connector
->tile_group
);
5313 connector
->tile_group
= NULL
;