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Linux 4.19.133
[linux/fpc-iii.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
blob6a859e077ea0290d115031da247d4dc69033d1eb
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #include <linux/component.h>
7 #include <linux/dma-fence.h>
8 #include <linux/moduleparam.h>
9 #include <linux/of_device.h>
10 #include <linux/thermal.h>
11
12 #include "etnaviv_cmdbuf.h"
13 #include "etnaviv_dump.h"
14 #include "etnaviv_gpu.h"
15 #include "etnaviv_gem.h"
16 #include "etnaviv_mmu.h"
17 #include "etnaviv_perfmon.h"
18 #include "etnaviv_sched.h"
19 #include "common.xml.h"
20 #include "state.xml.h"
21 #include "state_hi.xml.h"
22 #include "cmdstream.xml.h"
23
24 #ifndef PHYS_OFFSET
25 #define PHYS_OFFSET 0
26 #endif
27
28 static const struct platform_device_id gpu_ids[] = {
29 { .name = "etnaviv-gpu,2d" },
30 { },
31 };
32
33 /*
34 * Driver functions:
35 */
36
37 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
38 {
39 switch (param) {
40 case ETNAVIV_PARAM_GPU_MODEL:
41 *value = gpu->identity.model;
42 break;
43
44 case ETNAVIV_PARAM_GPU_REVISION:
45 *value = gpu->identity.revision;
46 break;
47
48 case ETNAVIV_PARAM_GPU_FEATURES_0:
49 *value = gpu->identity.features;
50 break;
51
52 case ETNAVIV_PARAM_GPU_FEATURES_1:
53 *value = gpu->identity.minor_features0;
54 break;
55
56 case ETNAVIV_PARAM_GPU_FEATURES_2:
57 *value = gpu->identity.minor_features1;
58 break;
59
60 case ETNAVIV_PARAM_GPU_FEATURES_3:
61 *value = gpu->identity.minor_features2;
62 break;
63
64 case ETNAVIV_PARAM_GPU_FEATURES_4:
65 *value = gpu->identity.minor_features3;
66 break;
67
68 case ETNAVIV_PARAM_GPU_FEATURES_5:
69 *value = gpu->identity.minor_features4;
70 break;
71
72 case ETNAVIV_PARAM_GPU_FEATURES_6:
73 *value = gpu->identity.minor_features5;
74 break;
75
76 case ETNAVIV_PARAM_GPU_FEATURES_7:
77 *value = gpu->identity.minor_features6;
78 break;
79
80 case ETNAVIV_PARAM_GPU_FEATURES_8:
81 *value = gpu->identity.minor_features7;
82 break;
83
84 case ETNAVIV_PARAM_GPU_FEATURES_9:
85 *value = gpu->identity.minor_features8;
86 break;
87
88 case ETNAVIV_PARAM_GPU_FEATURES_10:
89 *value = gpu->identity.minor_features9;
90 break;
91
92 case ETNAVIV_PARAM_GPU_FEATURES_11:
93 *value = gpu->identity.minor_features10;
94 break;
95
96 case ETNAVIV_PARAM_GPU_FEATURES_12:
97 *value = gpu->identity.minor_features11;
98 break;
99
100 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
101 *value = gpu->identity.stream_count;
102 break;
103
104 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
105 *value = gpu->identity.register_max;
106 break;
107
108 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
109 *value = gpu->identity.thread_count;
110 break;
111
112 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
113 *value = gpu->identity.vertex_cache_size;
114 break;
115
116 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
117 *value = gpu->identity.shader_core_count;
118 break;
119
120 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
121 *value = gpu->identity.pixel_pipes;
122 break;
123
124 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
125 *value = gpu->identity.vertex_output_buffer_size;
126 break;
127
128 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
129 *value = gpu->identity.buffer_size;
130 break;
131
132 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
133 *value = gpu->identity.instruction_count;
134 break;
135
136 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
137 *value = gpu->identity.num_constants;
138 break;
139
140 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
141 *value = gpu->identity.varyings_count;
142 break;
143
144 default:
145 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
146 return -EINVAL;
147 }
148
149 return 0;
150 }
151
152
153 #define etnaviv_is_model_rev(gpu, mod, rev) \
154 ((gpu)->identity.model == chipModel_##mod && \
155 (gpu)->identity.revision == rev)
156 #define etnaviv_field(val, field) \
157 (((val) & field##__MASK) >> field##__SHIFT)
158
159 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
160 {
161 if (gpu->identity.minor_features0 &
162 chipMinorFeatures0_MORE_MINOR_FEATURES) {
163 u32 specs[4];
164 unsigned int streams;
165
166 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
167 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
168 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
169 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
170
171 gpu->identity.stream_count = etnaviv_field(specs[0],
172 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
173 gpu->identity.register_max = etnaviv_field(specs[0],
174 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
175 gpu->identity.thread_count = etnaviv_field(specs[0],
176 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
177 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
178 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
179 gpu->identity.shader_core_count = etnaviv_field(specs[0],
180 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
181 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
182 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
183 gpu->identity.vertex_output_buffer_size =
184 etnaviv_field(specs[0],
185 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
186
187 gpu->identity.buffer_size = etnaviv_field(specs[1],
188 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
189 gpu->identity.instruction_count = etnaviv_field(specs[1],
190 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
191 gpu->identity.num_constants = etnaviv_field(specs[1],
192 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
193
194 gpu->identity.varyings_count = etnaviv_field(specs[2],
195 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
196
197 /* This overrides the value from older register if non-zero */
198 streams = etnaviv_field(specs[3],
199 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
200 if (streams)
201 gpu->identity.stream_count = streams;
202 }
203
204 /* Fill in the stream count if not specified */
205 if (gpu->identity.stream_count == 0) {
206 if (gpu->identity.model >= 0x1000)
207 gpu->identity.stream_count = 4;
208 else
209 gpu->identity.stream_count = 1;
210 }
211
212 /* Convert the register max value */
213 if (gpu->identity.register_max)
214 gpu->identity.register_max = 1 << gpu->identity.register_max;
215 else if (gpu->identity.model == chipModel_GC400)
216 gpu->identity.register_max = 32;
217 else
218 gpu->identity.register_max = 64;
219
220 /* Convert thread count */
221 if (gpu->identity.thread_count)
222 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
223 else if (gpu->identity.model == chipModel_GC400)
224 gpu->identity.thread_count = 64;
225 else if (gpu->identity.model == chipModel_GC500 ||
226 gpu->identity.model == chipModel_GC530)
227 gpu->identity.thread_count = 128;
228 else
229 gpu->identity.thread_count = 256;
230
231 if (gpu->identity.vertex_cache_size == 0)
232 gpu->identity.vertex_cache_size = 8;
233
234 if (gpu->identity.shader_core_count == 0) {
235 if (gpu->identity.model >= 0x1000)
236 gpu->identity.shader_core_count = 2;
237 else
238 gpu->identity.shader_core_count = 1;
239 }
240
241 if (gpu->identity.pixel_pipes == 0)
242 gpu->identity.pixel_pipes = 1;
243
244 /* Convert virtex buffer size */
245 if (gpu->identity.vertex_output_buffer_size) {
246 gpu->identity.vertex_output_buffer_size =
247 1 << gpu->identity.vertex_output_buffer_size;
248 } else if (gpu->identity.model == chipModel_GC400) {
249 if (gpu->identity.revision < 0x4000)
250 gpu->identity.vertex_output_buffer_size = 512;
251 else if (gpu->identity.revision < 0x4200)
252 gpu->identity.vertex_output_buffer_size = 256;
253 else
254 gpu->identity.vertex_output_buffer_size = 128;
255 } else {
256 gpu->identity.vertex_output_buffer_size = 512;
257 }
258
259 switch (gpu->identity.instruction_count) {
260 case 0:
261 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
262 gpu->identity.model == chipModel_GC880)
263 gpu->identity.instruction_count = 512;
264 else
265 gpu->identity.instruction_count = 256;
266 break;
267
268 case 1:
269 gpu->identity.instruction_count = 1024;
270 break;
271
272 case 2:
273 gpu->identity.instruction_count = 2048;
274 break;
275
276 default:
277 gpu->identity.instruction_count = 256;
278 break;
279 }
280
281 if (gpu->identity.num_constants == 0)
282 gpu->identity.num_constants = 168;
283
284 if (gpu->identity.varyings_count == 0) {
285 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
286 gpu->identity.varyings_count = 12;
287 else
288 gpu->identity.varyings_count = 8;
289 }
290
291 /*
292 * For some cores, two varyings are consumed for position, so the
293 * maximum varying count needs to be reduced by one.
294 */
295 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
296 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
297 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
298 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
299 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
300 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
301 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
302 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
303 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
304 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
305 etnaviv_is_model_rev(gpu, GC880, 0x5106))
306 gpu->identity.varyings_count -= 1;
307 }
308
309 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
310 {
311 u32 chipIdentity;
312
313 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
314
315 /* Special case for older graphic cores. */
316 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
317 gpu->identity.model = chipModel_GC500;
318 gpu->identity.revision = etnaviv_field(chipIdentity,
319 VIVS_HI_CHIP_IDENTITY_REVISION);
320 } else {
321
322 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
323 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
324
325 /*
326 * !!!! HACK ALERT !!!!
327 * Because people change device IDs without letting software
328 * know about it - here is the hack to make it all look the
329 * same. Only for GC400 family.
330 */
331 if ((gpu->identity.model & 0xff00) == 0x0400 &&
332 gpu->identity.model != chipModel_GC420) {
333 gpu->identity.model = gpu->identity.model & 0x0400;
334 }
335
336 /* Another special case */
337 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
338 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
339 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
340
341 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
342 /*
343 * This IP has an ECO; put the correct
344 * revision in it.
345 */
346 gpu->identity.revision = 0x1051;
347 }
348 }
349
350 /*
351 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
352 * reality it's just a re-branded GC3000. We can identify this
353 * core by the upper half of the revision register being all 1.
354 * Fix model/rev here, so all other places can refer to this
355 * core by its real identity.
356 */
357 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
358 gpu->identity.model = chipModel_GC3000;
359 gpu->identity.revision &= 0xffff;
360 }
361 }
362
363 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
364 gpu->identity.model, gpu->identity.revision);
365
366 /*
367 * If there is a match in the HWDB, we aren't interested in the
368 * remaining register values, as they might be wrong.
369 */
370 if (etnaviv_fill_identity_from_hwdb(gpu))
371 return;
372
373 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
374
375 /* Disable fast clear on GC700. */
376 if (gpu->identity.model == chipModel_GC700)
377 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
378
379 if ((gpu->identity.model == chipModel_GC500 &&
380 gpu->identity.revision < 2) ||
381 (gpu->identity.model == chipModel_GC300 &&
382 gpu->identity.revision < 0x2000)) {
383
384 /*
385 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
386 * registers.
387 */
388 gpu->identity.minor_features0 = 0;
389 gpu->identity.minor_features1 = 0;
390 gpu->identity.minor_features2 = 0;
391 gpu->identity.minor_features3 = 0;
392 gpu->identity.minor_features4 = 0;
393 gpu->identity.minor_features5 = 0;
394 } else
395 gpu->identity.minor_features0 =
396 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
397
398 if (gpu->identity.minor_features0 &
399 chipMinorFeatures0_MORE_MINOR_FEATURES) {
400 gpu->identity.minor_features1 =
401 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
402 gpu->identity.minor_features2 =
403 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
404 gpu->identity.minor_features3 =
405 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
406 gpu->identity.minor_features4 =
407 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
408 gpu->identity.minor_features5 =
409 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
410 }
411
412 /* GC600 idle register reports zero bits where modules aren't present */
413 if (gpu->identity.model == chipModel_GC600) {
414 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
415 VIVS_HI_IDLE_STATE_RA |
416 VIVS_HI_IDLE_STATE_SE |
417 VIVS_HI_IDLE_STATE_PA |
418 VIVS_HI_IDLE_STATE_SH |
419 VIVS_HI_IDLE_STATE_PE |
420 VIVS_HI_IDLE_STATE_DE |
421 VIVS_HI_IDLE_STATE_FE;
422 } else {
423 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
424 }
425
426 etnaviv_hw_specs(gpu);
427 }
428
429 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
430 {
431 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
432 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
433 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
434 }
435
436 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
437 {
438 if (gpu->identity.minor_features2 &
439 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
440 clk_set_rate(gpu->clk_core,
441 gpu->base_rate_core >> gpu->freq_scale);
442 clk_set_rate(gpu->clk_shader,
443 gpu->base_rate_shader >> gpu->freq_scale);
444 } else {
445 unsigned int fscale = 1 << (6 - gpu->freq_scale);
446 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
447
448 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
449 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
450 etnaviv_gpu_load_clock(gpu, clock);
451 }
452 }
453
454 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
455 {
456 u32 control, idle;
457 unsigned long timeout;
458 bool failed = true;
459
460 /* We hope that the GPU resets in under one second */
461 timeout = jiffies + msecs_to_jiffies(1000);
462
463 while (time_is_after_jiffies(timeout)) {
464 /* enable clock */
465 unsigned int fscale = 1 << (6 - gpu->freq_scale);
466 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
467 etnaviv_gpu_load_clock(gpu, control);
468
469 /* isolate the GPU. */
470 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
471 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
472
473 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
474 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
475 VIVS_MMUv2_AHB_CONTROL_RESET);
476 } else {
477 /* set soft reset. */
478 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
479 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
480 }
481
482 /* wait for reset. */
483 usleep_range(10, 20);
484
485 /* reset soft reset bit. */
486 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
487 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
488
489 /* reset GPU isolation. */
490 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
491 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
492
493 /* read idle register. */
494 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
495
496 /* try reseting again if FE it not idle */
497 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
498 dev_dbg(gpu->dev, "FE is not idle\n");
499 continue;
500 }
501
502 /* read reset register. */
503 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
504
505 /* is the GPU idle? */
506 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
507 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
508 dev_dbg(gpu->dev, "GPU is not idle\n");
509 continue;
510 }
511
512 /* disable debug registers, as they are not normally needed */
513 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
514 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
515
516 failed = false;
517 break;
518 }
519
520 if (failed) {
521 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
522 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
523
524 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
525 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
526 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
527 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
528
529 return -EBUSY;
530 }
531
532 /* We rely on the GPU running, so program the clock */
533 etnaviv_gpu_update_clock(gpu);
534
535 return 0;
536 }
537
538 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
539 {
540 u32 pmc, ppc;
541
542 /* enable clock gating */
543 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
544 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
545
546 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
547 if (gpu->identity.revision == 0x4301 ||
548 gpu->identity.revision == 0x4302)
549 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
550
551 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
552
553 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
554
555 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
556 if (gpu->identity.model >= chipModel_GC400 &&
557 gpu->identity.model != chipModel_GC420 &&
558 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
559 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
560
561 /*
562 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
563 * present without a bug fix.
564 */
565 if (gpu->identity.revision < 0x5000 &&
566 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
567 !(gpu->identity.minor_features1 &
568 chipMinorFeatures1_DISABLE_PE_GATING))
569 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
570
571 if (gpu->identity.revision < 0x5422)
572 pmc |= BIT(15); /* Unknown bit */
573
574 /* Disable TX clock gating on affected core revisions. */
575 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
576 etnaviv_is_model_rev(gpu, GC2000, 0x5108))
577 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
578
579 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
580 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
581
582 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
583 }
584
585 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
586 {
587 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
588 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
589 VIVS_FE_COMMAND_CONTROL_ENABLE |
590 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
591
592 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
593 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
594 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
595 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
596 }
597 }
598
599 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
600 {
601 /*
602 * Base value for VIVS_PM_PULSE_EATER register on models where it
603 * cannot be read, extracted from vivante kernel driver.
604 */
605 u32 pulse_eater = 0x01590880;
606
607 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
608 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
609 pulse_eater |= BIT(23);
610
611 }
612
613 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
614 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
615 pulse_eater &= ~BIT(16);
616 pulse_eater |= BIT(17);
617 }
618
619 if ((gpu->identity.revision > 0x5420) &&
620 (gpu->identity.features & chipFeatures_PIPE_3D))
621 {
622 /* Performance fix: disable internal DFS */
623 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
624 pulse_eater |= BIT(18);
625 }
626
627 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
628 }
629
630 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
631 {
632 u16 prefetch;
633
634 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
635 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
636 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
637 u32 mc_memory_debug;
638
639 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
640
641 if (gpu->identity.revision == 0x5007)
642 mc_memory_debug |= 0x0c;
643 else
644 mc_memory_debug |= 0x08;
645
646 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
647 }
648
649 /* enable module-level clock gating */
650 etnaviv_gpu_enable_mlcg(gpu);
651
652 /*
653 * Update GPU AXI cache atttribute to "cacheable, no allocate".
654 * This is necessary to prevent the iMX6 SoC locking up.
655 */
656 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
657 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
658 VIVS_HI_AXI_CONFIG_ARCACHE(2));
659
660 /* GC2000 rev 5108 needs a special bus config */
661 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
662 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
663 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
664 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
665 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
666 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
667 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
668 }
669
670 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
671 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
672 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
673 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
674 }
675
676 /* setup the pulse eater */
677 etnaviv_gpu_setup_pulse_eater(gpu);
678
679 /* setup the MMU */
680 etnaviv_iommu_restore(gpu);
681
682 /* Start command processor */
683 prefetch = etnaviv_buffer_init(gpu);
684
685 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
686 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
687 prefetch);
688 }
689
690 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
691 {
692 int ret, i;
693
694 ret = pm_runtime_get_sync(gpu->dev);
695 if (ret < 0) {
696 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
697 return ret;
698 }
699
700 etnaviv_hw_identify(gpu);
701
702 if (gpu->identity.model == 0) {
703 dev_err(gpu->dev, "Unknown GPU model\n");
704 ret = -ENXIO;
705 goto fail;
706 }
707
708 /* Exclude VG cores with FE2.0 */
709 if (gpu->identity.features & chipFeatures_PIPE_VG &&
710 gpu->identity.features & chipFeatures_FE20) {
711 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
712 ret = -ENXIO;
713 goto fail;
714 }
715
716 /*
717 * Set the GPU linear window to be at the end of the DMA window, where
718 * the CMA area is likely to reside. This ensures that we are able to
719 * map the command buffers while having the linear window overlap as
720 * much RAM as possible, so we can optimize mappings for other buffers.
721 *
722 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
723 * to different views of the memory on the individual engines.
724 */
725 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
726 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
727 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
728 if (dma_mask < PHYS_OFFSET + SZ_2G)
729 gpu->memory_base = PHYS_OFFSET;
730 else
731 gpu->memory_base = dma_mask - SZ_2G + 1;
732 } else if (PHYS_OFFSET >= SZ_2G) {
733 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
734 gpu->memory_base = PHYS_OFFSET;
735 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
736 }
737
738 /*
739 * On cores with security features supported, we claim control over the
740 * security states.
741 */
742 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
743 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
744 gpu->sec_mode = ETNA_SEC_KERNEL;
745
746 ret = etnaviv_hw_reset(gpu);
747 if (ret) {
748 dev_err(gpu->dev, "GPU reset failed\n");
749 goto fail;
750 }
751
752 gpu->mmu = etnaviv_iommu_new(gpu);
753 if (IS_ERR(gpu->mmu)) {
754 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
755 ret = PTR_ERR(gpu->mmu);
756 goto fail;
757 }
758
759 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
760 if (IS_ERR(gpu->cmdbuf_suballoc)) {
761 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
762 ret = PTR_ERR(gpu->cmdbuf_suballoc);
763 goto destroy_iommu;
764 }
765
766 /* Create buffer: */
767 ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
768 PAGE_SIZE);
769 if (ret) {
770 dev_err(gpu->dev, "could not create command buffer\n");
771 goto destroy_suballoc;
772 }
773
774 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
775 etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
776 ret = -EINVAL;
777 dev_err(gpu->dev,
778 "command buffer outside valid memory window\n");
779 goto free_buffer;
780 }
781
782 /* Setup event management */
783 spin_lock_init(&gpu->event_spinlock);
784 init_completion(&gpu->event_free);
785 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
786 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
787 complete(&gpu->event_free);
788
789 /* Now program the hardware */
790 mutex_lock(&gpu->lock);
791 etnaviv_gpu_hw_init(gpu);
792 gpu->exec_state = -1;
793 mutex_unlock(&gpu->lock);
794
795 pm_runtime_mark_last_busy(gpu->dev);
796 pm_runtime_put_autosuspend(gpu->dev);
797
798 return 0;
799
800 free_buffer:
801 etnaviv_cmdbuf_free(&gpu->buffer);
802 gpu->buffer.suballoc = NULL;
803 destroy_suballoc:
804 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
805 gpu->cmdbuf_suballoc = NULL;
806 destroy_iommu:
807 etnaviv_iommu_destroy(gpu->mmu);
808 gpu->mmu = NULL;
809 fail:
810 pm_runtime_mark_last_busy(gpu->dev);
811 pm_runtime_put_autosuspend(gpu->dev);
812
813 return ret;
814 }
815
816 #ifdef CONFIG_DEBUG_FS
817 struct dma_debug {
818 u32 address[2];
819 u32 state[2];
820 };
821
822 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
823 {
824 u32 i;
825
826 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
827 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
828
829 for (i = 0; i < 500; i++) {
830 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
831 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
832
833 if (debug->address[0] != debug->address[1])
834 break;
835
836 if (debug->state[0] != debug->state[1])
837 break;
838 }
839 }
840
841 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
842 {
843 struct dma_debug debug;
844 u32 dma_lo, dma_hi, axi, idle;
845 int ret;
846
847 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
848
849 ret = pm_runtime_get_sync(gpu->dev);
850 if (ret < 0)
851 return ret;
852
853 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
854 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
855 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
856 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
857
858 verify_dma(gpu, &debug);
859
860 seq_puts(m, "\tfeatures\n");
861 seq_printf(m, "\t major_features: 0x%08x\n",
862 gpu->identity.features);
863 seq_printf(m, "\t minor_features0: 0x%08x\n",
864 gpu->identity.minor_features0);
865 seq_printf(m, "\t minor_features1: 0x%08x\n",
866 gpu->identity.minor_features1);
867 seq_printf(m, "\t minor_features2: 0x%08x\n",
868 gpu->identity.minor_features2);
869 seq_printf(m, "\t minor_features3: 0x%08x\n",
870 gpu->identity.minor_features3);
871 seq_printf(m, "\t minor_features4: 0x%08x\n",
872 gpu->identity.minor_features4);
873 seq_printf(m, "\t minor_features5: 0x%08x\n",
874 gpu->identity.minor_features5);
875 seq_printf(m, "\t minor_features6: 0x%08x\n",
876 gpu->identity.minor_features6);
877 seq_printf(m, "\t minor_features7: 0x%08x\n",
878 gpu->identity.minor_features7);
879 seq_printf(m, "\t minor_features8: 0x%08x\n",
880 gpu->identity.minor_features8);
881 seq_printf(m, "\t minor_features9: 0x%08x\n",
882 gpu->identity.minor_features9);
883 seq_printf(m, "\t minor_features10: 0x%08x\n",
884 gpu->identity.minor_features10);
885 seq_printf(m, "\t minor_features11: 0x%08x\n",
886 gpu->identity.minor_features11);
887
888 seq_puts(m, "\tspecs\n");
889 seq_printf(m, "\t stream_count: %d\n",
890 gpu->identity.stream_count);
891 seq_printf(m, "\t register_max: %d\n",
892 gpu->identity.register_max);
893 seq_printf(m, "\t thread_count: %d\n",
894 gpu->identity.thread_count);
895 seq_printf(m, "\t vertex_cache_size: %d\n",
896 gpu->identity.vertex_cache_size);
897 seq_printf(m, "\t shader_core_count: %d\n",
898 gpu->identity.shader_core_count);
899 seq_printf(m, "\t pixel_pipes: %d\n",
900 gpu->identity.pixel_pipes);
901 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
902 gpu->identity.vertex_output_buffer_size);
903 seq_printf(m, "\t buffer_size: %d\n",
904 gpu->identity.buffer_size);
905 seq_printf(m, "\t instruction_count: %d\n",
906 gpu->identity.instruction_count);
907 seq_printf(m, "\t num_constants: %d\n",
908 gpu->identity.num_constants);
909 seq_printf(m, "\t varyings_count: %d\n",
910 gpu->identity.varyings_count);
911
912 seq_printf(m, "\taxi: 0x%08x\n", axi);
913 seq_printf(m, "\tidle: 0x%08x\n", idle);
914 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
915 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
916 seq_puts(m, "\t FE is not idle\n");
917 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
918 seq_puts(m, "\t DE is not idle\n");
919 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
920 seq_puts(m, "\t PE is not idle\n");
921 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
922 seq_puts(m, "\t SH is not idle\n");
923 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
924 seq_puts(m, "\t PA is not idle\n");
925 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
926 seq_puts(m, "\t SE is not idle\n");
927 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
928 seq_puts(m, "\t RA is not idle\n");
929 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
930 seq_puts(m, "\t TX is not idle\n");
931 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
932 seq_puts(m, "\t VG is not idle\n");
933 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
934 seq_puts(m, "\t IM is not idle\n");
935 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
936 seq_puts(m, "\t FP is not idle\n");
937 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
938 seq_puts(m, "\t TS is not idle\n");
939 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
940 seq_puts(m, "\t AXI low power mode\n");
941
942 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
943 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
944 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
945 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
946
947 seq_puts(m, "\tMC\n");
948 seq_printf(m, "\t read0: 0x%08x\n", read0);
949 seq_printf(m, "\t read1: 0x%08x\n", read1);
950 seq_printf(m, "\t write: 0x%08x\n", write);
951 }
952
953 seq_puts(m, "\tDMA ");
954
955 if (debug.address[0] == debug.address[1] &&
956 debug.state[0] == debug.state[1]) {
957 seq_puts(m, "seems to be stuck\n");
958 } else if (debug.address[0] == debug.address[1]) {
959 seq_puts(m, "address is constant\n");
960 } else {
961 seq_puts(m, "is running\n");
962 }
963
964 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
965 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
966 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
967 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
968 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
969 dma_lo, dma_hi);
970
971 ret = 0;
972
973 pm_runtime_mark_last_busy(gpu->dev);
974 pm_runtime_put_autosuspend(gpu->dev);
975
976 return ret;
977 }
978 #endif
979
980 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
981 {
982 unsigned long flags;
983 unsigned int i = 0;
984
985 dev_err(gpu->dev, "recover hung GPU!\n");
986
987 if (pm_runtime_get_sync(gpu->dev) < 0)
988 return;
989
990 mutex_lock(&gpu->lock);
991
992 etnaviv_hw_reset(gpu);
993
994 /* complete all events, the GPU won't do it after the reset */
995 spin_lock_irqsave(&gpu->event_spinlock, flags);
996 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
997 complete(&gpu->event_free);
998 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
999 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1000 gpu->completed_fence = gpu->active_fence;
1001
1002 etnaviv_gpu_hw_init(gpu);
1003 gpu->lastctx = NULL;
1004 gpu->exec_state = -1;
1005
1006 mutex_unlock(&gpu->lock);
1007 pm_runtime_mark_last_busy(gpu->dev);
1008 pm_runtime_put_autosuspend(gpu->dev);
1009 }
1010
1011 /* fence object management */
1012 struct etnaviv_fence {
1013 struct etnaviv_gpu *gpu;
1014 struct dma_fence base;
1015 };
1016
1017 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1018 {
1019 return container_of(fence, struct etnaviv_fence, base);
1020 }
1021
1022 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1023 {
1024 return "etnaviv";
1025 }
1026
1027 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1028 {
1029 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1030
1031 return dev_name(f->gpu->dev);
1032 }
1033
1034 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1035 {
1036 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1037
1038 return fence_completed(f->gpu, f->base.seqno);
1039 }
1040
1041 static void etnaviv_fence_release(struct dma_fence *fence)
1042 {
1043 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1044
1045 kfree_rcu(f, base.rcu);
1046 }
1047
1048 static const struct dma_fence_ops etnaviv_fence_ops = {
1049 .get_driver_name = etnaviv_fence_get_driver_name,
1050 .get_timeline_name = etnaviv_fence_get_timeline_name,
1051 .signaled = etnaviv_fence_signaled,
1052 .release = etnaviv_fence_release,
1053 };
1054
1055 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1056 {
1057 struct etnaviv_fence *f;
1058
1059 /*
1060 * GPU lock must already be held, otherwise fence completion order might
1061 * not match the seqno order assigned here.
1062 */
1063 lockdep_assert_held(&gpu->lock);
1064
1065 f = kzalloc(sizeof(*f), GFP_KERNEL);
1066 if (!f)
1067 return NULL;
1068
1069 f->gpu = gpu;
1070
1071 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1072 gpu->fence_context, ++gpu->next_fence);
1073
1074 return &f->base;
1075 }
1076
1077 /*
1078 * event management:
1079 */
1080
1081 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1082 unsigned int *events)
1083 {
1084 unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
1085 unsigned i, acquired = 0;
1086
1087 for (i = 0; i < nr_events; i++) {
1088 unsigned long ret;
1089
1090 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1091
1092 if (!ret) {
1093 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1094 goto out;
1095 }
1096
1097 acquired++;
1098 timeout = ret;
1099 }
1100
1101 spin_lock_irqsave(&gpu->event_spinlock, flags);
1102
1103 for (i = 0; i < nr_events; i++) {
1104 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1105
1106 events[i] = event;
1107 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1108 set_bit(event, gpu->event_bitmap);
1109 }
1110
1111 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1112
1113 return 0;
1114
1115 out:
1116 for (i = 0; i < acquired; i++)
1117 complete(&gpu->event_free);
1118
1119 return -EBUSY;
1120 }
1121
1122 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1123 {
1124 unsigned long flags;
1125
1126 spin_lock_irqsave(&gpu->event_spinlock, flags);
1127
1128 if (!test_bit(event, gpu->event_bitmap)) {
1129 dev_warn(gpu->dev, "event %u is already marked as free",
1130 event);
1131 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1132 } else {
1133 clear_bit(event, gpu->event_bitmap);
1134 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1135
1136 complete(&gpu->event_free);
1137 }
1138 }
1139
1140 /*
1141 * Cmdstream submission/retirement:
1142 */
1143 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1144 u32 id, struct timespec *timeout)
1145 {
1146 struct dma_fence *fence;
1147 int ret;
1148
1149 /*
1150 * Look up the fence and take a reference. We might still find a fence
1151 * whose refcount has already dropped to zero. dma_fence_get_rcu
1152 * pretends we didn't find a fence in that case.
1153 */
1154 rcu_read_lock();
1155 fence = idr_find(&gpu->fence_idr, id);
1156 if (fence)
1157 fence = dma_fence_get_rcu(fence);
1158 rcu_read_unlock();
1159
1160 if (!fence)
1161 return 0;
1162
1163 if (!timeout) {
1164 /* No timeout was requested: just test for completion */
1165 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1166 } else {
1167 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1168
1169 ret = dma_fence_wait_timeout(fence, true, remaining);
1170 if (ret == 0)
1171 ret = -ETIMEDOUT;
1172 else if (ret != -ERESTARTSYS)
1173 ret = 0;
1174
1175 }
1176
1177 dma_fence_put(fence);
1178 return ret;
1179 }
1180
1181 /*
1182 * Wait for an object to become inactive. This, on it's own, is not race
1183 * free: the object is moved by the scheduler off the active list, and
1184 * then the iova is put. Moreover, the object could be re-submitted just
1185 * after we notice that it's become inactive.
1186 *
1187 * Although the retirement happens under the gpu lock, we don't want to hold
1188 * that lock in this function while waiting.
1189 */
1190 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1191 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1192 {
1193 unsigned long remaining;
1194 long ret;
1195
1196 if (!timeout)
1197 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1198
1199 remaining = etnaviv_timeout_to_jiffies(timeout);
1200
1201 ret = wait_event_interruptible_timeout(gpu->fence_event,
1202 !is_active(etnaviv_obj),
1203 remaining);
1204 if (ret > 0)
1205 return 0;
1206 else if (ret == -ERESTARTSYS)
1207 return -ERESTARTSYS;
1208 else
1209 return -ETIMEDOUT;
1210 }
1211
1212 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1213 struct etnaviv_event *event, unsigned int flags)
1214 {
1215 const struct etnaviv_gem_submit *submit = event->submit;
1216 unsigned int i;
1217
1218 for (i = 0; i < submit->nr_pmrs; i++) {
1219 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1220
1221 if (pmr->flags == flags)
1222 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1223 }
1224 }
1225
1226 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1227 struct etnaviv_event *event)
1228 {
1229 u32 val;
1230
1231 /* disable clock gating */
1232 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1233 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1234 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1235
1236 /* enable debug register */
1237 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1238 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1239 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1240
1241 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1242 }
1243
1244 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1245 struct etnaviv_event *event)
1246 {
1247 const struct etnaviv_gem_submit *submit = event->submit;
1248 unsigned int i;
1249 u32 val;
1250
1251 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1252
1253 for (i = 0; i < submit->nr_pmrs; i++) {
1254 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1255
1256 *pmr->bo_vma = pmr->sequence;
1257 }
1258
1259 /* disable debug register */
1260 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1261 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1262 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1263
1264 /* enable clock gating */
1265 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1266 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1267 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1268 }
1269
1270
1271 /* add bo's to gpu's ring, and kick gpu: */
1272 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1273 {
1274 struct etnaviv_gpu *gpu = submit->gpu;
1275 struct dma_fence *gpu_fence;
1276 unsigned int i, nr_events = 1, event[3];
1277 int ret;
1278
1279 if (!submit->runtime_resumed) {
1280 ret = pm_runtime_get_sync(gpu->dev);
1281 if (ret < 0)
1282 return NULL;
1283 submit->runtime_resumed = true;
1284 }
1285
1286 /*
1287 * if there are performance monitor requests we need to have
1288 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1289 * requests.
1290 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1291 * and update the sequence number for userspace.
1292 */
1293 if (submit->nr_pmrs)
1294 nr_events = 3;
1295
1296 ret = event_alloc(gpu, nr_events, event);
1297 if (ret) {
1298 DRM_ERROR("no free events\n");
1299 return NULL;
1300 }
1301
1302 mutex_lock(&gpu->lock);
1303
1304 gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1305 if (!gpu_fence) {
1306 for (i = 0; i < nr_events; i++)
1307 event_free(gpu, event[i]);
1308
1309 goto out_unlock;
1310 }
1311
1312 gpu->active_fence = gpu_fence->seqno;
1313
1314 if (submit->nr_pmrs) {
1315 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1316 kref_get(&submit->refcount);
1317 gpu->event[event[1]].submit = submit;
1318 etnaviv_sync_point_queue(gpu, event[1]);
1319 }
1320
1321 gpu->event[event[0]].fence = gpu_fence;
1322 submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1323 etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1324 &submit->cmdbuf);
1325
1326 if (submit->nr_pmrs) {
1327 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1328 kref_get(&submit->refcount);
1329 gpu->event[event[2]].submit = submit;
1330 etnaviv_sync_point_queue(gpu, event[2]);
1331 }
1332
1333 out_unlock:
1334 mutex_unlock(&gpu->lock);
1335
1336 return gpu_fence;
1337 }
1338
1339 static void sync_point_worker(struct work_struct *work)
1340 {
1341 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1342 sync_point_work);
1343 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1344 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1345
1346 event->sync_point(gpu, event);
1347 etnaviv_submit_put(event->submit);
1348 event_free(gpu, gpu->sync_point_event);
1349
1350 /* restart FE last to avoid GPU and IRQ racing against this worker */
1351 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1352 }
1353
1354 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1355 {
1356 u32 status_reg, status;
1357 int i;
1358
1359 if (gpu->sec_mode == ETNA_SEC_NONE)
1360 status_reg = VIVS_MMUv2_STATUS;
1361 else
1362 status_reg = VIVS_MMUv2_SEC_STATUS;
1363
1364 status = gpu_read(gpu, status_reg);
1365 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1366
1367 for (i = 0; i < 4; i++) {
1368 u32 address_reg;
1369
1370 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1371 continue;
1372
1373 if (gpu->sec_mode == ETNA_SEC_NONE)
1374 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1375 else
1376 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1377
1378 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1379 gpu_read(gpu, address_reg));
1380 }
1381 }
1382
1383 static irqreturn_t irq_handler(int irq, void *data)
1384 {
1385 struct etnaviv_gpu *gpu = data;
1386 irqreturn_t ret = IRQ_NONE;
1387
1388 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1389
1390 if (intr != 0) {
1391 int event;
1392
1393 pm_runtime_mark_last_busy(gpu->dev);
1394
1395 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1396
1397 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1398 dev_err(gpu->dev, "AXI bus error\n");
1399 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1400 }
1401
1402 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1403 dump_mmu_fault(gpu);
1404 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1405 }
1406
1407 while ((event = ffs(intr)) != 0) {
1408 struct dma_fence *fence;
1409
1410 event -= 1;
1411
1412 intr &= ~(1 << event);
1413
1414 dev_dbg(gpu->dev, "event %u\n", event);
1415
1416 if (gpu->event[event].sync_point) {
1417 gpu->sync_point_event = event;
1418 queue_work(gpu->wq, &gpu->sync_point_work);
1419 }
1420
1421 fence = gpu->event[event].fence;
1422 if (!fence)
1423 continue;
1424
1425 gpu->event[event].fence = NULL;
1426
1427 /*
1428 * Events can be processed out of order. Eg,
1429 * - allocate and queue event 0
1430 * - allocate event 1
1431 * - event 0 completes, we process it
1432 * - allocate and queue event 0
1433 * - event 1 and event 0 complete
1434 * we can end up processing event 0 first, then 1.
1435 */
1436 if (fence_after(fence->seqno, gpu->completed_fence))
1437 gpu->completed_fence = fence->seqno;
1438 dma_fence_signal(fence);
1439
1440 event_free(gpu, event);
1441 }
1442
1443 ret = IRQ_HANDLED;
1444 }
1445
1446 return ret;
1447 }
1448
1449 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1450 {
1451 int ret;
1452
1453 if (gpu->clk_reg) {
1454 ret = clk_prepare_enable(gpu->clk_reg);
1455 if (ret)
1456 return ret;
1457 }
1458
1459 if (gpu->clk_bus) {
1460 ret = clk_prepare_enable(gpu->clk_bus);
1461 if (ret)
1462 return ret;
1463 }
1464
1465 if (gpu->clk_core) {
1466 ret = clk_prepare_enable(gpu->clk_core);
1467 if (ret)
1468 goto disable_clk_bus;
1469 }
1470
1471 if (gpu->clk_shader) {
1472 ret = clk_prepare_enable(gpu->clk_shader);
1473 if (ret)
1474 goto disable_clk_core;
1475 }
1476
1477 return 0;
1478
1479 disable_clk_core:
1480 if (gpu->clk_core)
1481 clk_disable_unprepare(gpu->clk_core);
1482 disable_clk_bus:
1483 if (gpu->clk_bus)
1484 clk_disable_unprepare(gpu->clk_bus);
1485
1486 return ret;
1487 }
1488
1489 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1490 {
1491 if (gpu->clk_shader)
1492 clk_disable_unprepare(gpu->clk_shader);
1493 if (gpu->clk_core)
1494 clk_disable_unprepare(gpu->clk_core);
1495 if (gpu->clk_bus)
1496 clk_disable_unprepare(gpu->clk_bus);
1497 if (gpu->clk_reg)
1498 clk_disable_unprepare(gpu->clk_reg);
1499
1500 return 0;
1501 }
1502
1503 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1504 {
1505 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1506
1507 do {
1508 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1509
1510 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1511 return 0;
1512
1513 if (time_is_before_jiffies(timeout)) {
1514 dev_warn(gpu->dev,
1515 "timed out waiting for idle: idle=0x%x\n",
1516 idle);
1517 return -ETIMEDOUT;
1518 }
1519
1520 udelay(5);
1521 } while (1);
1522 }
1523
1524 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1525 {
1526 if (gpu->buffer.suballoc) {
1527 /* Replace the last WAIT with END */
1528 mutex_lock(&gpu->lock);
1529 etnaviv_buffer_end(gpu);
1530 mutex_unlock(&gpu->lock);
1531
1532 /*
1533 * We know that only the FE is busy here, this should
1534 * happen quickly (as the WAIT is only 200 cycles). If
1535 * we fail, just warn and continue.
1536 */
1537 etnaviv_gpu_wait_idle(gpu, 100);
1538 }
1539
1540 return etnaviv_gpu_clk_disable(gpu);
1541 }
1542
1543 #ifdef CONFIG_PM
1544 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1545 {
1546 int ret;
1547
1548 ret = mutex_lock_killable(&gpu->lock);
1549 if (ret)
1550 return ret;
1551
1552 etnaviv_gpu_update_clock(gpu);
1553 etnaviv_gpu_hw_init(gpu);
1554
1555 gpu->lastctx = NULL;
1556 gpu->exec_state = -1;
1557
1558 mutex_unlock(&gpu->lock);
1559
1560 return 0;
1561 }
1562 #endif
1563
1564 static int
1565 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1566 unsigned long *state)
1567 {
1568 *state = 6;
1569
1570 return 0;
1571 }
1572
1573 static int
1574 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1575 unsigned long *state)
1576 {
1577 struct etnaviv_gpu *gpu = cdev->devdata;
1578
1579 *state = gpu->freq_scale;
1580
1581 return 0;
1582 }
1583
1584 static int
1585 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1586 unsigned long state)
1587 {
1588 struct etnaviv_gpu *gpu = cdev->devdata;
1589
1590 mutex_lock(&gpu->lock);
1591 gpu->freq_scale = state;
1592 if (!pm_runtime_suspended(gpu->dev))
1593 etnaviv_gpu_update_clock(gpu);
1594 mutex_unlock(&gpu->lock);
1595
1596 return 0;
1597 }
1598
1599 static struct thermal_cooling_device_ops cooling_ops = {
1600 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1601 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1602 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1603 };
1604
1605 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1606 void *data)
1607 {
1608 struct drm_device *drm = data;
1609 struct etnaviv_drm_private *priv = drm->dev_private;
1610 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1611 int ret;
1612
1613 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1614 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1615 (char *)dev_name(dev), gpu, &cooling_ops);
1616 if (IS_ERR(gpu->cooling))
1617 return PTR_ERR(gpu->cooling);
1618 }
1619
1620 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1621 if (!gpu->wq) {
1622 ret = -ENOMEM;
1623 goto out_thermal;
1624 }
1625
1626 ret = etnaviv_sched_init(gpu);
1627 if (ret)
1628 goto out_workqueue;
1629
1630 #ifdef CONFIG_PM
1631 ret = pm_runtime_get_sync(gpu->dev);
1632 #else
1633 ret = etnaviv_gpu_clk_enable(gpu);
1634 #endif
1635 if (ret < 0)
1636 goto out_sched;
1637
1638
1639 gpu->drm = drm;
1640 gpu->fence_context = dma_fence_context_alloc(1);
1641 idr_init(&gpu->fence_idr);
1642 spin_lock_init(&gpu->fence_spinlock);
1643
1644 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1645 init_waitqueue_head(&gpu->fence_event);
1646
1647 priv->gpu[priv->num_gpus++] = gpu;
1648
1649 pm_runtime_mark_last_busy(gpu->dev);
1650 pm_runtime_put_autosuspend(gpu->dev);
1651
1652 return 0;
1653
1654 out_sched:
1655 etnaviv_sched_fini(gpu);
1656
1657 out_workqueue:
1658 destroy_workqueue(gpu->wq);
1659
1660 out_thermal:
1661 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1662 thermal_cooling_device_unregister(gpu->cooling);
1663
1664 return ret;
1665 }
1666
1667 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1668 void *data)
1669 {
1670 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1671
1672 DBG("%s", dev_name(gpu->dev));
1673
1674 flush_workqueue(gpu->wq);
1675 destroy_workqueue(gpu->wq);
1676
1677 etnaviv_sched_fini(gpu);
1678
1679 #ifdef CONFIG_PM
1680 pm_runtime_get_sync(gpu->dev);
1681 pm_runtime_put_sync_suspend(gpu->dev);
1682 #else
1683 etnaviv_gpu_hw_suspend(gpu);
1684 #endif
1685
1686 if (gpu->buffer.suballoc)
1687 etnaviv_cmdbuf_free(&gpu->buffer);
1688
1689 if (gpu->cmdbuf_suballoc) {
1690 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1691 gpu->cmdbuf_suballoc = NULL;
1692 }
1693
1694 if (gpu->mmu) {
1695 etnaviv_iommu_destroy(gpu->mmu);
1696 gpu->mmu = NULL;
1697 }
1698
1699 gpu->drm = NULL;
1700 idr_destroy(&gpu->fence_idr);
1701
1702 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1703 thermal_cooling_device_unregister(gpu->cooling);
1704 gpu->cooling = NULL;
1705 }
1706
1707 static const struct component_ops gpu_ops = {
1708 .bind = etnaviv_gpu_bind,
1709 .unbind = etnaviv_gpu_unbind,
1710 };
1711
1712 static const struct of_device_id etnaviv_gpu_match[] = {
1713 {
1714 .compatible = "vivante,gc"
1715 },
1716 { /* sentinel */ }
1717 };
1718 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1719
1720 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1721 {
1722 struct device *dev = &pdev->dev;
1723 struct etnaviv_gpu *gpu;
1724 struct resource *res;
1725 int err;
1726
1727 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1728 if (!gpu)
1729 return -ENOMEM;
1730
1731 gpu->dev = &pdev->dev;
1732 mutex_init(&gpu->lock);
1733 mutex_init(&gpu->fence_lock);
1734
1735 /* Map registers: */
1736 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1737 gpu->mmio = devm_ioremap_resource(&pdev->dev, res);
1738 if (IS_ERR(gpu->mmio))
1739 return PTR_ERR(gpu->mmio);
1740
1741 /* Get Interrupt: */
1742 gpu->irq = platform_get_irq(pdev, 0);
1743 if (gpu->irq < 0) {
1744 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1745 return gpu->irq;
1746 }
1747
1748 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1749 dev_name(gpu->dev), gpu);
1750 if (err) {
1751 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1752 return err;
1753 }
1754
1755 /* Get Clocks: */
1756 gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
1757 DBG("clk_reg: %p", gpu->clk_reg);
1758 if (IS_ERR(gpu->clk_reg))
1759 gpu->clk_reg = NULL;
1760
1761 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1762 DBG("clk_bus: %p", gpu->clk_bus);
1763 if (IS_ERR(gpu->clk_bus))
1764 gpu->clk_bus = NULL;
1765
1766 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1767 DBG("clk_core: %p", gpu->clk_core);
1768 if (IS_ERR(gpu->clk_core))
1769 gpu->clk_core = NULL;
1770 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1771
1772 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1773 DBG("clk_shader: %p", gpu->clk_shader);
1774 if (IS_ERR(gpu->clk_shader))
1775 gpu->clk_shader = NULL;
1776 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1777
1778 /* TODO: figure out max mapped size */
1779 dev_set_drvdata(dev, gpu);
1780
1781 /*
1782 * We treat the device as initially suspended. The runtime PM
1783 * autosuspend delay is rather arbitary: no measurements have
1784 * yet been performed to determine an appropriate value.
1785 */
1786 pm_runtime_use_autosuspend(gpu->dev);
1787 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1788 pm_runtime_enable(gpu->dev);
1789
1790 err = component_add(&pdev->dev, &gpu_ops);
1791 if (err < 0) {
1792 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1793 return err;
1794 }
1795
1796 return 0;
1797 }
1798
1799 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1800 {
1801 component_del(&pdev->dev, &gpu_ops);
1802 pm_runtime_disable(&pdev->dev);
1803 return 0;
1804 }
1805
1806 #ifdef CONFIG_PM
1807 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1808 {
1809 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1810 u32 idle, mask;
1811
1812 /* If we have outstanding fences, we're not idle */
1813 if (gpu->completed_fence != gpu->active_fence)
1814 return -EBUSY;
1815
1816 /* Check whether the hardware (except FE) is idle */
1817 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1818 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1819 if (idle != mask)
1820 return -EBUSY;
1821
1822 return etnaviv_gpu_hw_suspend(gpu);
1823 }
1824
1825 static int etnaviv_gpu_rpm_resume(struct device *dev)
1826 {
1827 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1828 int ret;
1829
1830 ret = etnaviv_gpu_clk_enable(gpu);
1831 if (ret)
1832 return ret;
1833
1834 /* Re-initialise the basic hardware state */
1835 if (gpu->drm && gpu->buffer.suballoc) {
1836 ret = etnaviv_gpu_hw_resume(gpu);
1837 if (ret) {
1838 etnaviv_gpu_clk_disable(gpu);
1839 return ret;
1840 }
1841 }
1842
1843 return 0;
1844 }
1845 #endif
1846
1847 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1848 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1849 NULL)
1850 };
1851
1852 struct platform_driver etnaviv_gpu_driver = {
1853 .driver = {
1854 .name = "etnaviv-gpu",
1855 .owner = THIS_MODULE,
1856 .pm = &etnaviv_gpu_pm_ops,
1857 .of_match_table = etnaviv_gpu_match,
1858 },
1859 .probe = etnaviv_gpu_platform_probe,
1860 .remove = etnaviv_gpu_platform_remove,
1861 .id_table = gpu_ids,
1862 };
Linux with added FPC-III support