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Linux 4.19.133
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / gvt / cmd_parser.c
blobbe15289bff9c187d3926bd066498d9a89bad45a9
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Kevin Tian <kevin.tian@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
32 * Yulei Zhang <yulei.zhang@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
34 *
35 */
36
37 #include <linux/slab.h>
38 #include "i915_drv.h"
39 #include "gvt.h"
40 #include "i915_pvinfo.h"
41 #include "trace.h"
42
43 #define INVALID_OP (~0U)
44
45 #define OP_LEN_MI 9
46 #define OP_LEN_2D 10
47 #define OP_LEN_3D_MEDIA 16
48 #define OP_LEN_MFX_VC 16
49 #define OP_LEN_VEBOX 16
50
51 #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
52
53 struct sub_op_bits {
54 int hi;
55 int low;
56 };
57 struct decode_info {
58 char *name;
59 int op_len;
60 int nr_sub_op;
61 struct sub_op_bits *sub_op;
62 };
63
64 #define MAX_CMD_BUDGET 0x7fffffff
65 #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
66 #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
67 #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
68
69 #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
70 #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
71 #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
72
73 /* Render Command Map */
74
75 /* MI_* command Opcode (28:23) */
76 #define OP_MI_NOOP 0x0
77 #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
78 #define OP_MI_USER_INTERRUPT 0x2
79 #define OP_MI_WAIT_FOR_EVENT 0x3
80 #define OP_MI_FLUSH 0x4
81 #define OP_MI_ARB_CHECK 0x5
82 #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
83 #define OP_MI_REPORT_HEAD 0x7
84 #define OP_MI_ARB_ON_OFF 0x8
85 #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
86 #define OP_MI_BATCH_BUFFER_END 0xA
87 #define OP_MI_SUSPEND_FLUSH 0xB
88 #define OP_MI_PREDICATE 0xC /* IVB+ */
89 #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
90 #define OP_MI_SET_APPID 0xE /* IVB+ */
91 #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
92 #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
93 #define OP_MI_DISPLAY_FLIP 0x14
94 #define OP_MI_SEMAPHORE_MBOX 0x16
95 #define OP_MI_SET_CONTEXT 0x18
96 #define OP_MI_MATH 0x1A
97 #define OP_MI_URB_CLEAR 0x19
98 #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
99 #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
100
101 #define OP_MI_STORE_DATA_IMM 0x20
102 #define OP_MI_STORE_DATA_INDEX 0x21
103 #define OP_MI_LOAD_REGISTER_IMM 0x22
104 #define OP_MI_UPDATE_GTT 0x23
105 #define OP_MI_STORE_REGISTER_MEM 0x24
106 #define OP_MI_FLUSH_DW 0x26
107 #define OP_MI_CLFLUSH 0x27
108 #define OP_MI_REPORT_PERF_COUNT 0x28
109 #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
110 #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
111 #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
112 #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
113 #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
114 #define OP_MI_2E 0x2E /* BDW+ */
115 #define OP_MI_2F 0x2F /* BDW+ */
116 #define OP_MI_BATCH_BUFFER_START 0x31
117
118 /* Bit definition for dword 0 */
119 #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
120
121 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
122
123 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
124 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
125 #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
126 #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
127
128 /* 2D command: Opcode (28:22) */
129 #define OP_2D(x) ((2<<7) | x)
130
131 #define OP_XY_SETUP_BLT OP_2D(0x1)
132 #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
133 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
134 #define OP_XY_PIXEL_BLT OP_2D(0x24)
135 #define OP_XY_SCANLINES_BLT OP_2D(0x25)
136 #define OP_XY_TEXT_BLT OP_2D(0x26)
137 #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
138 #define OP_XY_COLOR_BLT OP_2D(0x50)
139 #define OP_XY_PAT_BLT OP_2D(0x51)
140 #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
141 #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
142 #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
143 #define OP_XY_FULL_BLT OP_2D(0x55)
144 #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
145 #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
146 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
147 #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
148 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
149 #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
150 #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
151 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
152 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
153 #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
154 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
155
156 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
157 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
158 ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
159
160 #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
161
162 #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
163 #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
164 #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
165
166 #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
167
168 #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
169
170 #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
171 #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
172 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
173 #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
174 #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
175 #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5)
176
177 #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
178 #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
179 #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
180 #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
181
182 #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
183 #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
184 #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
185 #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
186 #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
187 #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
188 #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
189 #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
190 #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
191 #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
192 #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
193 #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
194 #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
195 #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
196 #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
197 #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
198 #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
199 #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
200 #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
201 #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
202 #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
203 #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
204 #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
205 #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
206 #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
207 #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
208 #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
209 #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
210 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
211 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
212 #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
213 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
214 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
215 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
216 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
217 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
218 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
219 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
220 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
221 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
222 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
223 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
224 #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
225 #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
226 #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
227 #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
228 #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
229 #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
230 #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
231 #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
232 #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
233 #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
234 #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
235 #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
236 #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
237 #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
238 #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
239 #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
240 #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
241 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
242 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
243 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
244 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
245 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
246 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
247 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
248
249 #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
250 #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
251 #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
252 #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
253 #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
254 #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
255 #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
256 #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
257 #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
258 #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
259 #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
260
261 #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
262 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
263 #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
264 #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
265 #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
266 #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
267 #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
268 #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
269 #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
270 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
271 #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
272 #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
273 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
274 #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
275 #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
276 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
277 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
278 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
279 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
280 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
281 #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
282 #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
283 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
284 #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
285 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
286 #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
287 #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
288 #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
289
290 /* VCCP Command Parser */
291
292 /*
293 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
294 * git://anongit.freedesktop.org/vaapi/intel-driver
295 * src/i965_defines.h
296 *
297 */
298
299 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
300 (3 << 13 | \
301 (pipeline) << 11 | \
302 (op) << 8 | \
303 (sub_opa) << 5 | \
304 (sub_opb))
305
306 #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
307 #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
308 #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
309 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
310 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
311 #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
312 #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
313 #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
314 #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
315 #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
316 #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
317
318 #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
319
320 #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
321 #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
322 #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
323 #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
324 #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
325 #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
326 #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
327 #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
328 #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
329 #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
330 #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
331 #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
332
333 #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
334 #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
335 #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
336 #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
337 #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
338
339 #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
340 #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
341 #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
342 #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
343 #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
344
345 #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
346 #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
347 #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
348
349 #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
350 #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
351 #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
352
353 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
354 (3 << 13 | \
355 (pipeline) << 11 | \
356 (op) << 8 | \
357 (sub_opa) << 5 | \
358 (sub_opb))
359
360 #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
361 #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
362 #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
363
364 struct parser_exec_state;
365
366 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
367
368 #define GVT_CMD_HASH_BITS 7
369
370 /* which DWords need address fix */
371 #define ADDR_FIX_1(x1) (1 << (x1))
372 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
373 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
374 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
375 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
376
377 struct cmd_info {
378 char *name;
379 u32 opcode;
380
381 #define F_LEN_MASK (1U<<0)
382 #define F_LEN_CONST 1U
383 #define F_LEN_VAR 0U
384
385 /*
386 * command has its own ip advance logic
387 * e.g. MI_BATCH_START, MI_BATCH_END
388 */
389 #define F_IP_ADVANCE_CUSTOM (1<<1)
390
391 #define F_POST_HANDLE (1<<2)
392 u32 flag;
393
394 #define R_RCS (1 << RCS)
395 #define R_VCS1 (1 << VCS)
396 #define R_VCS2 (1 << VCS2)
397 #define R_VCS (R_VCS1 | R_VCS2)
398 #define R_BCS (1 << BCS)
399 #define R_VECS (1 << VECS)
400 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
401 /* rings that support this cmd: BLT/RCS/VCS/VECS */
402 uint16_t rings;
403
404 /* devices that support this cmd: SNB/IVB/HSW/... */
405 uint16_t devices;
406
407 /* which DWords are address that need fix up.
408 * bit 0 means a 32-bit non address operand in command
409 * bit 1 means address operand, which could be 32-bit
410 * or 64-bit depending on different architectures.(
411 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
412 * No matter the address length, each address only takes
413 * one bit in the bitmap.
414 */
415 uint16_t addr_bitmap;
416
417 /* flag == F_LEN_CONST : command length
418 * flag == F_LEN_VAR : length bias bits
419 * Note: length is in DWord
420 */
421 uint8_t len;
422
423 parser_cmd_handler handler;
424 };
425
426 struct cmd_entry {
427 struct hlist_node hlist;
428 struct cmd_info *info;
429 };
430
431 enum {
432 RING_BUFFER_INSTRUCTION,
433 BATCH_BUFFER_INSTRUCTION,
434 BATCH_BUFFER_2ND_LEVEL,
435 };
436
437 enum {
438 GTT_BUFFER,
439 PPGTT_BUFFER
440 };
441
442 struct parser_exec_state {
443 struct intel_vgpu *vgpu;
444 int ring_id;
445
446 int buf_type;
447
448 /* batch buffer address type */
449 int buf_addr_type;
450
451 /* graphics memory address of ring buffer start */
452 unsigned long ring_start;
453 unsigned long ring_size;
454 unsigned long ring_head;
455 unsigned long ring_tail;
456
457 /* instruction graphics memory address */
458 unsigned long ip_gma;
459
460 /* mapped va of the instr_gma */
461 void *ip_va;
462 void *rb_va;
463
464 void *ret_bb_va;
465 /* next instruction when return from batch buffer to ring buffer */
466 unsigned long ret_ip_gma_ring;
467
468 /* next instruction when return from 2nd batch buffer to batch buffer */
469 unsigned long ret_ip_gma_bb;
470
471 /* batch buffer address type (GTT or PPGTT)
472 * used when ret from 2nd level batch buffer
473 */
474 int saved_buf_addr_type;
475 bool is_ctx_wa;
476
477 struct cmd_info *info;
478
479 struct intel_vgpu_workload *workload;
480 };
481
482 #define gmadr_dw_number(s) \
483 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
484
485 static unsigned long bypass_scan_mask = 0;
486
487 /* ring ALL, type = 0 */
488 static struct sub_op_bits sub_op_mi[] = {
489 {31, 29},
490 {28, 23},
491 };
492
493 static struct decode_info decode_info_mi = {
494 "MI",
495 OP_LEN_MI,
496 ARRAY_SIZE(sub_op_mi),
497 sub_op_mi,
498 };
499
500 /* ring RCS, command type 2 */
501 static struct sub_op_bits sub_op_2d[] = {
502 {31, 29},
503 {28, 22},
504 };
505
506 static struct decode_info decode_info_2d = {
507 "2D",
508 OP_LEN_2D,
509 ARRAY_SIZE(sub_op_2d),
510 sub_op_2d,
511 };
512
513 /* ring RCS, command type 3 */
514 static struct sub_op_bits sub_op_3d_media[] = {
515 {31, 29},
516 {28, 27},
517 {26, 24},
518 {23, 16},
519 };
520
521 static struct decode_info decode_info_3d_media = {
522 "3D_Media",
523 OP_LEN_3D_MEDIA,
524 ARRAY_SIZE(sub_op_3d_media),
525 sub_op_3d_media,
526 };
527
528 /* ring VCS, command type 3 */
529 static struct sub_op_bits sub_op_mfx_vc[] = {
530 {31, 29},
531 {28, 27},
532 {26, 24},
533 {23, 21},
534 {20, 16},
535 };
536
537 static struct decode_info decode_info_mfx_vc = {
538 "MFX_VC",
539 OP_LEN_MFX_VC,
540 ARRAY_SIZE(sub_op_mfx_vc),
541 sub_op_mfx_vc,
542 };
543
544 /* ring VECS, command type 3 */
545 static struct sub_op_bits sub_op_vebox[] = {
546 {31, 29},
547 {28, 27},
548 {26, 24},
549 {23, 21},
550 {20, 16},
551 };
552
553 static struct decode_info decode_info_vebox = {
554 "VEBOX",
555 OP_LEN_VEBOX,
556 ARRAY_SIZE(sub_op_vebox),
557 sub_op_vebox,
558 };
559
560 static struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
561 [RCS] = {
562 &decode_info_mi,
563 NULL,
564 NULL,
565 &decode_info_3d_media,
566 NULL,
567 NULL,
568 NULL,
569 NULL,
570 },
571
572 [VCS] = {
573 &decode_info_mi,
574 NULL,
575 NULL,
576 &decode_info_mfx_vc,
577 NULL,
578 NULL,
579 NULL,
580 NULL,
581 },
582
583 [BCS] = {
584 &decode_info_mi,
585 NULL,
586 &decode_info_2d,
587 NULL,
588 NULL,
589 NULL,
590 NULL,
591 NULL,
592 },
593
594 [VECS] = {
595 &decode_info_mi,
596 NULL,
597 NULL,
598 &decode_info_vebox,
599 NULL,
600 NULL,
601 NULL,
602 NULL,
603 },
604
605 [VCS2] = {
606 &decode_info_mi,
607 NULL,
608 NULL,
609 &decode_info_mfx_vc,
610 NULL,
611 NULL,
612 NULL,
613 NULL,
614 },
615 };
616
617 static inline u32 get_opcode(u32 cmd, int ring_id)
618 {
619 struct decode_info *d_info;
620
621 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
622 if (d_info == NULL)
623 return INVALID_OP;
624
625 return cmd >> (32 - d_info->op_len);
626 }
627
628 static inline struct cmd_info *find_cmd_entry(struct intel_gvt *gvt,
629 unsigned int opcode, int ring_id)
630 {
631 struct cmd_entry *e;
632
633 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
634 if ((opcode == e->info->opcode) &&
635 (e->info->rings & (1 << ring_id)))
636 return e->info;
637 }
638 return NULL;
639 }
640
641 static inline struct cmd_info *get_cmd_info(struct intel_gvt *gvt,
642 u32 cmd, int ring_id)
643 {
644 u32 opcode;
645
646 opcode = get_opcode(cmd, ring_id);
647 if (opcode == INVALID_OP)
648 return NULL;
649
650 return find_cmd_entry(gvt, opcode, ring_id);
651 }
652
653 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
654 {
655 return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
656 }
657
658 static inline void print_opcode(u32 cmd, int ring_id)
659 {
660 struct decode_info *d_info;
661 int i;
662
663 d_info = ring_decode_info[ring_id][CMD_TYPE(cmd)];
664 if (d_info == NULL)
665 return;
666
667 gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
668 cmd >> (32 - d_info->op_len), d_info->name);
669
670 for (i = 0; i < d_info->nr_sub_op; i++)
671 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
672 d_info->sub_op[i].low));
673
674 pr_err("\n");
675 }
676
677 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
678 {
679 return s->ip_va + (index << 2);
680 }
681
682 static inline u32 cmd_val(struct parser_exec_state *s, int index)
683 {
684 return *cmd_ptr(s, index);
685 }
686
687 static void parser_exec_state_dump(struct parser_exec_state *s)
688 {
689 int cnt = 0;
690 int i;
691
692 gvt_dbg_cmd(" vgpu%d RING%d: ring_start(%08lx) ring_end(%08lx)"
693 " ring_head(%08lx) ring_tail(%08lx)\n", s->vgpu->id,
694 s->ring_id, s->ring_start, s->ring_start + s->ring_size,
695 s->ring_head, s->ring_tail);
696
697 gvt_dbg_cmd(" %s %s ip_gma(%08lx) ",
698 s->buf_type == RING_BUFFER_INSTRUCTION ?
699 "RING_BUFFER" : "BATCH_BUFFER",
700 s->buf_addr_type == GTT_BUFFER ?
701 "GTT" : "PPGTT", s->ip_gma);
702
703 if (s->ip_va == NULL) {
704 gvt_dbg_cmd(" ip_va(NULL)");
705 return;
706 }
707
708 gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n",
709 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
710 cmd_val(s, 2), cmd_val(s, 3));
711
712 print_opcode(cmd_val(s, 0), s->ring_id);
713
714 s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
715
716 while (cnt < 1024) {
717 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
718 for (i = 0; i < 8; i++)
719 gvt_dbg_cmd("%08x ", cmd_val(s, i));
720 gvt_dbg_cmd("\n");
721
722 s->ip_va += 8 * sizeof(u32);
723 cnt += 8;
724 }
725 }
726
727 static inline void update_ip_va(struct parser_exec_state *s)
728 {
729 unsigned long len = 0;
730
731 if (WARN_ON(s->ring_head == s->ring_tail))
732 return;
733
734 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
735 unsigned long ring_top = s->ring_start + s->ring_size;
736
737 if (s->ring_head > s->ring_tail) {
738 if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
739 len = (s->ip_gma - s->ring_head);
740 else if (s->ip_gma >= s->ring_start &&
741 s->ip_gma <= s->ring_tail)
742 len = (ring_top - s->ring_head) +
743 (s->ip_gma - s->ring_start);
744 } else
745 len = (s->ip_gma - s->ring_head);
746
747 s->ip_va = s->rb_va + len;
748 } else {/* shadow batch buffer */
749 s->ip_va = s->ret_bb_va;
750 }
751 }
752
753 static inline int ip_gma_set(struct parser_exec_state *s,
754 unsigned long ip_gma)
755 {
756 WARN_ON(!IS_ALIGNED(ip_gma, 4));
757
758 s->ip_gma = ip_gma;
759 update_ip_va(s);
760 return 0;
761 }
762
763 static inline int ip_gma_advance(struct parser_exec_state *s,
764 unsigned int dw_len)
765 {
766 s->ip_gma += (dw_len << 2);
767
768 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
769 if (s->ip_gma >= s->ring_start + s->ring_size)
770 s->ip_gma -= s->ring_size;
771 update_ip_va(s);
772 } else {
773 s->ip_va += (dw_len << 2);
774 }
775
776 return 0;
777 }
778
779 static inline int get_cmd_length(struct cmd_info *info, u32 cmd)
780 {
781 if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
782 return info->len;
783 else
784 return (cmd & ((1U << info->len) - 1)) + 2;
785 return 0;
786 }
787
788 static inline int cmd_length(struct parser_exec_state *s)
789 {
790 return get_cmd_length(s->info, cmd_val(s, 0));
791 }
792
793 /* do not remove this, some platform may need clflush here */
794 #define patch_value(s, addr, val) do { \
795 *addr = val; \
796 } while (0)
797
798 static bool is_shadowed_mmio(unsigned int offset)
799 {
800 bool ret = false;
801
802 if ((offset == 0x2168) || /*BB current head register UDW */
803 (offset == 0x2140) || /*BB current header register */
804 (offset == 0x211c) || /*second BB header register UDW */
805 (offset == 0x2114)) { /*second BB header register UDW */
806 ret = true;
807 }
808 return ret;
809 }
810
811 static inline bool is_force_nonpriv_mmio(unsigned int offset)
812 {
813 return (offset >= 0x24d0 && offset < 0x2500);
814 }
815
816 static int force_nonpriv_reg_handler(struct parser_exec_state *s,
817 unsigned int offset, unsigned int index, char *cmd)
818 {
819 struct intel_gvt *gvt = s->vgpu->gvt;
820 unsigned int data;
821 u32 ring_base;
822 u32 nopid;
823 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
824
825 if (!strcmp(cmd, "lri"))
826 data = cmd_val(s, index + 1);
827 else {
828 gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",
829 offset, cmd);
830 return -EINVAL;
831 }
832
833 ring_base = dev_priv->engine[s->ring_id]->mmio_base;
834 nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));
835
836 if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&
837 data != nopid) {
838 gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
839 offset, data);
840 patch_value(s, cmd_ptr(s, index), nopid);
841 return 0;
842 }
843 return 0;
844 }
845
846 static inline bool is_mocs_mmio(unsigned int offset)
847 {
848 return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
849 ((offset >= 0xb020) && (offset <= 0xb0a0));
850 }
851
852 static int mocs_cmd_reg_handler(struct parser_exec_state *s,
853 unsigned int offset, unsigned int index)
854 {
855 if (!is_mocs_mmio(offset))
856 return -EINVAL;
857 vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);
858 return 0;
859 }
860
861 static int cmd_reg_handler(struct parser_exec_state *s,
862 unsigned int offset, unsigned int index, char *cmd)
863 {
864 struct intel_vgpu *vgpu = s->vgpu;
865 struct intel_gvt *gvt = vgpu->gvt;
866 u32 ctx_sr_ctl;
867
868 if (offset + 4 > gvt->device_info.mmio_size) {
869 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
870 cmd, offset);
871 return -EFAULT;
872 }
873
874 if (!intel_gvt_mmio_is_cmd_access(gvt, offset)) {
875 gvt_vgpu_err("%s access to non-render register (%x)\n",
876 cmd, offset);
877 return -EBADRQC;
878 }
879
880 if (is_shadowed_mmio(offset)) {
881 gvt_vgpu_err("found access of shadowed MMIO %x\n", offset);
882 return 0;
883 }
884
885 if (is_mocs_mmio(offset) &&
886 mocs_cmd_reg_handler(s, offset, index))
887 return -EINVAL;
888
889 if (is_force_nonpriv_mmio(offset) &&
890 force_nonpriv_reg_handler(s, offset, index, cmd))
891 return -EPERM;
892
893 if (offset == i915_mmio_reg_offset(DERRMR) ||
894 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
895 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
896 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
897 }
898
899 /* TODO
900 * Right now only scan LRI command on KBL and in inhibit context.
901 * It's good enough to support initializing mmio by lri command in
902 * vgpu inhibit context on KBL.
903 */
904 if (IS_KABYLAKE(s->vgpu->gvt->dev_priv) &&
905 intel_gvt_mmio_is_in_ctx(gvt, offset) &&
906 !strncmp(cmd, "lri", 3)) {
907 intel_gvt_hypervisor_read_gpa(s->vgpu,
908 s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
909 /* check inhibit context */
910 if (ctx_sr_ctl & 1) {
911 u32 data = cmd_val(s, index + 1);
912
913 if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
914 intel_vgpu_mask_mmio_write(vgpu,
915 offset, &data, 4);
916 else
917 vgpu_vreg(vgpu, offset) = data;
918 }
919 }
920
921 /* TODO: Update the global mask if this MMIO is a masked-MMIO */
922 intel_gvt_mmio_set_cmd_accessed(gvt, offset);
923 return 0;
924 }
925
926 #define cmd_reg(s, i) \
927 (cmd_val(s, i) & GENMASK(22, 2))
928
929 #define cmd_reg_inhibit(s, i) \
930 (cmd_val(s, i) & GENMASK(22, 18))
931
932 #define cmd_gma(s, i) \
933 (cmd_val(s, i) & GENMASK(31, 2))
934
935 #define cmd_gma_hi(s, i) \
936 (cmd_val(s, i) & GENMASK(15, 0))
937
938 static int cmd_handler_lri(struct parser_exec_state *s)
939 {
940 int i, ret = 0;
941 int cmd_len = cmd_length(s);
942 struct intel_gvt *gvt = s->vgpu->gvt;
943
944 for (i = 1; i < cmd_len; i += 2) {
945 if (IS_BROADWELL(gvt->dev_priv) &&
946 (s->ring_id != RCS)) {
947 if (s->ring_id == BCS &&
948 cmd_reg(s, i) ==
949 i915_mmio_reg_offset(DERRMR))
950 ret |= 0;
951 else
952 ret |= (cmd_reg_inhibit(s, i)) ?
953 -EBADRQC : 0;
954 }
955 if (ret)
956 break;
957 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
958 if (ret)
959 break;
960 }
961 return ret;
962 }
963
964 static int cmd_handler_lrr(struct parser_exec_state *s)
965 {
966 int i, ret = 0;
967 int cmd_len = cmd_length(s);
968
969 for (i = 1; i < cmd_len; i += 2) {
970 if (IS_BROADWELL(s->vgpu->gvt->dev_priv))
971 ret |= ((cmd_reg_inhibit(s, i) ||
972 (cmd_reg_inhibit(s, i + 1)))) ?
973 -EBADRQC : 0;
974 if (ret)
975 break;
976 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
977 if (ret)
978 break;
979 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
980 if (ret)
981 break;
982 }
983 return ret;
984 }
985
986 static inline int cmd_address_audit(struct parser_exec_state *s,
987 unsigned long guest_gma, int op_size, bool index_mode);
988
989 static int cmd_handler_lrm(struct parser_exec_state *s)
990 {
991 struct intel_gvt *gvt = s->vgpu->gvt;
992 int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
993 unsigned long gma;
994 int i, ret = 0;
995 int cmd_len = cmd_length(s);
996
997 for (i = 1; i < cmd_len;) {
998 if (IS_BROADWELL(gvt->dev_priv))
999 ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1000 if (ret)
1001 break;
1002 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1003 if (ret)
1004 break;
1005 if (cmd_val(s, 0) & (1 << 22)) {
1006 gma = cmd_gma(s, i + 1);
1007 if (gmadr_bytes == 8)
1008 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1009 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1010 if (ret)
1011 break;
1012 }
1013 i += gmadr_dw_number(s) + 1;
1014 }
1015 return ret;
1016 }
1017
1018 static int cmd_handler_srm(struct parser_exec_state *s)
1019 {
1020 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1021 unsigned long gma;
1022 int i, ret = 0;
1023 int cmd_len = cmd_length(s);
1024
1025 for (i = 1; i < cmd_len;) {
1026 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1027 if (ret)
1028 break;
1029 if (cmd_val(s, 0) & (1 << 22)) {
1030 gma = cmd_gma(s, i + 1);
1031 if (gmadr_bytes == 8)
1032 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1033 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1034 if (ret)
1035 break;
1036 }
1037 i += gmadr_dw_number(s) + 1;
1038 }
1039 return ret;
1040 }
1041
1042 struct cmd_interrupt_event {
1043 int pipe_control_notify;
1044 int mi_flush_dw;
1045 int mi_user_interrupt;
1046 };
1047
1048 static struct cmd_interrupt_event cmd_interrupt_events[] = {
1049 [RCS] = {
1050 .pipe_control_notify = RCS_PIPE_CONTROL,
1051 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1052 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1053 },
1054 [BCS] = {
1055 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1056 .mi_flush_dw = BCS_MI_FLUSH_DW,
1057 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1058 },
1059 [VCS] = {
1060 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1061 .mi_flush_dw = VCS_MI_FLUSH_DW,
1062 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1063 },
1064 [VCS2] = {
1065 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1066 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1067 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1068 },
1069 [VECS] = {
1070 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1071 .mi_flush_dw = VECS_MI_FLUSH_DW,
1072 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1073 },
1074 };
1075
1076 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1077 {
1078 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1079 unsigned long gma;
1080 bool index_mode = false;
1081 unsigned int post_sync;
1082 int ret = 0;
1083
1084 post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1085
1086 /* LRI post sync */
1087 if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1088 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1089 /* post sync */
1090 else if (post_sync) {
1091 if (post_sync == 2)
1092 ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1093 else if (post_sync == 3)
1094 ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1095 else if (post_sync == 1) {
1096 /* check ggtt*/
1097 if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1098 gma = cmd_val(s, 2) & GENMASK(31, 3);
1099 if (gmadr_bytes == 8)
1100 gma |= (cmd_gma_hi(s, 3)) << 32;
1101 /* Store Data Index */
1102 if (cmd_val(s, 1) & (1 << 21))
1103 index_mode = true;
1104 ret |= cmd_address_audit(s, gma, sizeof(u64),
1105 index_mode);
1106 }
1107 }
1108 }
1109
1110 if (ret)
1111 return ret;
1112
1113 if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1114 set_bit(cmd_interrupt_events[s->ring_id].pipe_control_notify,
1115 s->workload->pending_events);
1116 return 0;
1117 }
1118
1119 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1120 {
1121 set_bit(cmd_interrupt_events[s->ring_id].mi_user_interrupt,
1122 s->workload->pending_events);
1123 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1124 return 0;
1125 }
1126
1127 static int cmd_advance_default(struct parser_exec_state *s)
1128 {
1129 return ip_gma_advance(s, cmd_length(s));
1130 }
1131
1132 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1133 {
1134 int ret;
1135
1136 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1137 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1138 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1139 s->buf_addr_type = s->saved_buf_addr_type;
1140 } else {
1141 s->buf_type = RING_BUFFER_INSTRUCTION;
1142 s->buf_addr_type = GTT_BUFFER;
1143 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1144 s->ret_ip_gma_ring -= s->ring_size;
1145 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1146 }
1147 return ret;
1148 }
1149
1150 struct mi_display_flip_command_info {
1151 int pipe;
1152 int plane;
1153 int event;
1154 i915_reg_t stride_reg;
1155 i915_reg_t ctrl_reg;
1156 i915_reg_t surf_reg;
1157 u64 stride_val;
1158 u64 tile_val;
1159 u64 surf_val;
1160 bool async_flip;
1161 };
1162
1163 struct plane_code_mapping {
1164 int pipe;
1165 int plane;
1166 int event;
1167 };
1168
1169 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1170 struct mi_display_flip_command_info *info)
1171 {
1172 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1173 struct plane_code_mapping gen8_plane_code[] = {
1174 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1175 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1176 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1177 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1178 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1179 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1180 };
1181 u32 dword0, dword1, dword2;
1182 u32 v;
1183
1184 dword0 = cmd_val(s, 0);
1185 dword1 = cmd_val(s, 1);
1186 dword2 = cmd_val(s, 2);
1187
1188 v = (dword0 & GENMASK(21, 19)) >> 19;
1189 if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))
1190 return -EBADRQC;
1191
1192 info->pipe = gen8_plane_code[v].pipe;
1193 info->plane = gen8_plane_code[v].plane;
1194 info->event = gen8_plane_code[v].event;
1195 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1196 info->tile_val = (dword1 & 0x1);
1197 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1198 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1199
1200 if (info->plane == PLANE_A) {
1201 info->ctrl_reg = DSPCNTR(info->pipe);
1202 info->stride_reg = DSPSTRIDE(info->pipe);
1203 info->surf_reg = DSPSURF(info->pipe);
1204 } else if (info->plane == PLANE_B) {
1205 info->ctrl_reg = SPRCTL(info->pipe);
1206 info->stride_reg = SPRSTRIDE(info->pipe);
1207 info->surf_reg = SPRSURF(info->pipe);
1208 } else {
1209 WARN_ON(1);
1210 return -EBADRQC;
1211 }
1212 return 0;
1213 }
1214
1215 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1216 struct mi_display_flip_command_info *info)
1217 {
1218 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1219 struct intel_vgpu *vgpu = s->vgpu;
1220 u32 dword0 = cmd_val(s, 0);
1221 u32 dword1 = cmd_val(s, 1);
1222 u32 dword2 = cmd_val(s, 2);
1223 u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1224
1225 info->plane = PRIMARY_PLANE;
1226
1227 switch (plane) {
1228 case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1229 info->pipe = PIPE_A;
1230 info->event = PRIMARY_A_FLIP_DONE;
1231 break;
1232 case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1233 info->pipe = PIPE_B;
1234 info->event = PRIMARY_B_FLIP_DONE;
1235 break;
1236 case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1237 info->pipe = PIPE_C;
1238 info->event = PRIMARY_C_FLIP_DONE;
1239 break;
1240
1241 case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1242 info->pipe = PIPE_A;
1243 info->event = SPRITE_A_FLIP_DONE;
1244 info->plane = SPRITE_PLANE;
1245 break;
1246 case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1247 info->pipe = PIPE_B;
1248 info->event = SPRITE_B_FLIP_DONE;
1249 info->plane = SPRITE_PLANE;
1250 break;
1251 case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1252 info->pipe = PIPE_C;
1253 info->event = SPRITE_C_FLIP_DONE;
1254 info->plane = SPRITE_PLANE;
1255 break;
1256
1257 default:
1258 gvt_vgpu_err("unknown plane code %d\n", plane);
1259 return -EBADRQC;
1260 }
1261
1262 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1263 info->tile_val = (dword1 & GENMASK(2, 0));
1264 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1265 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1266
1267 info->ctrl_reg = DSPCNTR(info->pipe);
1268 info->stride_reg = DSPSTRIDE(info->pipe);
1269 info->surf_reg = DSPSURF(info->pipe);
1270
1271 return 0;
1272 }
1273
1274 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1275 struct mi_display_flip_command_info *info)
1276 {
1277 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1278 u32 stride, tile;
1279
1280 if (!info->async_flip)
1281 return 0;
1282
1283 if (IS_SKYLAKE(dev_priv)
1284 || IS_KABYLAKE(dev_priv)
1285 || IS_BROXTON(dev_priv)) {
1286 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1287 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1288 GENMASK(12, 10)) >> 10;
1289 } else {
1290 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1291 GENMASK(15, 6)) >> 6;
1292 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1293 }
1294
1295 if (stride != info->stride_val)
1296 gvt_dbg_cmd("cannot change stride during async flip\n");
1297
1298 if (tile != info->tile_val)
1299 gvt_dbg_cmd("cannot change tile during async flip\n");
1300
1301 return 0;
1302 }
1303
1304 static int gen8_update_plane_mmio_from_mi_display_flip(
1305 struct parser_exec_state *s,
1306 struct mi_display_flip_command_info *info)
1307 {
1308 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1309 struct intel_vgpu *vgpu = s->vgpu;
1310
1311 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1312 info->surf_val << 12);
1313 if (IS_SKYLAKE(dev_priv)
1314 || IS_KABYLAKE(dev_priv)
1315 || IS_BROXTON(dev_priv)) {
1316 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1317 info->stride_val);
1318 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1319 info->tile_val << 10);
1320 } else {
1321 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1322 info->stride_val << 6);
1323 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1324 info->tile_val << 10);
1325 }
1326
1327 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;
1328 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1329 return 0;
1330 }
1331
1332 static int decode_mi_display_flip(struct parser_exec_state *s,
1333 struct mi_display_flip_command_info *info)
1334 {
1335 struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;
1336
1337 if (IS_BROADWELL(dev_priv))
1338 return gen8_decode_mi_display_flip(s, info);
1339 if (IS_SKYLAKE(dev_priv)
1340 || IS_KABYLAKE(dev_priv)
1341 || IS_BROXTON(dev_priv))
1342 return skl_decode_mi_display_flip(s, info);
1343
1344 return -ENODEV;
1345 }
1346
1347 static int check_mi_display_flip(struct parser_exec_state *s,
1348 struct mi_display_flip_command_info *info)
1349 {
1350 return gen8_check_mi_display_flip(s, info);
1351 }
1352
1353 static int update_plane_mmio_from_mi_display_flip(
1354 struct parser_exec_state *s,
1355 struct mi_display_flip_command_info *info)
1356 {
1357 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1358 }
1359
1360 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1361 {
1362 struct mi_display_flip_command_info info;
1363 struct intel_vgpu *vgpu = s->vgpu;
1364 int ret;
1365 int i;
1366 int len = cmd_length(s);
1367
1368 ret = decode_mi_display_flip(s, &info);
1369 if (ret) {
1370 gvt_vgpu_err("fail to decode MI display flip command\n");
1371 return ret;
1372 }
1373
1374 ret = check_mi_display_flip(s, &info);
1375 if (ret) {
1376 gvt_vgpu_err("invalid MI display flip command\n");
1377 return ret;
1378 }
1379
1380 ret = update_plane_mmio_from_mi_display_flip(s, &info);
1381 if (ret) {
1382 gvt_vgpu_err("fail to update plane mmio\n");
1383 return ret;
1384 }
1385
1386 for (i = 0; i < len; i++)
1387 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1388 return 0;
1389 }
1390
1391 static bool is_wait_for_flip_pending(u32 cmd)
1392 {
1393 return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1394 MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1395 MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1396 MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1397 MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1398 MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1399 }
1400
1401 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1402 {
1403 u32 cmd = cmd_val(s, 0);
1404
1405 if (!is_wait_for_flip_pending(cmd))
1406 return 0;
1407
1408 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1409 return 0;
1410 }
1411
1412 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1413 {
1414 unsigned long addr;
1415 unsigned long gma_high, gma_low;
1416 struct intel_vgpu *vgpu = s->vgpu;
1417 int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1418
1419 if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1420 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1421 return INTEL_GVT_INVALID_ADDR;
1422 }
1423
1424 gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1425 if (gmadr_bytes == 4) {
1426 addr = gma_low;
1427 } else {
1428 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1429 addr = (((unsigned long)gma_high) << 32) | gma_low;
1430 }
1431 return addr;
1432 }
1433
1434 static inline int cmd_address_audit(struct parser_exec_state *s,
1435 unsigned long guest_gma, int op_size, bool index_mode)
1436 {
1437 struct intel_vgpu *vgpu = s->vgpu;
1438 u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1439 int i;
1440 int ret;
1441
1442 if (op_size > max_surface_size) {
1443 gvt_vgpu_err("command address audit fail name %s\n",
1444 s->info->name);
1445 return -EFAULT;
1446 }
1447
1448 if (index_mode) {
1449 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1450 ret = -EFAULT;
1451 goto err;
1452 }
1453 } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1454 ret = -EFAULT;
1455 goto err;
1456 }
1457
1458 return 0;
1459
1460 err:
1461 gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1462 s->info->name, guest_gma, op_size);
1463
1464 pr_err("cmd dump: ");
1465 for (i = 0; i < cmd_length(s); i++) {
1466 if (!(i % 4))
1467 pr_err("\n%08x ", cmd_val(s, i));
1468 else
1469 pr_err("%08x ", cmd_val(s, i));
1470 }
1471 pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1472 vgpu->id,
1473 vgpu_aperture_gmadr_base(vgpu),
1474 vgpu_aperture_gmadr_end(vgpu),
1475 vgpu_hidden_gmadr_base(vgpu),
1476 vgpu_hidden_gmadr_end(vgpu));
1477 return ret;
1478 }
1479
1480 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1481 {
1482 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1483 int op_size = (cmd_length(s) - 3) * sizeof(u32);
1484 int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1485 unsigned long gma, gma_low, gma_high;
1486 int ret = 0;
1487
1488 /* check ppggt */
1489 if (!(cmd_val(s, 0) & (1 << 22)))
1490 return 0;
1491
1492 gma = cmd_val(s, 2) & GENMASK(31, 2);
1493
1494 if (gmadr_bytes == 8) {
1495 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1496 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1497 gma = (gma_high << 32) | gma_low;
1498 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1499 }
1500 ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1501 return ret;
1502 }
1503
1504 static inline int unexpected_cmd(struct parser_exec_state *s)
1505 {
1506 struct intel_vgpu *vgpu = s->vgpu;
1507
1508 gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1509
1510 return -EBADRQC;
1511 }
1512
1513 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1514 {
1515 return unexpected_cmd(s);
1516 }
1517
1518 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1519 {
1520 return unexpected_cmd(s);
1521 }
1522
1523 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1524 {
1525 return unexpected_cmd(s);
1526 }
1527
1528 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1529 {
1530 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1531 int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1532 sizeof(u32);
1533 unsigned long gma, gma_high;
1534 int ret = 0;
1535
1536 if (!(cmd_val(s, 0) & (1 << 22)))
1537 return ret;
1538
1539 gma = cmd_val(s, 1) & GENMASK(31, 2);
1540 if (gmadr_bytes == 8) {
1541 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1542 gma = (gma_high << 32) | gma;
1543 }
1544 ret = cmd_address_audit(s, gma, op_size, false);
1545 return ret;
1546 }
1547
1548 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1549 {
1550 return unexpected_cmd(s);
1551 }
1552
1553 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1554 {
1555 return unexpected_cmd(s);
1556 }
1557
1558 static int cmd_handler_mi_conditional_batch_buffer_end(
1559 struct parser_exec_state *s)
1560 {
1561 return unexpected_cmd(s);
1562 }
1563
1564 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1565 {
1566 return unexpected_cmd(s);
1567 }
1568
1569 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1570 {
1571 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1572 unsigned long gma;
1573 bool index_mode = false;
1574 int ret = 0;
1575
1576 /* Check post-sync and ppgtt bit */
1577 if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1578 gma = cmd_val(s, 1) & GENMASK(31, 3);
1579 if (gmadr_bytes == 8)
1580 gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1581 /* Store Data Index */
1582 if (cmd_val(s, 0) & (1 << 21))
1583 index_mode = true;
1584 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1585 }
1586 /* Check notify bit */
1587 if ((cmd_val(s, 0) & (1 << 8)))
1588 set_bit(cmd_interrupt_events[s->ring_id].mi_flush_dw,
1589 s->workload->pending_events);
1590 return ret;
1591 }
1592
1593 static void addr_type_update_snb(struct parser_exec_state *s)
1594 {
1595 if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1596 (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1597 s->buf_addr_type = PPGTT_BUFFER;
1598 }
1599 }
1600
1601
1602 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1603 unsigned long gma, unsigned long end_gma, void *va)
1604 {
1605 unsigned long copy_len, offset;
1606 unsigned long len = 0;
1607 unsigned long gpa;
1608
1609 while (gma != end_gma) {
1610 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1611 if (gpa == INTEL_GVT_INVALID_ADDR) {
1612 gvt_vgpu_err("invalid gma address: %lx\n", gma);
1613 return -EFAULT;
1614 }
1615
1616 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1617
1618 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1619 I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1620
1621 intel_gvt_hypervisor_read_gpa(vgpu, gpa, va + len, copy_len);
1622
1623 len += copy_len;
1624 gma += copy_len;
1625 }
1626 return len;
1627 }
1628
1629
1630 /*
1631 * Check whether a batch buffer needs to be scanned. Currently
1632 * the only criteria is based on privilege.
1633 */
1634 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1635 {
1636 /* Decide privilege based on address space */
1637 if (cmd_val(s, 0) & (1 << 8) &&
1638 !(s->vgpu->scan_nonprivbb & (1 << s->ring_id)))
1639 return 0;
1640 return 1;
1641 }
1642
1643 static int find_bb_size(struct parser_exec_state *s, unsigned long *bb_size)
1644 {
1645 unsigned long gma = 0;
1646 struct cmd_info *info;
1647 uint32_t cmd_len = 0;
1648 bool bb_end = false;
1649 struct intel_vgpu *vgpu = s->vgpu;
1650 u32 cmd;
1651 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1652 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1653
1654 *bb_size = 0;
1655
1656 /* get the start gm address of the batch buffer */
1657 gma = get_gma_bb_from_cmd(s, 1);
1658 if (gma == INTEL_GVT_INVALID_ADDR)
1659 return -EFAULT;
1660
1661 cmd = cmd_val(s, 0);
1662 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1663 if (info == NULL) {
1664 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1665 cmd, get_opcode(cmd, s->ring_id),
1666 (s->buf_addr_type == PPGTT_BUFFER) ?
1667 "ppgtt" : "ggtt", s->ring_id, s->workload);
1668 return -EBADRQC;
1669 }
1670 do {
1671 if (copy_gma_to_hva(s->vgpu, mm,
1672 gma, gma + 4, &cmd) < 0)
1673 return -EFAULT;
1674 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
1675 if (info == NULL) {
1676 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
1677 cmd, get_opcode(cmd, s->ring_id),
1678 (s->buf_addr_type == PPGTT_BUFFER) ?
1679 "ppgtt" : "ggtt", s->ring_id, s->workload);
1680 return -EBADRQC;
1681 }
1682
1683 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1684 bb_end = true;
1685 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1686 if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1687 /* chained batch buffer */
1688 bb_end = true;
1689 }
1690 cmd_len = get_cmd_length(info, cmd) << 2;
1691 *bb_size += cmd_len;
1692 gma += cmd_len;
1693 } while (!bb_end);
1694
1695 return 0;
1696 }
1697
1698 static int perform_bb_shadow(struct parser_exec_state *s)
1699 {
1700 struct intel_vgpu *vgpu = s->vgpu;
1701 struct intel_vgpu_shadow_bb *bb;
1702 unsigned long gma = 0;
1703 unsigned long bb_size;
1704 int ret = 0;
1705 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1706 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1707 unsigned long gma_start_offset = 0;
1708
1709 /* get the start gm address of the batch buffer */
1710 gma = get_gma_bb_from_cmd(s, 1);
1711 if (gma == INTEL_GVT_INVALID_ADDR)
1712 return -EFAULT;
1713
1714 ret = find_bb_size(s, &bb_size);
1715 if (ret)
1716 return ret;
1717
1718 bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1719 if (!bb)
1720 return -ENOMEM;
1721
1722 bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1723
1724 /* the gma_start_offset stores the batch buffer's start gma's
1725 * offset relative to page boundary. so for non-privileged batch
1726 * buffer, the shadowed gem object holds exactly the same page
1727 * layout as original gem object. This is for the convience of
1728 * replacing the whole non-privilged batch buffer page to this
1729 * shadowed one in PPGTT at the same gma address. (this replacing
1730 * action is not implemented yet now, but may be necessary in
1731 * future).
1732 * for prileged batch buffer, we just change start gma address to
1733 * that of shadowed page.
1734 */
1735 if (bb->ppgtt)
1736 gma_start_offset = gma & ~I915_GTT_PAGE_MASK;
1737
1738 bb->obj = i915_gem_object_create(s->vgpu->gvt->dev_priv,
1739 roundup(bb_size + gma_start_offset, PAGE_SIZE));
1740 if (IS_ERR(bb->obj)) {
1741 ret = PTR_ERR(bb->obj);
1742 goto err_free_bb;
1743 }
1744
1745 ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);
1746 if (ret)
1747 goto err_free_obj;
1748
1749 bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1750 if (IS_ERR(bb->va)) {
1751 ret = PTR_ERR(bb->va);
1752 goto err_finish_shmem_access;
1753 }
1754
1755 if (bb->clflush & CLFLUSH_BEFORE) {
1756 drm_clflush_virt_range(bb->va, bb->obj->base.size);
1757 bb->clflush &= ~CLFLUSH_BEFORE;
1758 }
1759
1760 ret = copy_gma_to_hva(s->vgpu, mm,
1761 gma, gma + bb_size,
1762 bb->va + gma_start_offset);
1763 if (ret < 0) {
1764 gvt_vgpu_err("fail to copy guest ring buffer\n");
1765 ret = -EFAULT;
1766 goto err_unmap;
1767 }
1768
1769 INIT_LIST_HEAD(&bb->list);
1770 list_add(&bb->list, &s->workload->shadow_bb);
1771
1772 bb->accessing = true;
1773 bb->bb_start_cmd_va = s->ip_va;
1774
1775 if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1776 bb->bb_offset = s->ip_va - s->rb_va;
1777 else
1778 bb->bb_offset = 0;
1779
1780 /*
1781 * ip_va saves the virtual address of the shadow batch buffer, while
1782 * ip_gma saves the graphics address of the original batch buffer.
1783 * As the shadow batch buffer is just a copy from the originial one,
1784 * it should be right to use shadow batch buffer'va and original batch
1785 * buffer's gma in pair. After all, we don't want to pin the shadow
1786 * buffer here (too early).
1787 */
1788 s->ip_va = bb->va + gma_start_offset;
1789 s->ip_gma = gma;
1790 return 0;
1791 err_unmap:
1792 i915_gem_object_unpin_map(bb->obj);
1793 err_finish_shmem_access:
1794 i915_gem_obj_finish_shmem_access(bb->obj);
1795 err_free_obj:
1796 i915_gem_object_put(bb->obj);
1797 err_free_bb:
1798 kfree(bb);
1799 return ret;
1800 }
1801
1802 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1803 {
1804 bool second_level;
1805 int ret = 0;
1806 struct intel_vgpu *vgpu = s->vgpu;
1807
1808 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1809 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1810 return -EFAULT;
1811 }
1812
1813 second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
1814 if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
1815 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
1816 return -EFAULT;
1817 }
1818
1819 s->saved_buf_addr_type = s->buf_addr_type;
1820 addr_type_update_snb(s);
1821 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
1822 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
1823 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1824 } else if (second_level) {
1825 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
1826 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
1827 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
1828 }
1829
1830 if (batch_buffer_needs_scan(s)) {
1831 ret = perform_bb_shadow(s);
1832 if (ret < 0)
1833 gvt_vgpu_err("invalid shadow batch buffer\n");
1834 } else {
1835 /* emulate a batch buffer end to do return right */
1836 ret = cmd_handler_mi_batch_buffer_end(s);
1837 if (ret < 0)
1838 return ret;
1839 }
1840 return ret;
1841 }
1842
1843 static struct cmd_info cmd_info[] = {
1844 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1845
1846 {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
1847 0, 1, NULL},
1848
1849 {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
1850 0, 1, cmd_handler_mi_user_interrupt},
1851
1852 {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
1853 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
1854
1855 {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
1856
1857 {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1858 NULL},
1859
1860 {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1861 NULL},
1862
1863 {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1864 NULL},
1865
1866 {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1867 NULL},
1868
1869 {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
1870 D_ALL, 0, 1, NULL},
1871
1872 {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
1873 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1874 cmd_handler_mi_batch_buffer_end},
1875
1876 {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
1877 0, 1, NULL},
1878
1879 {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1880 NULL},
1881
1882 {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
1883 D_ALL, 0, 1, NULL},
1884
1885 {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
1886 NULL},
1887
1888 {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
1889 NULL},
1890
1891 {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR | F_POST_HANDLE,
1892 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
1893
1894 {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR, R_ALL, D_ALL,
1895 0, 8, NULL},
1896
1897 {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
1898
1899 {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
1900
1901 {"ME_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL, F_LEN_VAR, R_ALL,
1902 D_BDW_PLUS, 0, 8, NULL},
1903
1904 {"ME_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1905 ADDR_FIX_1(2), 8, cmd_handler_mi_semaphore_wait},
1906
1907 {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
1908 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
1909
1910 {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
1911 0, 8, cmd_handler_mi_store_data_index},
1912
1913 {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
1914 D_ALL, 0, 8, cmd_handler_lri},
1915
1916 {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
1917 cmd_handler_mi_update_gtt},
1918
1919 {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM, F_LEN_VAR, R_ALL,
1920 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_srm},
1921
1922 {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
1923 cmd_handler_mi_flush_dw},
1924
1925 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
1926 10, cmd_handler_mi_clflush},
1927
1928 {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT, F_LEN_VAR, R_ALL,
1929 D_ALL, ADDR_FIX_1(1), 6, cmd_handler_mi_report_perf_count},
1930
1931 {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM, F_LEN_VAR, R_ALL,
1932 D_ALL, ADDR_FIX_1(2), 8, cmd_handler_lrm},
1933
1934 {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG, F_LEN_VAR, R_ALL,
1935 D_ALL, 0, 8, cmd_handler_lrr},
1936
1937 {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM, F_LEN_VAR, R_RCS,
1938 D_ALL, 0, 8, NULL},
1939
1940 {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR, R_RCS, D_ALL,
1941 ADDR_FIX_1(2), 8, NULL},
1942
1943 {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
1944 ADDR_FIX_1(2), 8, NULL},
1945
1946 {"MI_OP_2E", OP_MI_2E, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_2(1, 2),
1947 8, cmd_handler_mi_op_2e},
1948
1949 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
1950 8, cmd_handler_mi_op_2f},
1951
1952 {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
1953 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
1954 cmd_handler_mi_batch_buffer_start},
1955
1956 {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
1957 F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
1958 cmd_handler_mi_conditional_batch_buffer_end},
1959
1960 {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
1961 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
1962
1963 {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1964 ADDR_FIX_2(4, 7), 8, NULL},
1965
1966 {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
1967 0, 8, NULL},
1968
1969 {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
1970 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
1971
1972 {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1973
1974 {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
1975 0, 8, NULL},
1976
1977 {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1978 ADDR_FIX_1(3), 8, NULL},
1979
1980 {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
1981 D_ALL, 0, 8, NULL},
1982
1983 {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
1984 ADDR_FIX_1(4), 8, NULL},
1985
1986 {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1987 ADDR_FIX_2(4, 5), 8, NULL},
1988
1989 {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
1990 ADDR_FIX_1(4), 8, NULL},
1991
1992 {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
1993 ADDR_FIX_2(4, 7), 8, NULL},
1994
1995 {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
1996 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
1997
1998 {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
1999
2000 {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2001 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2002
2003 {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2004 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2005
2006 {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2007 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2008 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2009
2010 {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2011 D_ALL, ADDR_FIX_1(4), 8, NULL},
2012
2013 {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2014 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2015
2016 {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2017 D_ALL, ADDR_FIX_1(4), 8, NULL},
2018
2019 {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2020 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2021
2022 {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2023 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2024
2025 {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2026 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2027 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2028
2029 {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2030 ADDR_FIX_2(4, 5), 8, NULL},
2031
2032 {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2033 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2034
2035 {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2036 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2037 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2038
2039 {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2040 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2041 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2042
2043 {"3DSTATE_BLEND_STATE_POINTERS",
2044 OP_3DSTATE_BLEND_STATE_POINTERS,
2045 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2046
2047 {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2048 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2049 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2050
2051 {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2052 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2053 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2054
2055 {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2056 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2057 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2058
2059 {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2060 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2061 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2062
2063 {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2064 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2065 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2066
2067 {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2068 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2069 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2070
2071 {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2072 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2073 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2074
2075 {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2076 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2077 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2078
2079 {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2080 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2081 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2082
2083 {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2084 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2085 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2086
2087 {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2088 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2089 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2090
2091 {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2092 0, 8, NULL},
2093
2094 {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2095 0, 8, NULL},
2096
2097 {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2098 0, 8, NULL},
2099
2100 {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2101 0, 8, NULL},
2102
2103 {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2104 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2105
2106 {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2107 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2108
2109 {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2110 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2111
2112 {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2113 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2114
2115 {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2116 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2117
2118 {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2119 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2120
2121 {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2122 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2123
2124 {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2125 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2126
2127 {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2128 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2129
2130 {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2131 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2132
2133 {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2134 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2135
2136 {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2137 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2138
2139 {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2140 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2141
2142 {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2143 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2144
2145 {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2146 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2147
2148 {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2149 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2150
2151 {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2152 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2153
2154 {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2155 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2156
2157 {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2158 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2159
2160 {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2161 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2162
2163 {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2164 D_BDW_PLUS, 0, 8, NULL},
2165
2166 {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2167 NULL},
2168
2169 {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2170 D_BDW_PLUS, 0, 8, NULL},
2171
2172 {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2173 D_BDW_PLUS, 0, 8, NULL},
2174
2175 {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2176 8, NULL},
2177
2178 {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2179 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2180
2181 {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2182 8, NULL},
2183
2184 {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2185 NULL},
2186
2187 {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2188 NULL},
2189
2190 {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2191 NULL},
2192
2193 {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2194 D_BDW_PLUS, 0, 8, NULL},
2195
2196 {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2197 R_RCS, D_ALL, 0, 8, NULL},
2198
2199 {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2200 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2201
2202 {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2203 R_RCS, D_ALL, 0, 1, NULL},
2204
2205 {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2206
2207 {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2208 R_RCS, D_ALL, 0, 8, NULL},
2209
2210 {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2211 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2212
2213 {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2214
2215 {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2216
2217 {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2218
2219 {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2220 D_BDW_PLUS, 0, 8, NULL},
2221
2222 {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2223 D_BDW_PLUS, 0, 8, NULL},
2224
2225 {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2226 D_ALL, 0, 8, NULL},
2227
2228 {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2229 D_BDW_PLUS, 0, 8, NULL},
2230
2231 {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2232 D_BDW_PLUS, 0, 8, NULL},
2233
2234 {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2235
2236 {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2237
2238 {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2239
2240 {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2241 D_ALL, 0, 8, NULL},
2242
2243 {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2244
2245 {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2246
2247 {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2248 R_RCS, D_ALL, 0, 8, NULL},
2249
2250 {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2251 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2252
2253 {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2254 0, 8, NULL},
2255
2256 {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2257 D_ALL, ADDR_FIX_1(2), 8, NULL},
2258
2259 {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2260 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2261
2262 {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2263 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2264
2265 {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2266 D_ALL, 0, 8, NULL},
2267
2268 {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2269 D_ALL, 0, 8, NULL},
2270
2271 {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2272 D_ALL, 0, 8, NULL},
2273
2274 {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2275 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2276
2277 {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2278 D_BDW_PLUS, 0, 8, NULL},
2279
2280 {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2281 D_ALL, ADDR_FIX_1(2), 8, NULL},
2282
2283 {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2284 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2285
2286 {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2287 R_RCS, D_ALL, 0, 8, NULL},
2288
2289 {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2290 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2291
2292 {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2293 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2294
2295 {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2296 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2297
2298 {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2299 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2300
2301 {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2302 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2303
2304 {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2305 R_RCS, D_ALL, 0, 8, NULL},
2306
2307 {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2308 D_ALL, 0, 9, NULL},
2309
2310 {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2311 ADDR_FIX_2(2, 4), 8, NULL},
2312
2313 {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2314 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2315 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2316
2317 {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2318 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2319
2320 {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2321 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2322 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2323
2324 {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2325 D_BDW_PLUS, 0, 8, NULL},
2326
2327 {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2328 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2329
2330 {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2331
2332 {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2333 1, NULL},
2334
2335 {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2336 ADDR_FIX_1(1), 8, NULL},
2337
2338 {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2339
2340 {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2341 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2342
2343 {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2344 ADDR_FIX_1(1), 8, NULL},
2345
2346 {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2347
2348 {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2349
2350 {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2351 0, 8, NULL},
2352
2353 {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2354 D_SKL_PLUS, 0, 8, NULL},
2355
2356 {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2357 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2358
2359 {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2360 0, 16, NULL},
2361
2362 {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2363 0, 16, NULL},
2364
2365 {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2366 0, 16, NULL},
2367
2368 {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2369
2370 {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2371 0, 16, NULL},
2372
2373 {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2374 0, 16, NULL},
2375
2376 {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2377 0, 16, NULL},
2378
2379 {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2380 0, 8, NULL},
2381
2382 {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2383 NULL},
2384
2385 {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2386 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2387
2388 {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2389 R_VCS, D_ALL, 0, 12, NULL},
2390
2391 {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2392 R_VCS, D_ALL, 0, 12, NULL},
2393
2394 {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2395 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2396
2397 {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2398 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2399
2400 {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2401 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2402
2403 {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2404
2405 {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2406 R_VCS, D_ALL, 0, 12, NULL},
2407
2408 {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2409 R_VCS, D_ALL, 0, 12, NULL},
2410
2411 {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2412 R_VCS, D_ALL, 0, 12, NULL},
2413
2414 {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2415 R_VCS, D_ALL, 0, 12, NULL},
2416
2417 {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2418 R_VCS, D_ALL, 0, 12, NULL},
2419
2420 {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2421 R_VCS, D_ALL, 0, 12, NULL},
2422
2423 {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2424 R_VCS, D_ALL, 0, 6, NULL},
2425
2426 {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2427 R_VCS, D_ALL, 0, 12, NULL},
2428
2429 {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2430 R_VCS, D_ALL, 0, 12, NULL},
2431
2432 {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2433 R_VCS, D_ALL, 0, 12, NULL},
2434
2435 {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2436 R_VCS, D_ALL, 0, 12, NULL},
2437
2438 {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2439 R_VCS, D_ALL, 0, 12, NULL},
2440
2441 {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2442 R_VCS, D_ALL, 0, 12, NULL},
2443
2444 {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2445 R_VCS, D_ALL, 0, 12, NULL},
2446 {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2447 R_VCS, D_ALL, 0, 12, NULL},
2448
2449 {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2450 R_VCS, D_ALL, 0, 12, NULL},
2451
2452 {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2453 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2454
2455 {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2456 R_VCS, D_ALL, 0, 12, NULL},
2457
2458 {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2459 R_VCS, D_ALL, 0, 12, NULL},
2460
2461 {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2462 R_VCS, D_ALL, 0, 12, NULL},
2463
2464 {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2465 R_VCS, D_ALL, 0, 12, NULL},
2466
2467 {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2468 R_VCS, D_ALL, 0, 12, NULL},
2469
2470 {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2471 R_VCS, D_ALL, 0, 12, NULL},
2472
2473 {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2474 R_VCS, D_ALL, 0, 12, NULL},
2475
2476 {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2477 R_VCS, D_ALL, 0, 12, NULL},
2478
2479 {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2480 R_VCS, D_ALL, 0, 12, NULL},
2481
2482 {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2483 R_VCS, D_ALL, 0, 12, NULL},
2484
2485 {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2486 R_VCS, D_ALL, 0, 12, NULL},
2487
2488 {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2489 0, 16, NULL},
2490
2491 {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2492
2493 {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2494
2495 {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2496 R_VCS, D_ALL, 0, 12, NULL},
2497
2498 {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2499 R_VCS, D_ALL, 0, 12, NULL},
2500
2501 {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2502 R_VCS, D_ALL, 0, 12, NULL},
2503
2504 {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2505
2506 {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2507 0, 12, NULL},
2508
2509 {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2510 0, 20, NULL},
2511 };
2512
2513 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2514 {
2515 hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2516 }
2517
2518 /* call the cmd handler, and advance ip */
2519 static int cmd_parser_exec(struct parser_exec_state *s)
2520 {
2521 struct intel_vgpu *vgpu = s->vgpu;
2522 struct cmd_info *info;
2523 u32 cmd;
2524 int ret = 0;
2525
2526 cmd = cmd_val(s, 0);
2527
2528 info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2529 if (info == NULL) {
2530 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
2531 cmd, get_opcode(cmd, s->ring_id),
2532 (s->buf_addr_type == PPGTT_BUFFER) ?
2533 "ppgtt" : "ggtt", s->ring_id, s->workload);
2534 return -EBADRQC;
2535 }
2536
2537 s->info = info;
2538
2539 trace_gvt_command(vgpu->id, s->ring_id, s->ip_gma, s->ip_va,
2540 cmd_length(s), s->buf_type, s->buf_addr_type,
2541 s->workload, info->name);
2542
2543 if (info->handler) {
2544 ret = info->handler(s);
2545 if (ret < 0) {
2546 gvt_vgpu_err("%s handler error\n", info->name);
2547 return ret;
2548 }
2549 }
2550
2551 if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2552 ret = cmd_advance_default(s);
2553 if (ret) {
2554 gvt_vgpu_err("%s IP advance error\n", info->name);
2555 return ret;
2556 }
2557 }
2558 return 0;
2559 }
2560
2561 static inline bool gma_out_of_range(unsigned long gma,
2562 unsigned long gma_head, unsigned int gma_tail)
2563 {
2564 if (gma_tail >= gma_head)
2565 return (gma < gma_head) || (gma > gma_tail);
2566 else
2567 return (gma > gma_tail) && (gma < gma_head);
2568 }
2569
2570 /* Keep the consistent return type, e.g EBADRQC for unknown
2571 * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2572 * works as the input of VM healthy status.
2573 */
2574 static int command_scan(struct parser_exec_state *s,
2575 unsigned long rb_head, unsigned long rb_tail,
2576 unsigned long rb_start, unsigned long rb_len)
2577 {
2578
2579 unsigned long gma_head, gma_tail, gma_bottom;
2580 int ret = 0;
2581 struct intel_vgpu *vgpu = s->vgpu;
2582
2583 gma_head = rb_start + rb_head;
2584 gma_tail = rb_start + rb_tail;
2585 gma_bottom = rb_start + rb_len;
2586
2587 while (s->ip_gma != gma_tail) {
2588 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2589 if (!(s->ip_gma >= rb_start) ||
2590 !(s->ip_gma < gma_bottom)) {
2591 gvt_vgpu_err("ip_gma %lx out of ring scope."
2592 "(base:0x%lx, bottom: 0x%lx)\n",
2593 s->ip_gma, rb_start,
2594 gma_bottom);
2595 parser_exec_state_dump(s);
2596 return -EFAULT;
2597 }
2598 if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2599 gvt_vgpu_err("ip_gma %lx out of range."
2600 "base 0x%lx head 0x%lx tail 0x%lx\n",
2601 s->ip_gma, rb_start,
2602 rb_head, rb_tail);
2603 parser_exec_state_dump(s);
2604 break;
2605 }
2606 }
2607 ret = cmd_parser_exec(s);
2608 if (ret) {
2609 gvt_vgpu_err("cmd parser error\n");
2610 parser_exec_state_dump(s);
2611 break;
2612 }
2613 }
2614
2615 return ret;
2616 }
2617
2618 static int scan_workload(struct intel_vgpu_workload *workload)
2619 {
2620 unsigned long gma_head, gma_tail, gma_bottom;
2621 struct parser_exec_state s;
2622 int ret = 0;
2623
2624 /* ring base is page aligned */
2625 if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2626 return -EINVAL;
2627
2628 gma_head = workload->rb_start + workload->rb_head;
2629 gma_tail = workload->rb_start + workload->rb_tail;
2630 gma_bottom = workload->rb_start + _RING_CTL_BUF_SIZE(workload->rb_ctl);
2631
2632 s.buf_type = RING_BUFFER_INSTRUCTION;
2633 s.buf_addr_type = GTT_BUFFER;
2634 s.vgpu = workload->vgpu;
2635 s.ring_id = workload->ring_id;
2636 s.ring_start = workload->rb_start;
2637 s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2638 s.ring_head = gma_head;
2639 s.ring_tail = gma_tail;
2640 s.rb_va = workload->shadow_ring_buffer_va;
2641 s.workload = workload;
2642 s.is_ctx_wa = false;
2643
2644 if ((bypass_scan_mask & (1 << workload->ring_id)) ||
2645 gma_head == gma_tail)
2646 return 0;
2647
2648 if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2649 ret = -EINVAL;
2650 goto out;
2651 }
2652
2653 ret = ip_gma_set(&s, gma_head);
2654 if (ret)
2655 goto out;
2656
2657 ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2658 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2659
2660 out:
2661 return ret;
2662 }
2663
2664 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2665 {
2666
2667 unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2668 struct parser_exec_state s;
2669 int ret = 0;
2670 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2671 struct intel_vgpu_workload,
2672 wa_ctx);
2673
2674 /* ring base is page aligned */
2675 if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2676 I915_GTT_PAGE_SIZE)))
2677 return -EINVAL;
2678
2679 ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(uint32_t);
2680 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2681 PAGE_SIZE);
2682 gma_head = wa_ctx->indirect_ctx.guest_gma;
2683 gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2684 gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2685
2686 s.buf_type = RING_BUFFER_INSTRUCTION;
2687 s.buf_addr_type = GTT_BUFFER;
2688 s.vgpu = workload->vgpu;
2689 s.ring_id = workload->ring_id;
2690 s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2691 s.ring_size = ring_size;
2692 s.ring_head = gma_head;
2693 s.ring_tail = gma_tail;
2694 s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2695 s.workload = workload;
2696 s.is_ctx_wa = true;
2697
2698 if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2699 ret = -EINVAL;
2700 goto out;
2701 }
2702
2703 ret = ip_gma_set(&s, gma_head);
2704 if (ret)
2705 goto out;
2706
2707 ret = command_scan(&s, 0, ring_tail,
2708 wa_ctx->indirect_ctx.guest_gma, ring_size);
2709 out:
2710 return ret;
2711 }
2712
2713 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2714 {
2715 struct intel_vgpu *vgpu = workload->vgpu;
2716 struct intel_vgpu_submission *s = &vgpu->submission;
2717 unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2718 void *shadow_ring_buffer_va;
2719 int ring_id = workload->ring_id;
2720 int ret;
2721
2722 guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2723
2724 /* calculate workload ring buffer size */
2725 workload->rb_len = (workload->rb_tail + guest_rb_size -
2726 workload->rb_head) % guest_rb_size;
2727
2728 gma_head = workload->rb_start + workload->rb_head;
2729 gma_tail = workload->rb_start + workload->rb_tail;
2730 gma_top = workload->rb_start + guest_rb_size;
2731
2732 if (workload->rb_len > s->ring_scan_buffer_size[ring_id]) {
2733 void *p;
2734
2735 /* realloc the new ring buffer if needed */
2736 p = krealloc(s->ring_scan_buffer[ring_id], workload->rb_len,
2737 GFP_KERNEL);
2738 if (!p) {
2739 gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2740 return -ENOMEM;
2741 }
2742 s->ring_scan_buffer[ring_id] = p;
2743 s->ring_scan_buffer_size[ring_id] = workload->rb_len;
2744 }
2745
2746 shadow_ring_buffer_va = s->ring_scan_buffer[ring_id];
2747
2748 /* get shadow ring buffer va */
2749 workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2750
2751 /* head > tail --> copy head <-> top */
2752 if (gma_head > gma_tail) {
2753 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2754 gma_head, gma_top, shadow_ring_buffer_va);
2755 if (ret < 0) {
2756 gvt_vgpu_err("fail to copy guest ring buffer\n");
2757 return ret;
2758 }
2759 shadow_ring_buffer_va += ret;
2760 gma_head = workload->rb_start;
2761 }
2762
2763 /* copy head or start <-> tail */
2764 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2765 shadow_ring_buffer_va);
2766 if (ret < 0) {
2767 gvt_vgpu_err("fail to copy guest ring buffer\n");
2768 return ret;
2769 }
2770 return 0;
2771 }
2772
2773 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2774 {
2775 int ret;
2776 struct intel_vgpu *vgpu = workload->vgpu;
2777
2778 ret = shadow_workload_ring_buffer(workload);
2779 if (ret) {
2780 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2781 return ret;
2782 }
2783
2784 ret = scan_workload(workload);
2785 if (ret) {
2786 gvt_vgpu_err("scan workload error\n");
2787 return ret;
2788 }
2789 return 0;
2790 }
2791
2792 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2793 {
2794 int ctx_size = wa_ctx->indirect_ctx.size;
2795 unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2796 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2797 struct intel_vgpu_workload,
2798 wa_ctx);
2799 struct intel_vgpu *vgpu = workload->vgpu;
2800 struct drm_i915_gem_object *obj;
2801 int ret = 0;
2802 void *map;
2803
2804 obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
2805 roundup(ctx_size + CACHELINE_BYTES,
2806 PAGE_SIZE));
2807 if (IS_ERR(obj))
2808 return PTR_ERR(obj);
2809
2810 /* get the va of the shadow batch buffer */
2811 map = i915_gem_object_pin_map(obj, I915_MAP_WB);
2812 if (IS_ERR(map)) {
2813 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
2814 ret = PTR_ERR(map);
2815 goto put_obj;
2816 }
2817
2818 ret = i915_gem_object_set_to_cpu_domain(obj, false);
2819 if (ret) {
2820 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
2821 goto unmap_src;
2822 }
2823
2824 ret = copy_gma_to_hva(workload->vgpu,
2825 workload->vgpu->gtt.ggtt_mm,
2826 guest_gma, guest_gma + ctx_size,
2827 map);
2828 if (ret < 0) {
2829 gvt_vgpu_err("fail to copy guest indirect ctx\n");
2830 goto unmap_src;
2831 }
2832
2833 wa_ctx->indirect_ctx.obj = obj;
2834 wa_ctx->indirect_ctx.shadow_va = map;
2835 return 0;
2836
2837 unmap_src:
2838 i915_gem_object_unpin_map(obj);
2839 put_obj:
2840 i915_gem_object_put(obj);
2841 return ret;
2842 }
2843
2844 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2845 {
2846 uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};
2847 unsigned char *bb_start_sva;
2848
2849 if (!wa_ctx->per_ctx.valid)
2850 return 0;
2851
2852 per_ctx_start[0] = 0x18800001;
2853 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
2854
2855 bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
2856 wa_ctx->indirect_ctx.size;
2857
2858 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
2859
2860 return 0;
2861 }
2862
2863 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2864 {
2865 int ret;
2866 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2867 struct intel_vgpu_workload,
2868 wa_ctx);
2869 struct intel_vgpu *vgpu = workload->vgpu;
2870
2871 if (wa_ctx->indirect_ctx.size == 0)
2872 return 0;
2873
2874 ret = shadow_indirect_ctx(wa_ctx);
2875 if (ret) {
2876 gvt_vgpu_err("fail to shadow indirect ctx\n");
2877 return ret;
2878 }
2879
2880 combine_wa_ctx(wa_ctx);
2881
2882 ret = scan_wa_ctx(wa_ctx);
2883 if (ret) {
2884 gvt_vgpu_err("scan wa ctx error\n");
2885 return ret;
2886 }
2887
2888 return 0;
2889 }
2890
2891 static struct cmd_info *find_cmd_entry_any_ring(struct intel_gvt *gvt,
2892 unsigned int opcode, unsigned long rings)
2893 {
2894 struct cmd_info *info = NULL;
2895 unsigned int ring;
2896
2897 for_each_set_bit(ring, &rings, I915_NUM_ENGINES) {
2898 info = find_cmd_entry(gvt, opcode, ring);
2899 if (info)
2900 break;
2901 }
2902 return info;
2903 }
2904
2905 static int init_cmd_table(struct intel_gvt *gvt)
2906 {
2907 int i;
2908 struct cmd_entry *e;
2909 struct cmd_info *info;
2910 unsigned int gen_type;
2911
2912 gen_type = intel_gvt_get_device_type(gvt);
2913
2914 for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
2915 if (!(cmd_info[i].devices & gen_type))
2916 continue;
2917
2918 e = kzalloc(sizeof(*e), GFP_KERNEL);
2919 if (!e)
2920 return -ENOMEM;
2921
2922 e->info = &cmd_info[i];
2923 info = find_cmd_entry_any_ring(gvt,
2924 e->info->opcode, e->info->rings);
2925 if (info) {
2926 gvt_err("%s %s duplicated\n", e->info->name,
2927 info->name);
2928 kfree(e);
2929 return -EEXIST;
2930 }
2931
2932 INIT_HLIST_NODE(&e->hlist);
2933 add_cmd_entry(gvt, e);
2934 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
2935 e->info->name, e->info->opcode, e->info->flag,
2936 e->info->devices, e->info->rings);
2937 }
2938 return 0;
2939 }
2940
2941 static void clean_cmd_table(struct intel_gvt *gvt)
2942 {
2943 struct hlist_node *tmp;
2944 struct cmd_entry *e;
2945 int i;
2946
2947 hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
2948 kfree(e);
2949
2950 hash_init(gvt->cmd_table);
2951 }
2952
2953 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
2954 {
2955 clean_cmd_table(gvt);
2956 }
2957
2958 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
2959 {
2960 int ret;
2961
2962 ret = init_cmd_table(gvt);
2963 if (ret) {
2964 intel_gvt_clean_cmd_parser(gvt);
2965 return ret;
2966 }
2967 return 0;
2968 }
Linux with added FPC-III support