drivers/gpu/drm/i915/gvt/mmio.h

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *    Dexuan Cui
  27  *
  28  * Contributors:
  29  *    Tina Zhang <tina.zhang@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Niu Bing <bing.niu@intel.com>
  32  *    Zhi Wang <zhi.a.wang@intel.com>
  33  *
  34  */
  35
  36 #ifndef _GVT_MMIO_H_
  37 #define _GVT_MMIO_H_
  38
  39 struct intel_gvt;
  40 struct intel_vgpu;
  41
  42 #define D_BDW   (1 << 0)
  43 #define D_SKL   (1 << 1)
  44 #define D_KBL   (1 << 2)
  45 #define D_BXT   (1 << 3)
  46
  47 #define D_GEN9PLUS      (D_SKL | D_KBL | D_BXT)
  48 #define D_GEN8PLUS      (D_BDW | D_SKL | D_KBL | D_BXT)
  49
  50 #define D_SKL_PLUS      (D_SKL | D_KBL | D_BXT)
  51 #define D_BDW_PLUS      (D_BDW | D_SKL | D_KBL | D_BXT)
  52
  53 #define D_PRE_SKL       (D_BDW)
  54 #define D_ALL           (D_BDW | D_SKL | D_KBL | D_BXT)
  55
  56 typedef int (*gvt_mmio_func)(struct intel_vgpu *, unsigned int, void *,
  57                              unsigned int);
  58
  59 struct intel_gvt_mmio_info {
  60         u32 offset;
  61         u64 ro_mask;
  62         u32 device;
  63         gvt_mmio_func read;
  64         gvt_mmio_func write;
  65         u32 addr_range;
  66         struct hlist_node node;
  67 };
  68
  69 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
  70                 unsigned int reg);
  71 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
  72 bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
  73
  74 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
  75 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
  76 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
  77         int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
  78         void *data);
  79
  80 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
  81 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
  82 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
  83
  84 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
  85
  86 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
  87                                 void *p_data, unsigned int bytes);
  88 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
  89                                 void *p_data, unsigned int bytes);
  90
  91 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
  92                                  void *p_data, unsigned int bytes);
  93 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
  94                                   void *p_data, unsigned int bytes);
  95
  96 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
  97                                           unsigned int offset);
  98
  99 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
 100                            void *pdata, unsigned int bytes, bool is_read);
 101
 102 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 103                                   void *p_data, unsigned int bytes);
 104 #endif