drivers/gpu/drm/i915/vlv_dsi_pll.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Shobhit Kumar <shobhit.kumar@intel.com>
  25  *      Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include "intel_drv.h"
  30 #include "i915_drv.h"
  31 #include "intel_dsi.h"
  32
  33 static const u16 lfsr_converts[] = {
  34         426, 469, 234, 373, 442, 221, 110, 311, 411,            /* 62 - 70 */
  35         461, 486, 243, 377, 188, 350, 175, 343, 427, 213,       /* 71 - 80 */
  36         106, 53, 282, 397, 454, 227, 113, 56, 284, 142,         /* 81 - 90 */
  37         71, 35, 273, 136, 324, 418, 465, 488, 500, 506          /* 91 - 100 */
  38 };
  39
  40 /* Get DSI clock from pixel clock */
  41 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt,
  42                              int lane_count)
  43 {
  44         u32 dsi_clk_khz;
  45         u32 bpp = mipi_dsi_pixel_format_to_bpp(fmt);
  46
  47         /* DSI data rate = pixel clock * bits per pixel / lane count
  48            pixel clock is converted from KHz to Hz */
  49         dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
  50
  51         return dsi_clk_khz;
  52 }
  53
  54 static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
  55                         struct intel_crtc_state *config,
  56                         int target_dsi_clk)
  57 {
  58         unsigned int m_min, m_max, p_min = 2, p_max = 6;
  59         unsigned int m, n, p;
  60         unsigned int calc_m, calc_p;
  61         int delta, ref_clk;
  62
  63         /* target_dsi_clk is expected in kHz */
  64         if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
  65                 DRM_ERROR("DSI CLK Out of Range\n");
  66                 return -ECHRNG;
  67         }
  68
  69         if (IS_CHERRYVIEW(dev_priv)) {
  70                 ref_clk = 100000;
  71                 n = 4;
  72                 m_min = 70;
  73                 m_max = 96;
  74         } else {
  75                 ref_clk = 25000;
  76                 n = 1;
  77                 m_min = 62;
  78                 m_max = 92;
  79         }
  80
  81         calc_p = p_min;
  82         calc_m = m_min;
  83         delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
  84
  85         for (m = m_min; m <= m_max && delta; m++) {
  86                 for (p = p_min; p <= p_max && delta; p++) {
  87                         /*
  88                          * Find the optimal m and p divisors with minimal delta
  89                          * +/- the required clock
  90                          */
  91                         int calc_dsi_clk = (m * ref_clk) / (p * n);
  92                         int d = abs(target_dsi_clk - calc_dsi_clk);
  93                         if (d < delta) {
  94                                 delta = d;
  95                                 calc_m = m;
  96                                 calc_p = p;
  97                         }
  98                 }
  99         }
 100
 101         /* register has log2(N1), this works fine for powers of two */
 102         config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
 103         config->dsi_pll.div =
 104                 (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
 105                 (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
 106
 107         return 0;
 108 }
 109
 110 /*
 111  * XXX: The muxing and gating is hard coded for now. Need to add support for
 112  * sharing PLLs with two DSI outputs.
 113  */
 114 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
 115                         struct intel_crtc_state *config)
 116 {
 117         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 118         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 119         int ret;
 120         u32 dsi_clk;
 121
 122         dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
 123                                     intel_dsi->lane_count);
 124
 125         ret = dsi_calc_mnp(dev_priv, config, dsi_clk);
 126         if (ret) {
 127                 DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
 128                 return ret;
 129         }
 130
 131         if (intel_dsi->ports & (1 << PORT_A))
 132                 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
 133
 134         if (intel_dsi->ports & (1 << PORT_C))
 135                 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
 136
 137         config->dsi_pll.ctrl |= DSI_PLL_VCO_EN;
 138
 139         DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
 140                       config->dsi_pll.div, config->dsi_pll.ctrl);
 141
 142         return 0;
 143 }
 144
 145 void vlv_dsi_pll_enable(struct intel_encoder *encoder,
 146                         const struct intel_crtc_state *config)
 147 {
 148         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 149
 150         DRM_DEBUG_KMS("\n");
 151
 152         mutex_lock(&dev_priv->sb_lock);
 153
 154         vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
 155         vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
 156         vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL,
 157                       config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN);
 158
 159         /* wait at least 0.5 us after ungating before enabling VCO,
 160          * allow hrtimer subsystem optimization by relaxing timing
 161          */
 162         usleep_range(10, 50);
 163
 164         vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl);
 165
 166         if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
 167                                                 DSI_PLL_LOCK, 20)) {
 168
 169                 mutex_unlock(&dev_priv->sb_lock);
 170                 DRM_ERROR("DSI PLL lock failed\n");
 171                 return;
 172         }
 173         mutex_unlock(&dev_priv->sb_lock);
 174
 175         DRM_DEBUG_KMS("DSI PLL locked\n");
 176 }
 177
 178 void vlv_dsi_pll_disable(struct intel_encoder *encoder)
 179 {
 180         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 181         u32 tmp;
 182
 183         DRM_DEBUG_KMS("\n");
 184
 185         mutex_lock(&dev_priv->sb_lock);
 186
 187         tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 188         tmp &= ~DSI_PLL_VCO_EN;
 189         tmp |= DSI_PLL_LDO_GATE;
 190         vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
 191
 192         mutex_unlock(&dev_priv->sb_lock);
 193 }
 194
 195 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
 196 {
 197         bool enabled;
 198         u32 val;
 199         u32 mask;
 200
 201         mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED;
 202         val = I915_READ(BXT_DSI_PLL_ENABLE);
 203         enabled = (val & mask) == mask;
 204
 205         if (!enabled)
 206                 return false;
 207
 208         /*
 209          * Dividers must be programmed with valid values. As per BSEPC, for
 210          * GEMINLAKE only PORT A divider values are checked while for BXT
 211          * both divider values are validated. Check this here for
 212          * paranoia, since BIOS is known to misconfigure PLLs in this way at
 213          * times, and since accessing DSI registers with invalid dividers
 214          * causes a system hang.
 215          */
 216         val = I915_READ(BXT_DSI_PLL_CTL);
 217         if (IS_GEMINILAKE(dev_priv)) {
 218                 if (!(val & BXT_DSIA_16X_MASK)) {
 219                         DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
 220                         enabled = false;
 221                 }
 222         } else {
 223                 if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) {
 224                         DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val);
 225                         enabled = false;
 226                 }
 227         }
 228
 229         return enabled;
 230 }
 231
 232 void bxt_dsi_pll_disable(struct intel_encoder *encoder)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 235         u32 val;
 236
 237         DRM_DEBUG_KMS("\n");
 238
 239         val = I915_READ(BXT_DSI_PLL_ENABLE);
 240         val &= ~BXT_DSI_PLL_DO_ENABLE;
 241         I915_WRITE(BXT_DSI_PLL_ENABLE, val);
 242
 243         /*
 244          * PLL lock should deassert within 200us.
 245          * Wait up to 1ms before timing out.
 246          */
 247         if (intel_wait_for_register(dev_priv,
 248                                     BXT_DSI_PLL_ENABLE,
 249                                     BXT_DSI_PLL_LOCKED,
 250                                     0,
 251                                     1))
 252                 DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
 253 }
 254
 255 static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp)
 256 {
 257         int bpp = mipi_dsi_pixel_format_to_bpp(fmt);
 258
 259         WARN(bpp != pipe_bpp,
 260              "bpp match assertion failure (expected %d, current %d)\n",
 261              bpp, pipe_bpp);
 262 }
 263
 264 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
 265                      struct intel_crtc_state *config)
 266 {
 267         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 268         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 269         u32 dsi_clock, pclk;
 270         u32 pll_ctl, pll_div;
 271         u32 m = 0, p = 0, n;
 272         int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
 273         int i;
 274
 275         DRM_DEBUG_KMS("\n");
 276
 277         mutex_lock(&dev_priv->sb_lock);
 278         pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 279         pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
 280         mutex_unlock(&dev_priv->sb_lock);
 281
 282         config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
 283         config->dsi_pll.div = pll_div;
 284
 285         /* mask out other bits and extract the P1 divisor */
 286         pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;
 287         pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2);
 288
 289         /* N1 divisor */
 290         n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT;
 291         n = 1 << n; /* register has log2(N1) */
 292
 293         /* mask out the other bits and extract the M1 divisor */
 294         pll_div &= DSI_PLL_M1_DIV_MASK;
 295         pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT;
 296
 297         while (pll_ctl) {
 298                 pll_ctl = pll_ctl >> 1;
 299                 p++;
 300         }
 301         p--;
 302
 303         if (!p) {
 304                 DRM_ERROR("wrong P1 divisor\n");
 305                 return 0;
 306         }
 307
 308         for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) {
 309                 if (lfsr_converts[i] == pll_div)
 310                         break;
 311         }
 312
 313         if (i == ARRAY_SIZE(lfsr_converts)) {
 314                 DRM_ERROR("wrong m_seed programmed\n");
 315                 return 0;
 316         }
 317
 318         m = i + 62;
 319
 320         dsi_clock = (m * refclk) / (p * n);
 321
 322         /* pixel_format and pipe_bpp should agree */
 323         assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
 324
 325         pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp);
 326
 327         return pclk;
 328 }
 329
 330 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
 331                      struct intel_crtc_state *config)
 332 {
 333         u32 pclk;
 334         u32 dsi_clk;
 335         u32 dsi_ratio;
 336         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 337         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 338
 339         /* Divide by zero */
 340         if (!pipe_bpp) {
 341                 DRM_ERROR("Invalid BPP(0)\n");
 342                 return 0;
 343         }
 344
 345         config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
 346
 347         dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
 348
 349         dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
 350
 351         /* pixel_format and pipe_bpp should agree */
 352         assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
 353
 354         pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
 355
 356         DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
 357         return pclk;
 358 }
 359
 360 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 361 {
 362         u32 temp;
 363         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 364         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 365
 366         temp = I915_READ(MIPI_CTRL(port));
 367         temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 368         I915_WRITE(MIPI_CTRL(port), temp |
 369                         intel_dsi->escape_clk_div <<
 370                         ESCAPE_CLOCK_DIVIDER_SHIFT);
 371 }
 372
 373 static void glk_dsi_program_esc_clock(struct drm_device *dev,
 374                                    const struct intel_crtc_state *config)
 375 {
 376         struct drm_i915_private *dev_priv = to_i915(dev);
 377         u32 dsi_rate = 0;
 378         u32 pll_ratio = 0;
 379         u32 ddr_clk = 0;
 380         u32 div1_value = 0;
 381         u32 div2_value = 0;
 382         u32 txesc1_div = 0;
 383         u32 txesc2_div = 0;
 384
 385         pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
 386
 387         dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
 388
 389         ddr_clk = dsi_rate / 2;
 390
 391         /* Variable divider value */
 392         div1_value = DIV_ROUND_CLOSEST(ddr_clk, 20000);
 393
 394         /* Calculate TXESC1 divider */
 395         if (div1_value <= 10)
 396                 txesc1_div = div1_value;
 397         else if ((div1_value > 10) && (div1_value <= 20))
 398                 txesc1_div = DIV_ROUND_UP(div1_value, 2);
 399         else if ((div1_value > 20) && (div1_value <= 30))
 400                 txesc1_div = DIV_ROUND_UP(div1_value, 4);
 401         else if ((div1_value > 30) && (div1_value <= 40))
 402                 txesc1_div = DIV_ROUND_UP(div1_value, 6);
 403         else if ((div1_value > 40) && (div1_value <= 50))
 404                 txesc1_div = DIV_ROUND_UP(div1_value, 8);
 405         else
 406                 txesc1_div = 10;
 407
 408         /* Calculate TXESC2 divider */
 409         div2_value = DIV_ROUND_UP(div1_value, txesc1_div);
 410
 411         if (div2_value < 10)
 412                 txesc2_div = div2_value;
 413         else
 414                 txesc2_div = 10;
 415
 416         I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK);
 417         I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK);
 418 }
 419
 420 /* Program BXT Mipi clocks and dividers */
 421 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
 422                                    const struct intel_crtc_state *config)
 423 {
 424         struct drm_i915_private *dev_priv = to_i915(dev);
 425         u32 tmp;
 426         u32 dsi_rate = 0;
 427         u32 pll_ratio = 0;
 428         u32 rx_div;
 429         u32 tx_div;
 430         u32 rx_div_upper;
 431         u32 rx_div_lower;
 432         u32 mipi_8by3_divider;
 433
 434         /* Clear old configurations */
 435         tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
 436         tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
 437         tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
 438         tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
 439         tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
 440
 441         /* Get the current DSI rate(actual) */
 442         pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK;
 443         dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
 444
 445         /*
 446          * tx clock should be <= 20MHz and the div value must be
 447          * subtracted by 1 as per bspec
 448          */
 449         tx_div = DIV_ROUND_UP(dsi_rate, 20000) - 1;
 450         /*
 451          * rx clock should be <= 150MHz and the div value must be
 452          * subtracted by 1 as per bspec
 453          */
 454         rx_div = DIV_ROUND_UP(dsi_rate, 150000) - 1;
 455
 456         /*
 457          * rx divider value needs to be updated in the
 458          * two differnt bit fields in the register hence splitting the
 459          * rx divider value accordingly
 460          */
 461         rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
 462         rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
 463
 464         mipi_8by3_divider = 0x2;
 465
 466         tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
 467         tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);
 468         tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower);
 469         tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper);
 470
 471         I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
 472 }
 473
 474 int bxt_dsi_pll_compute(struct intel_encoder *encoder,
 475                         struct intel_crtc_state *config)
 476 {
 477         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 478         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 479         u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;
 480         u32 dsi_clk;
 481
 482         dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
 483                                     intel_dsi->lane_count);
 484
 485         /*
 486          * From clock diagram, to get PLL ratio divider, divide double of DSI
 487          * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
 488          * round 'up' the result
 489          */
 490         dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
 491
 492         if (IS_BROXTON(dev_priv)) {
 493                 dsi_ratio_min = BXT_DSI_PLL_RATIO_MIN;
 494                 dsi_ratio_max = BXT_DSI_PLL_RATIO_MAX;
 495         } else {
 496                 dsi_ratio_min = GLK_DSI_PLL_RATIO_MIN;
 497                 dsi_ratio_max = GLK_DSI_PLL_RATIO_MAX;
 498         }
 499
 500         if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) {
 501                 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
 502                 return -ECHRNG;
 503         } else
 504                 DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
 505
 506         /*
 507          * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
 508          * Spec says both have to be programmed, even if one is not getting
 509          * used. Configure MIPI_CLOCK_CTL dividers in modeset
 510          */
 511         config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2;
 512
 513         /* As per recommendation from hardware team,
 514          * Prog PVD ratio =1 if dsi ratio <= 50
 515          */
 516         if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
 517                 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
 518
 519         return 0;
 520 }
 521
 522 void bxt_dsi_pll_enable(struct intel_encoder *encoder,
 523                         const struct intel_crtc_state *config)
 524 {
 525         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 526         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 527         enum port port;
 528         u32 val;
 529
 530         DRM_DEBUG_KMS("\n");
 531
 532         /* Configure PLL vales */
 533         I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl);
 534         POSTING_READ(BXT_DSI_PLL_CTL);
 535
 536         /* Program TX, RX, Dphy clocks */
 537         if (IS_BROXTON(dev_priv)) {
 538                 for_each_dsi_port(port, intel_dsi->ports)
 539                         bxt_dsi_program_clocks(encoder->base.dev, port, config);
 540         } else {
 541                 glk_dsi_program_esc_clock(encoder->base.dev, config);
 542         }
 543
 544         /* Enable DSI PLL */
 545         val = I915_READ(BXT_DSI_PLL_ENABLE);
 546         val |= BXT_DSI_PLL_DO_ENABLE;
 547         I915_WRITE(BXT_DSI_PLL_ENABLE, val);
 548
 549         /* Timeout and fail if PLL not locked */
 550         if (intel_wait_for_register(dev_priv,
 551                                     BXT_DSI_PLL_ENABLE,
 552                                     BXT_DSI_PLL_LOCKED,
 553                                     BXT_DSI_PLL_LOCKED,
 554                                     1)) {
 555                 DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
 556                 return;
 557         }
 558
 559         DRM_DEBUG_KMS("DSI PLL locked\n");
 560 }
 561
 562 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 563 {
 564         u32 tmp;
 565         struct drm_device *dev = encoder->base.dev;
 566         struct drm_i915_private *dev_priv = to_i915(dev);
 567
 568         /* Clear old configurations */
 569         if (IS_BROXTON(dev_priv)) {
 570                 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
 571                 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
 572                 tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port));
 573                 tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port));
 574                 tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port));
 575                 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
 576         } else {
 577                 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
 578                 tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK;
 579                 I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp);
 580
 581                 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2);
 582                 tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK;
 583                 I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp);
 584         }
 585         I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 586 }