drivers/gpu/drm/msm/adreno/adreno_device.c

   1 /*
   2  * Copyright (C) 2013-2014 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "adreno_gpu.h"
  21
  22 #define ANY_ID 0xff
  23
  24 bool hang_debug = false;
  25 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  26 module_param_named(hang_debug, hang_debug, bool, 0600);
  27
  28 static const struct adreno_info gpulist[] = {
  29         {
  30                 .rev   = ADRENO_REV(3, 0, 5, ANY_ID),
  31                 .revn  = 305,
  32                 .name  = "A305",
  33                 .fw = {
  34                         [ADRENO_FW_PM4] = "a300_pm4.fw",
  35                         [ADRENO_FW_PFP] = "a300_pfp.fw",
  36                 },
  37                 .gmem  = SZ_256K,
  38                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  39                 .init  = a3xx_gpu_init,
  40         }, {
  41                 .rev   = ADRENO_REV(3, 0, 6, 0),
  42                 .revn  = 307,        /* because a305c is revn==306 */
  43                 .name  = "A306",
  44                 .fw = {
  45                         [ADRENO_FW_PM4] = "a300_pm4.fw",
  46                         [ADRENO_FW_PFP] = "a300_pfp.fw",
  47                 },
  48                 .gmem  = SZ_128K,
  49                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  50                 .init  = a3xx_gpu_init,
  51         }, {
  52                 .rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  53                 .revn  = 320,
  54                 .name  = "A320",
  55                 .fw = {
  56                         [ADRENO_FW_PM4] = "a300_pm4.fw",
  57                         [ADRENO_FW_PFP] = "a300_pfp.fw",
  58                 },
  59                 .gmem  = SZ_512K,
  60                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  61                 .init  = a3xx_gpu_init,
  62         }, {
  63                 .rev   = ADRENO_REV(3, 3, 0, ANY_ID),
  64                 .revn  = 330,
  65                 .name  = "A330",
  66                 .fw = {
  67                         [ADRENO_FW_PM4] = "a330_pm4.fw",
  68                         [ADRENO_FW_PFP] = "a330_pfp.fw",
  69                 },
  70                 .gmem  = SZ_1M,
  71                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  72                 .init  = a3xx_gpu_init,
  73         }, {
  74                 .rev   = ADRENO_REV(4, 2, 0, ANY_ID),
  75                 .revn  = 420,
  76                 .name  = "A420",
  77                 .fw = {
  78                         [ADRENO_FW_PM4] = "a420_pm4.fw",
  79                         [ADRENO_FW_PFP] = "a420_pfp.fw",
  80                 },
  81                 .gmem  = (SZ_1M + SZ_512K),
  82                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  83                 .init  = a4xx_gpu_init,
  84         }, {
  85                 .rev   = ADRENO_REV(4, 3, 0, ANY_ID),
  86                 .revn  = 430,
  87                 .name  = "A430",
  88                 .fw = {
  89                         [ADRENO_FW_PM4] = "a420_pm4.fw",
  90                         [ADRENO_FW_PFP] = "a420_pfp.fw",
  91                 },
  92                 .gmem  = (SZ_1M + SZ_512K),
  93                 .inactive_period = DRM_MSM_INACTIVE_PERIOD,
  94                 .init  = a4xx_gpu_init,
  95         }, {
  96                 .rev = ADRENO_REV(5, 3, 0, 2),
  97                 .revn = 530,
  98                 .name = "A530",
  99                 .fw = {
 100                         [ADRENO_FW_PM4] = "a530_pm4.fw",
 101                         [ADRENO_FW_PFP] = "a530_pfp.fw",
 102                         [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
 103                 },
 104                 .gmem = SZ_1M,
 105                 /*
 106                  * Increase inactive period to 250 to avoid bouncing
 107                  * the GDSC which appears to make it grumpy
 108                  */
 109                 .inactive_period = 250,
 110                 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
 111                         ADRENO_QUIRK_FAULT_DETECT_MASK,
 112                 .init = a5xx_gpu_init,
 113                 .zapfw = "a530_zap.mdt",
 114         }, {
 115                 .rev = ADRENO_REV(6, 3, 0, ANY_ID),
 116                 .revn = 630,
 117                 .name = "A630",
 118                 .fw = {
 119                         [ADRENO_FW_SQE] = "a630_sqe.fw",
 120                         [ADRENO_FW_GMU] = "a630_gmu.bin",
 121                 },
 122                 .gmem = SZ_1M,
 123                 .init = a6xx_gpu_init,
 124         },
 125 };
 126
 127 MODULE_FIRMWARE("qcom/a300_pm4.fw");
 128 MODULE_FIRMWARE("qcom/a300_pfp.fw");
 129 MODULE_FIRMWARE("qcom/a330_pm4.fw");
 130 MODULE_FIRMWARE("qcom/a330_pfp.fw");
 131 MODULE_FIRMWARE("qcom/a420_pm4.fw");
 132 MODULE_FIRMWARE("qcom/a420_pfp.fw");
 133 MODULE_FIRMWARE("qcom/a530_pm4.fw");
 134 MODULE_FIRMWARE("qcom/a530_pfp.fw");
 135 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
 136 MODULE_FIRMWARE("qcom/a530_zap.mdt");
 137 MODULE_FIRMWARE("qcom/a530_zap.b00");
 138 MODULE_FIRMWARE("qcom/a530_zap.b01");
 139 MODULE_FIRMWARE("qcom/a530_zap.b02");
 140 MODULE_FIRMWARE("qcom/a630_sqe.fw");
 141 MODULE_FIRMWARE("qcom/a630_gmu.bin");
 142
 143 static inline bool _rev_match(uint8_t entry, uint8_t id)
 144 {
 145         return (entry == ANY_ID) || (entry == id);
 146 }
 147
 148 const struct adreno_info *adreno_info(struct adreno_rev rev)
 149 {
 150         int i;
 151
 152         /* identify gpu: */
 153         for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
 154                 const struct adreno_info *info = &gpulist[i];
 155                 if (_rev_match(info->rev.core, rev.core) &&
 156                                 _rev_match(info->rev.major, rev.major) &&
 157                                 _rev_match(info->rev.minor, rev.minor) &&
 158                                 _rev_match(info->rev.patchid, rev.patchid))
 159                         return info;
 160         }
 161
 162         return NULL;
 163 }
 164
 165 struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
 166 {
 167         struct msm_drm_private *priv = dev->dev_private;
 168         struct platform_device *pdev = priv->gpu_pdev;
 169         struct msm_gpu *gpu = NULL;
 170         struct adreno_gpu *adreno_gpu;
 171         int ret;
 172
 173         if (pdev)
 174                 gpu = platform_get_drvdata(pdev);
 175
 176         if (!gpu) {
 177                 dev_err_once(dev->dev, "no GPU device was found\n");
 178                 return NULL;
 179         }
 180
 181         adreno_gpu = to_adreno_gpu(gpu);
 182
 183         /*
 184          * The number one reason for HW init to fail is if the firmware isn't
 185          * loaded yet. Try that first and don't bother continuing on
 186          * otherwise
 187          */
 188
 189         ret = adreno_load_fw(adreno_gpu);
 190         if (ret)
 191                 return NULL;
 192
 193         /* Make sure pm runtime is active and reset any previous errors */
 194         pm_runtime_set_active(&pdev->dev);
 195
 196         ret = pm_runtime_get_sync(&pdev->dev);
 197         if (ret < 0) {
 198                 dev_err(dev->dev, "Couldn't power up the GPU: %d\n", ret);
 199                 return NULL;
 200         }
 201
 202         mutex_lock(&dev->struct_mutex);
 203         ret = msm_gpu_hw_init(gpu);
 204         mutex_unlock(&dev->struct_mutex);
 205         pm_runtime_put_autosuspend(&pdev->dev);
 206         if (ret) {
 207                 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
 208                 return NULL;
 209         }
 210
 211 #ifdef CONFIG_DEBUG_FS
 212         if (gpu->funcs->debugfs_init) {
 213                 gpu->funcs->debugfs_init(gpu, dev->primary);
 214                 gpu->funcs->debugfs_init(gpu, dev->render);
 215         }
 216 #endif
 217
 218         return gpu;
 219 }
 220
 221 static void set_gpu_pdev(struct drm_device *dev,
 222                 struct platform_device *pdev)
 223 {
 224         struct msm_drm_private *priv = dev->dev_private;
 225         priv->gpu_pdev = pdev;
 226 }
 227
 228 static int find_chipid(struct device *dev, struct adreno_rev *rev)
 229 {
 230         struct device_node *node = dev->of_node;
 231         const char *compat;
 232         int ret;
 233         u32 chipid;
 234
 235         /* first search the compat strings for qcom,adreno-XYZ.W: */
 236         ret = of_property_read_string_index(node, "compatible", 0, &compat);
 237         if (ret == 0) {
 238                 unsigned int r, patch;
 239
 240                 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) {
 241                         rev->core = r / 100;
 242                         r %= 100;
 243                         rev->major = r / 10;
 244                         r %= 10;
 245                         rev->minor = r;
 246                         rev->patchid = patch;
 247
 248                         return 0;
 249                 }
 250         }
 251
 252         /* and if that fails, fall back to legacy "qcom,chipid" property: */
 253         ret = of_property_read_u32(node, "qcom,chipid", &chipid);
 254         if (ret) {
 255                 dev_err(dev, "could not parse qcom,chipid: %d\n", ret);
 256                 return ret;
 257         }
 258
 259         rev->core = (chipid >> 24) & 0xff;
 260         rev->major = (chipid >> 16) & 0xff;
 261         rev->minor = (chipid >> 8) & 0xff;
 262         rev->patchid = (chipid & 0xff);
 263
 264         dev_warn(dev, "Using legacy qcom,chipid binding!\n");
 265         dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
 266                 rev->core, rev->major, rev->minor, rev->patchid);
 267
 268         return 0;
 269 }
 270
 271 static int adreno_bind(struct device *dev, struct device *master, void *data)
 272 {
 273         static struct adreno_platform_config config = {};
 274         const struct adreno_info *info;
 275         struct drm_device *drm = dev_get_drvdata(master);
 276         struct msm_gpu *gpu;
 277         int ret;
 278
 279         ret = find_chipid(dev, &config.rev);
 280         if (ret)
 281                 return ret;
 282
 283         dev->platform_data = &config;
 284         set_gpu_pdev(drm, to_platform_device(dev));
 285
 286         info = adreno_info(config.rev);
 287
 288         if (!info) {
 289                 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
 290                         config.rev.core, config.rev.major,
 291                         config.rev.minor, config.rev.patchid);
 292                 return -ENXIO;
 293         }
 294
 295         DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
 296                 config.rev.minor, config.rev.patchid);
 297
 298         gpu = info->init(drm);
 299         if (IS_ERR(gpu)) {
 300                 dev_warn(drm->dev, "failed to load adreno gpu\n");
 301                 return PTR_ERR(gpu);
 302         }
 303
 304         dev_set_drvdata(dev, gpu);
 305
 306         return 0;
 307 }
 308
 309 static void adreno_unbind(struct device *dev, struct device *master,
 310                 void *data)
 311 {
 312         struct msm_gpu *gpu = dev_get_drvdata(dev);
 313
 314         gpu->funcs->pm_suspend(gpu);
 315         gpu->funcs->destroy(gpu);
 316
 317         set_gpu_pdev(dev_get_drvdata(master), NULL);
 318 }
 319
 320 static const struct component_ops a3xx_ops = {
 321                 .bind   = adreno_bind,
 322                 .unbind = adreno_unbind,
 323 };
 324
 325 static int adreno_probe(struct platform_device *pdev)
 326 {
 327         return component_add(&pdev->dev, &a3xx_ops);
 328 }
 329
 330 static int adreno_remove(struct platform_device *pdev)
 331 {
 332         component_del(&pdev->dev, &a3xx_ops);
 333         return 0;
 334 }
 335
 336 static const struct of_device_id dt_match[] = {
 337         { .compatible = "qcom,adreno" },
 338         { .compatible = "qcom,adreno-3xx" },
 339         /* for backwards compat w/ downstream kgsl DT files: */
 340         { .compatible = "qcom,kgsl-3d0" },
 341         {}
 342 };
 343
 344 #ifdef CONFIG_PM
 345 static int adreno_resume(struct device *dev)
 346 {
 347         struct platform_device *pdev = to_platform_device(dev);
 348         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 349
 350         return gpu->funcs->pm_resume(gpu);
 351 }
 352
 353 static int adreno_suspend(struct device *dev)
 354 {
 355         struct platform_device *pdev = to_platform_device(dev);
 356         struct msm_gpu *gpu = platform_get_drvdata(pdev);
 357
 358         return gpu->funcs->pm_suspend(gpu);
 359 }
 360 #endif
 361
 362 static const struct dev_pm_ops adreno_pm_ops = {
 363         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
 364         SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
 365 };
 366
 367 static struct platform_driver adreno_driver = {
 368         .probe = adreno_probe,
 369         .remove = adreno_remove,
 370         .driver = {
 371                 .name = "adreno",
 372                 .of_match_table = dt_match,
 373                 .pm = &adreno_pm_ops,
 374         },
 375 };
 376
 377 void __init adreno_register(void)
 378 {
 379         platform_driver_register(&adreno_driver);
 380 }
 381
 382 void __exit adreno_unregister(void)
 383 {
 384         platform_driver_unregister(&adreno_driver);
 385 }