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[linux/fpc-iii.git] / drivers / gpu / drm / msm / adreno / adreno_gpu.h
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1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #ifndef __ADRENO_GPU_H__
21 #define __ADRENO_GPU_H__
23 #include <linux/firmware.h>
25 #include "msm_gpu.h"
27 #include "adreno_common.xml.h"
28 #include "adreno_pm4.xml.h"
30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
31 #define REG_SKIP ~0
32 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
34 /**
35 * adreno_regs: List of registers that are used in across all
36 * 3D devices. Each device type has different offset value for the same
37 * register, so an array of register offsets are declared for every device
38 * and are indexed by the enumeration values defined in this enum
40 enum adreno_regs {
41 REG_ADRENO_CP_RB_BASE,
42 REG_ADRENO_CP_RB_BASE_HI,
43 REG_ADRENO_CP_RB_RPTR_ADDR,
44 REG_ADRENO_CP_RB_RPTR_ADDR_HI,
45 REG_ADRENO_CP_RB_RPTR,
46 REG_ADRENO_CP_RB_WPTR,
47 REG_ADRENO_CP_RB_CNTL,
48 REG_ADRENO_REGISTER_MAX,
51 enum {
52 ADRENO_FW_PM4 = 0,
53 ADRENO_FW_SQE = 0, /* a6xx */
54 ADRENO_FW_PFP = 1,
55 ADRENO_FW_GMU = 1, /* a6xx */
56 ADRENO_FW_GPMU = 2,
57 ADRENO_FW_MAX,
60 enum adreno_quirks {
61 ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
62 ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
65 struct adreno_rev {
66 uint8_t core;
67 uint8_t major;
68 uint8_t minor;
69 uint8_t patchid;
72 #define ADRENO_REV(core, major, minor, patchid) \
73 ((struct adreno_rev){ core, major, minor, patchid })
75 struct adreno_gpu_funcs {
76 struct msm_gpu_funcs base;
77 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
80 struct adreno_info {
81 struct adreno_rev rev;
82 uint32_t revn;
83 const char *name;
84 const char *fw[ADRENO_FW_MAX];
85 uint32_t gmem;
86 enum adreno_quirks quirks;
87 struct msm_gpu *(*init)(struct drm_device *dev);
88 const char *zapfw;
89 u32 inactive_period;
92 const struct adreno_info *adreno_info(struct adreno_rev rev);
94 struct adreno_gpu {
95 struct msm_gpu base;
96 struct adreno_rev rev;
97 const struct adreno_info *info;
98 uint32_t gmem; /* actual gmem size */
99 uint32_t revn; /* numeric revision name */
100 const struct adreno_gpu_funcs *funcs;
102 /* interesting register offsets to dump: */
103 const unsigned int *registers;
106 * Are we loading fw from legacy path? Prior to addition
107 * of gpu firmware to linux-firmware, the fw files were
108 * placed in toplevel firmware directory, following qcom's
109 * android kernel. But linux-firmware preferred they be
110 * placed in a 'qcom' subdirectory.
112 * For backwards compatibility, we try first to load from
113 * the new path, using request_firmware_direct() to avoid
114 * any potential timeout waiting for usermode helper, then
115 * fall back to the old path (with direct load). And
116 * finally fall back to request_firmware() with the new
117 * path to allow the usermode helper.
119 enum {
120 FW_LOCATION_UNKNOWN = 0,
121 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
122 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
123 FW_LOCATION_HELPER,
124 } fwloc;
126 /* firmware: */
127 const struct firmware *fw[ADRENO_FW_MAX];
130 * Register offsets are different between some GPUs.
131 * GPU specific offsets will be exported by GPU specific
132 * code (a3xx_gpu.c) and stored in this common location.
134 const unsigned int *reg_offsets;
136 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
138 /* platform config data (ie. from DT, or pdata) */
139 struct adreno_platform_config {
140 struct adreno_rev rev;
143 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
145 #define spin_until(X) ({ \
146 int __ret = -ETIMEDOUT; \
147 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
148 do { \
149 if (X) { \
150 __ret = 0; \
151 break; \
153 } while (time_before(jiffies, __t)); \
154 __ret; \
158 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
160 return (gpu->revn >= 300) && (gpu->revn < 400);
163 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
165 return gpu->revn == 305;
168 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
170 /* yes, 307, because a305c is 306 */
171 return gpu->revn == 307;
174 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
176 return gpu->revn == 320;
179 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
181 return gpu->revn == 330;
184 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
186 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
189 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
191 return (gpu->revn >= 400) && (gpu->revn < 500);
194 static inline int adreno_is_a420(struct adreno_gpu *gpu)
196 return gpu->revn == 420;
199 static inline int adreno_is_a430(struct adreno_gpu *gpu)
201 return gpu->revn == 430;
204 static inline int adreno_is_a530(struct adreno_gpu *gpu)
206 return gpu->revn == 530;
209 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
210 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
211 const char *fwname);
212 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
213 const struct firmware *fw, u64 *iova);
214 int adreno_hw_init(struct msm_gpu *gpu);
215 void adreno_recover(struct msm_gpu *gpu);
216 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
217 struct msm_file_private *ctx);
218 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
219 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
220 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
221 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
222 struct drm_printer *p);
223 #endif
224 void adreno_dump_info(struct msm_gpu *gpu);
225 void adreno_dump(struct msm_gpu *gpu);
226 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
227 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
229 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
230 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
231 int nr_rings);
232 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
233 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
235 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
237 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
238 int adreno_gpu_state_put(struct msm_gpu_state *state);
240 /* ringbuffer helpers (the parts that are adreno specific) */
242 static inline void
243 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
245 adreno_wait_ring(ring, cnt+1);
246 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
249 /* no-op packet: */
250 static inline void
251 OUT_PKT2(struct msm_ringbuffer *ring)
253 adreno_wait_ring(ring, 1);
254 OUT_RING(ring, CP_TYPE2_PKT);
257 static inline void
258 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
260 adreno_wait_ring(ring, cnt+1);
261 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
264 static inline u32 PM4_PARITY(u32 val)
266 return (0x9669 >> (0xF & (val ^
267 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
268 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
269 (val >> 28)))) & 1;
272 /* Maximum number of values that can be executed for one opcode */
273 #define TYPE4_MAX_PAYLOAD 127
275 #define PKT4(_reg, _cnt) \
276 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
277 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
279 static inline void
280 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
282 adreno_wait_ring(ring, cnt + 1);
283 OUT_RING(ring, PKT4(regindx, cnt));
286 static inline void
287 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
289 adreno_wait_ring(ring, cnt + 1);
290 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
291 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
295 * adreno_reg_check() - Checks the validity of a register enum
296 * @gpu: Pointer to struct adreno_gpu
297 * @offset_name: The register enum that is checked
299 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
300 enum adreno_regs offset_name)
302 if (offset_name >= REG_ADRENO_REGISTER_MAX ||
303 !gpu->reg_offsets[offset_name]) {
304 BUG();
308 * REG_SKIP is a special value that tell us that the register in
309 * question isn't implemented on target but don't trigger a BUG(). This
310 * is used to cleanly implement adreno_gpu_write64() and
311 * adreno_gpu_read64() in a generic fashion
313 if (gpu->reg_offsets[offset_name] == REG_SKIP)
314 return false;
316 return true;
319 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
320 enum adreno_regs offset_name)
322 u32 reg = gpu->reg_offsets[offset_name];
323 u32 val = 0;
324 if(adreno_reg_check(gpu,offset_name))
325 val = gpu_read(&gpu->base, reg - 1);
326 return val;
329 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
330 enum adreno_regs offset_name, u32 data)
332 u32 reg = gpu->reg_offsets[offset_name];
333 if(adreno_reg_check(gpu, offset_name))
334 gpu_write(&gpu->base, reg - 1, data);
337 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
338 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
339 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
340 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
342 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
343 enum adreno_regs lo, enum adreno_regs hi, u64 data)
345 adreno_gpu_write(gpu, lo, lower_32_bits(data));
346 adreno_gpu_write(gpu, hi, upper_32_bits(data));
349 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
351 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
355 * Given a register and a count, return a value to program into
356 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
357 * registers starting at _reg.
359 * The register base needs to be a multiple of the length. If it is not, the
360 * hardware will quietly mask off the bits for you and shift the size. For
361 * example, if you intend the protection to start at 0x07 for a length of 4
362 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
363 * expose registers you intended to protect!
365 #define ADRENO_PROTECT_RW(_reg, _len) \
366 ((1 << 30) | (1 << 29) | \
367 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
370 * Same as above, but allow reads over the range. For areas of mixed use (such
371 * as performance counters) this allows us to protect a much larger range with a
372 * single register
374 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
375 ((1 << 29) \
376 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
378 #endif /* __ADRENO_GPU_H__ */