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Linux 4.19.133
[linux/fpc-iii.git] / drivers / gpu / drm / msm / msm_drv.c
blob6f81de85fb860d0db6b0c3d33250242a66bd573d
1 /*
2 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/kthread.h>
20 #include <uapi/linux/sched/types.h>
21 #include <drm/drm_of.h>
22
23 #include "msm_drv.h"
24 #include "msm_debugfs.h"
25 #include "msm_fence.h"
26 #include "msm_gpu.h"
27 #include "msm_kms.h"
28
29
30 /*
31 * MSM driver version:
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
37 * MSM_GEM_INFO ioctl.
38 */
39 #define MSM_VERSION_MAJOR 1
40 #define MSM_VERSION_MINOR 3
41 #define MSM_VERSION_PATCHLEVEL 0
42
43 static const struct drm_mode_config_funcs mode_config_funcs = {
44 .fb_create = msm_framebuffer_create,
45 .output_poll_changed = drm_fb_helper_output_poll_changed,
46 .atomic_check = drm_atomic_helper_check,
47 .atomic_commit = drm_atomic_helper_commit,
48 };
49
50 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
51 .atomic_commit_tail = msm_atomic_commit_tail,
52 };
53
54 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
55 static bool reglog = false;
56 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
57 module_param(reglog, bool, 0600);
58 #else
59 #define reglog 0
60 #endif
61
62 #ifdef CONFIG_DRM_FBDEV_EMULATION
63 static bool fbdev = true;
64 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
65 module_param(fbdev, bool, 0600);
66 #endif
67
68 static char *vram = "16m";
69 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
70 module_param(vram, charp, 0);
71
72 bool dumpstate = false;
73 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
74 module_param(dumpstate, bool, 0600);
75
76 static bool modeset = true;
77 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
78 module_param(modeset, bool, 0600);
79
80 /*
81 * Util/helpers:
82 */
83
84 int msm_clk_bulk_get(struct device *dev, struct clk_bulk_data **bulk)
85 {
86 struct property *prop;
87 const char *name;
88 struct clk_bulk_data *local;
89 int i = 0, ret, count;
90
91 count = of_property_count_strings(dev->of_node, "clock-names");
92 if (count < 1)
93 return 0;
94
95 local = devm_kcalloc(dev, sizeof(struct clk_bulk_data *),
96 count, GFP_KERNEL);
97 if (!local)
98 return -ENOMEM;
99
100 of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
101 local[i].id = devm_kstrdup(dev, name, GFP_KERNEL);
102 if (!local[i].id) {
103 devm_kfree(dev, local);
104 return -ENOMEM;
105 }
106
107 i++;
108 }
109
110 ret = devm_clk_bulk_get(dev, count, local);
111
112 if (ret) {
113 for (i = 0; i < count; i++)
114 devm_kfree(dev, (void *) local[i].id);
115 devm_kfree(dev, local);
116
117 return ret;
118 }
119
120 *bulk = local;
121 return count;
122 }
123
124 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
125 const char *name)
126 {
127 int i;
128 char n[32];
129
130 snprintf(n, sizeof(n), "%s_clk", name);
131
132 for (i = 0; bulk && i < count; i++) {
133 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
134 return bulk[i].clk;
135 }
136
137
138 return NULL;
139 }
140
141 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
142 {
143 struct clk *clk;
144 char name2[32];
145
146 clk = devm_clk_get(&pdev->dev, name);
147 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
148 return clk;
149
150 snprintf(name2, sizeof(name2), "%s_clk", name);
151
152 clk = devm_clk_get(&pdev->dev, name2);
153 if (!IS_ERR(clk))
154 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
155 "\"%s\" instead of \"%s\"\n", name, name2);
156
157 return clk;
158 }
159
160 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
161 const char *dbgname)
162 {
163 struct resource *res;
164 unsigned long size;
165 void __iomem *ptr;
166
167 if (name)
168 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
169 else
170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
171
172 if (!res) {
173 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
174 return ERR_PTR(-EINVAL);
175 }
176
177 size = resource_size(res);
178
179 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
180 if (!ptr) {
181 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
182 return ERR_PTR(-ENOMEM);
183 }
184
185 if (reglog)
186 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
187
188 return ptr;
189 }
190
191 void msm_writel(u32 data, void __iomem *addr)
192 {
193 if (reglog)
194 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
195 writel(data, addr);
196 }
197
198 u32 msm_readl(const void __iomem *addr)
199 {
200 u32 val = readl(addr);
201 if (reglog)
202 pr_err("IO:R %p %08x\n", addr, val);
203 return val;
204 }
205
206 struct vblank_event {
207 struct list_head node;
208 int crtc_id;
209 bool enable;
210 };
211
212 static void vblank_ctrl_worker(struct kthread_work *work)
213 {
214 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
215 struct msm_vblank_ctrl, work);
216 struct msm_drm_private *priv = container_of(vbl_ctrl,
217 struct msm_drm_private, vblank_ctrl);
218 struct msm_kms *kms = priv->kms;
219 struct vblank_event *vbl_ev, *tmp;
220 unsigned long flags;
221
222 spin_lock_irqsave(&vbl_ctrl->lock, flags);
223 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
224 list_del(&vbl_ev->node);
225 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
226
227 if (vbl_ev->enable)
228 kms->funcs->enable_vblank(kms,
229 priv->crtcs[vbl_ev->crtc_id]);
230 else
231 kms->funcs->disable_vblank(kms,
232 priv->crtcs[vbl_ev->crtc_id]);
233
234 kfree(vbl_ev);
235
236 spin_lock_irqsave(&vbl_ctrl->lock, flags);
237 }
238
239 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
240 }
241
242 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
243 int crtc_id, bool enable)
244 {
245 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
246 struct vblank_event *vbl_ev;
247 unsigned long flags;
248
249 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
250 if (!vbl_ev)
251 return -ENOMEM;
252
253 vbl_ev->crtc_id = crtc_id;
254 vbl_ev->enable = enable;
255
256 spin_lock_irqsave(&vbl_ctrl->lock, flags);
257 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
258 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
259
260 kthread_queue_work(&priv->disp_thread[crtc_id].worker,
261 &vbl_ctrl->work);
262
263 return 0;
264 }
265
266 static int msm_drm_uninit(struct device *dev)
267 {
268 struct platform_device *pdev = to_platform_device(dev);
269 struct drm_device *ddev = platform_get_drvdata(pdev);
270 struct msm_drm_private *priv = ddev->dev_private;
271 struct msm_kms *kms = priv->kms;
272 struct msm_mdss *mdss = priv->mdss;
273 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
274 struct vblank_event *vbl_ev, *tmp;
275 int i;
276
277 /* We must cancel and cleanup any pending vblank enable/disable
278 * work before drm_irq_uninstall() to avoid work re-enabling an
279 * irq after uninstall has disabled it.
280 */
281 kthread_flush_work(&vbl_ctrl->work);
282 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
283 list_del(&vbl_ev->node);
284 kfree(vbl_ev);
285 }
286
287 /* clean up display commit/event worker threads */
288 for (i = 0; i < priv->num_crtcs; i++) {
289 if (priv->disp_thread[i].thread) {
290 kthread_flush_worker(&priv->disp_thread[i].worker);
291 kthread_stop(priv->disp_thread[i].thread);
292 priv->disp_thread[i].thread = NULL;
293 }
294
295 if (priv->event_thread[i].thread) {
296 kthread_flush_worker(&priv->event_thread[i].worker);
297 kthread_stop(priv->event_thread[i].thread);
298 priv->event_thread[i].thread = NULL;
299 }
300 }
301
302 msm_gem_shrinker_cleanup(ddev);
303
304 drm_kms_helper_poll_fini(ddev);
305
306 drm_dev_unregister(ddev);
307
308 msm_perf_debugfs_cleanup(priv);
309 msm_rd_debugfs_cleanup(priv);
310
311 #ifdef CONFIG_DRM_FBDEV_EMULATION
312 if (fbdev && priv->fbdev)
313 msm_fbdev_free(ddev);
314 #endif
315 drm_mode_config_cleanup(ddev);
316
317 pm_runtime_get_sync(dev);
318 drm_irq_uninstall(ddev);
319 pm_runtime_put_sync(dev);
320
321 flush_workqueue(priv->wq);
322 destroy_workqueue(priv->wq);
323
324 if (kms && kms->funcs)
325 kms->funcs->destroy(kms);
326
327 if (priv->vram.paddr) {
328 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
329 drm_mm_takedown(&priv->vram.mm);
330 dma_free_attrs(dev, priv->vram.size, NULL,
331 priv->vram.paddr, attrs);
332 }
333
334 component_unbind_all(dev, ddev);
335
336 if (mdss && mdss->funcs)
337 mdss->funcs->destroy(ddev);
338
339 ddev->dev_private = NULL;
340 drm_dev_unref(ddev);
341
342 kfree(priv);
343
344 return 0;
345 }
346
347 #define KMS_MDP4 4
348 #define KMS_MDP5 5
349 #define KMS_DPU 3
350
351 static int get_mdp_ver(struct platform_device *pdev)
352 {
353 struct device *dev = &pdev->dev;
354
355 return (int) (unsigned long) of_device_get_match_data(dev);
356 }
357
358 #include <linux/of_address.h>
359
360 static int msm_init_vram(struct drm_device *dev)
361 {
362 struct msm_drm_private *priv = dev->dev_private;
363 struct device_node *node;
364 unsigned long size = 0;
365 int ret = 0;
366
367 /* In the device-tree world, we could have a 'memory-region'
368 * phandle, which gives us a link to our "vram". Allocating
369 * is all nicely abstracted behind the dma api, but we need
370 * to know the entire size to allocate it all in one go. There
371 * are two cases:
372 * 1) device with no IOMMU, in which case we need exclusive
373 * access to a VRAM carveout big enough for all gpu
374 * buffers
375 * 2) device with IOMMU, but where the bootloader puts up
376 * a splash screen. In this case, the VRAM carveout
377 * need only be large enough for fbdev fb. But we need
378 * exclusive access to the buffer to avoid the kernel
379 * using those pages for other purposes (which appears
380 * as corruption on screen before we have a chance to
381 * load and do initial modeset)
382 */
383
384 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
385 if (node) {
386 struct resource r;
387 ret = of_address_to_resource(node, 0, &r);
388 of_node_put(node);
389 if (ret)
390 return ret;
391 size = r.end - r.start;
392 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
393
394 /* if we have no IOMMU, then we need to use carveout allocator.
395 * Grab the entire CMA chunk carved out in early startup in
396 * mach-msm:
397 */
398 } else if (!iommu_present(&platform_bus_type)) {
399 DRM_INFO("using %s VRAM carveout\n", vram);
400 size = memparse(vram, NULL);
401 }
402
403 if (size) {
404 unsigned long attrs = 0;
405 void *p;
406
407 priv->vram.size = size;
408
409 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
410 spin_lock_init(&priv->vram.lock);
411
412 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
413 attrs |= DMA_ATTR_WRITE_COMBINE;
414
415 /* note that for no-kernel-mapping, the vaddr returned
416 * is bogus, but non-null if allocation succeeded:
417 */
418 p = dma_alloc_attrs(dev->dev, size,
419 &priv->vram.paddr, GFP_KERNEL, attrs);
420 if (!p) {
421 dev_err(dev->dev, "failed to allocate VRAM\n");
422 priv->vram.paddr = 0;
423 return -ENOMEM;
424 }
425
426 dev_info(dev->dev, "VRAM: %08x->%08x\n",
427 (uint32_t)priv->vram.paddr,
428 (uint32_t)(priv->vram.paddr + size));
429 }
430
431 return ret;
432 }
433
434 static int msm_drm_init(struct device *dev, struct drm_driver *drv)
435 {
436 struct platform_device *pdev = to_platform_device(dev);
437 struct drm_device *ddev;
438 struct msm_drm_private *priv;
439 struct msm_kms *kms;
440 struct msm_mdss *mdss;
441 int ret, i;
442 struct sched_param param;
443
444 ddev = drm_dev_alloc(drv, dev);
445 if (IS_ERR(ddev)) {
446 dev_err(dev, "failed to allocate drm_device\n");
447 return PTR_ERR(ddev);
448 }
449
450 platform_set_drvdata(pdev, ddev);
451
452 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
453 if (!priv) {
454 ret = -ENOMEM;
455 goto err_unref_drm_dev;
456 }
457
458 ddev->dev_private = priv;
459 priv->dev = ddev;
460
461 switch (get_mdp_ver(pdev)) {
462 case KMS_MDP5:
463 ret = mdp5_mdss_init(ddev);
464 break;
465 case KMS_DPU:
466 ret = dpu_mdss_init(ddev);
467 break;
468 default:
469 ret = 0;
470 break;
471 }
472 if (ret)
473 goto err_free_priv;
474
475 mdss = priv->mdss;
476
477 priv->wq = alloc_ordered_workqueue("msm", 0);
478
479 INIT_LIST_HEAD(&priv->inactive_list);
480 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
481 kthread_init_work(&priv->vblank_ctrl.work, vblank_ctrl_worker);
482 spin_lock_init(&priv->vblank_ctrl.lock);
483
484 drm_mode_config_init(ddev);
485
486 /* Bind all our sub-components: */
487 ret = component_bind_all(dev, ddev);
488 if (ret)
489 goto err_destroy_mdss;
490
491 ret = msm_init_vram(ddev);
492 if (ret)
493 goto err_msm_uninit;
494
495 if (!dev->dma_parms) {
496 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
497 GFP_KERNEL);
498 if (!dev->dma_parms)
499 return -ENOMEM;
500 }
501 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
502
503 msm_gem_shrinker_init(ddev);
504
505 switch (get_mdp_ver(pdev)) {
506 case KMS_MDP4:
507 kms = mdp4_kms_init(ddev);
508 priv->kms = kms;
509 break;
510 case KMS_MDP5:
511 kms = mdp5_kms_init(ddev);
512 break;
513 case KMS_DPU:
514 kms = dpu_kms_init(ddev);
515 priv->kms = kms;
516 break;
517 default:
518 kms = ERR_PTR(-ENODEV);
519 break;
520 }
521
522 if (IS_ERR(kms)) {
523 /*
524 * NOTE: once we have GPU support, having no kms should not
525 * be considered fatal.. ideally we would still support gpu
526 * and (for example) use dmabuf/prime to share buffers with
527 * imx drm driver on iMX5
528 */
529 dev_err(dev, "failed to load kms\n");
530 ret = PTR_ERR(kms);
531 goto err_msm_uninit;
532 }
533
534 /* Enable normalization of plane zpos */
535 ddev->mode_config.normalize_zpos = true;
536
537 if (kms) {
538 ret = kms->funcs->hw_init(kms);
539 if (ret) {
540 dev_err(dev, "kms hw init failed: %d\n", ret);
541 goto err_msm_uninit;
542 }
543 }
544
545 ddev->mode_config.funcs = &mode_config_funcs;
546 ddev->mode_config.helper_private = &mode_config_helper_funcs;
547
548 /**
549 * this priority was found during empiric testing to have appropriate
550 * realtime scheduling to process display updates and interact with
551 * other real time and normal priority task
552 */
553 param.sched_priority = 16;
554 for (i = 0; i < priv->num_crtcs; i++) {
555
556 /* initialize display thread */
557 priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
558 kthread_init_worker(&priv->disp_thread[i].worker);
559 priv->disp_thread[i].dev = ddev;
560 priv->disp_thread[i].thread =
561 kthread_run(kthread_worker_fn,
562 &priv->disp_thread[i].worker,
563 "crtc_commit:%d", priv->disp_thread[i].crtc_id);
564 ret = sched_setscheduler(priv->disp_thread[i].thread,
565 SCHED_FIFO, &param);
566 if (ret)
567 pr_warn("display thread priority update failed: %d\n",
568 ret);
569
570 if (IS_ERR(priv->disp_thread[i].thread)) {
571 dev_err(dev, "failed to create crtc_commit kthread\n");
572 priv->disp_thread[i].thread = NULL;
573 }
574
575 /* initialize event thread */
576 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
577 kthread_init_worker(&priv->event_thread[i].worker);
578 priv->event_thread[i].dev = ddev;
579 priv->event_thread[i].thread =
580 kthread_run(kthread_worker_fn,
581 &priv->event_thread[i].worker,
582 "crtc_event:%d", priv->event_thread[i].crtc_id);
583 /**
584 * event thread should also run at same priority as disp_thread
585 * because it is handling frame_done events. A lower priority
586 * event thread and higher priority disp_thread can causes
587 * frame_pending counters beyond 2. This can lead to commit
588 * failure at crtc commit level.
589 */
590 ret = sched_setscheduler(priv->event_thread[i].thread,
591 SCHED_FIFO, &param);
592 if (ret)
593 pr_warn("display event thread priority update failed: %d\n",
594 ret);
595
596 if (IS_ERR(priv->event_thread[i].thread)) {
597 dev_err(dev, "failed to create crtc_event kthread\n");
598 priv->event_thread[i].thread = NULL;
599 }
600
601 if ((!priv->disp_thread[i].thread) ||
602 !priv->event_thread[i].thread) {
603 /* clean up previously created threads if any */
604 for ( ; i >= 0; i--) {
605 if (priv->disp_thread[i].thread) {
606 kthread_stop(
607 priv->disp_thread[i].thread);
608 priv->disp_thread[i].thread = NULL;
609 }
610
611 if (priv->event_thread[i].thread) {
612 kthread_stop(
613 priv->event_thread[i].thread);
614 priv->event_thread[i].thread = NULL;
615 }
616 }
617 goto err_msm_uninit;
618 }
619 }
620
621 ret = drm_vblank_init(ddev, priv->num_crtcs);
622 if (ret < 0) {
623 dev_err(dev, "failed to initialize vblank\n");
624 goto err_msm_uninit;
625 }
626
627 if (kms) {
628 pm_runtime_get_sync(dev);
629 ret = drm_irq_install(ddev, kms->irq);
630 pm_runtime_put_sync(dev);
631 if (ret < 0) {
632 dev_err(dev, "failed to install IRQ handler\n");
633 goto err_msm_uninit;
634 }
635 }
636
637 ret = drm_dev_register(ddev, 0);
638 if (ret)
639 goto err_msm_uninit;
640
641 drm_mode_config_reset(ddev);
642
643 #ifdef CONFIG_DRM_FBDEV_EMULATION
644 if (fbdev)
645 priv->fbdev = msm_fbdev_init(ddev);
646 #endif
647
648 ret = msm_debugfs_late_init(ddev);
649 if (ret)
650 goto err_msm_uninit;
651
652 drm_kms_helper_poll_init(ddev);
653
654 return 0;
655
656 err_msm_uninit:
657 msm_drm_uninit(dev);
658 return ret;
659 err_destroy_mdss:
660 if (mdss && mdss->funcs)
661 mdss->funcs->destroy(ddev);
662 err_free_priv:
663 kfree(priv);
664 err_unref_drm_dev:
665 drm_dev_unref(ddev);
666 return ret;
667 }
668
669 /*
670 * DRM operations:
671 */
672
673 static void load_gpu(struct drm_device *dev)
674 {
675 static DEFINE_MUTEX(init_lock);
676 struct msm_drm_private *priv = dev->dev_private;
677
678 mutex_lock(&init_lock);
679
680 if (!priv->gpu)
681 priv->gpu = adreno_load_gpu(dev);
682
683 mutex_unlock(&init_lock);
684 }
685
686 static int context_init(struct drm_device *dev, struct drm_file *file)
687 {
688 struct msm_file_private *ctx;
689
690 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
691 if (!ctx)
692 return -ENOMEM;
693
694 msm_submitqueue_init(dev, ctx);
695
696 file->driver_priv = ctx;
697
698 return 0;
699 }
700
701 static int msm_open(struct drm_device *dev, struct drm_file *file)
702 {
703 /* For now, load gpu on open.. to avoid the requirement of having
704 * firmware in the initrd.
705 */
706 load_gpu(dev);
707
708 return context_init(dev, file);
709 }
710
711 static void context_close(struct msm_file_private *ctx)
712 {
713 msm_submitqueue_close(ctx);
714 kfree(ctx);
715 }
716
717 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
718 {
719 struct msm_drm_private *priv = dev->dev_private;
720 struct msm_file_private *ctx = file->driver_priv;
721
722 mutex_lock(&dev->struct_mutex);
723 if (ctx == priv->lastctx)
724 priv->lastctx = NULL;
725 mutex_unlock(&dev->struct_mutex);
726
727 context_close(ctx);
728 }
729
730 static irqreturn_t msm_irq(int irq, void *arg)
731 {
732 struct drm_device *dev = arg;
733 struct msm_drm_private *priv = dev->dev_private;
734 struct msm_kms *kms = priv->kms;
735 BUG_ON(!kms);
736 return kms->funcs->irq(kms);
737 }
738
739 static void msm_irq_preinstall(struct drm_device *dev)
740 {
741 struct msm_drm_private *priv = dev->dev_private;
742 struct msm_kms *kms = priv->kms;
743 BUG_ON(!kms);
744 kms->funcs->irq_preinstall(kms);
745 }
746
747 static int msm_irq_postinstall(struct drm_device *dev)
748 {
749 struct msm_drm_private *priv = dev->dev_private;
750 struct msm_kms *kms = priv->kms;
751 BUG_ON(!kms);
752 return kms->funcs->irq_postinstall(kms);
753 }
754
755 static void msm_irq_uninstall(struct drm_device *dev)
756 {
757 struct msm_drm_private *priv = dev->dev_private;
758 struct msm_kms *kms = priv->kms;
759 BUG_ON(!kms);
760 kms->funcs->irq_uninstall(kms);
761 }
762
763 static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
764 {
765 struct msm_drm_private *priv = dev->dev_private;
766 struct msm_kms *kms = priv->kms;
767 if (!kms)
768 return -ENXIO;
769 DBG("dev=%p, crtc=%u", dev, pipe);
770 return vblank_ctrl_queue_work(priv, pipe, true);
771 }
772
773 static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
774 {
775 struct msm_drm_private *priv = dev->dev_private;
776 struct msm_kms *kms = priv->kms;
777 if (!kms)
778 return;
779 DBG("dev=%p, crtc=%u", dev, pipe);
780 vblank_ctrl_queue_work(priv, pipe, false);
781 }
782
783 /*
784 * DRM ioctls:
785 */
786
787 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
788 struct drm_file *file)
789 {
790 struct msm_drm_private *priv = dev->dev_private;
791 struct drm_msm_param *args = data;
792 struct msm_gpu *gpu;
793
794 /* for now, we just have 3d pipe.. eventually this would need to
795 * be more clever to dispatch to appropriate gpu module:
796 */
797 if (args->pipe != MSM_PIPE_3D0)
798 return -EINVAL;
799
800 gpu = priv->gpu;
801
802 if (!gpu)
803 return -ENXIO;
804
805 return gpu->funcs->get_param(gpu, args->param, &args->value);
806 }
807
808 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
809 struct drm_file *file)
810 {
811 struct drm_msm_gem_new *args = data;
812
813 if (args->flags & ~MSM_BO_FLAGS) {
814 DRM_ERROR("invalid flags: %08x\n", args->flags);
815 return -EINVAL;
816 }
817
818 return msm_gem_new_handle(dev, file, args->size,
819 args->flags, &args->handle);
820 }
821
822 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
823 {
824 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
825 }
826
827 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
828 struct drm_file *file)
829 {
830 struct drm_msm_gem_cpu_prep *args = data;
831 struct drm_gem_object *obj;
832 ktime_t timeout = to_ktime(args->timeout);
833 int ret;
834
835 if (args->op & ~MSM_PREP_FLAGS) {
836 DRM_ERROR("invalid op: %08x\n", args->op);
837 return -EINVAL;
838 }
839
840 obj = drm_gem_object_lookup(file, args->handle);
841 if (!obj)
842 return -ENOENT;
843
844 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
845
846 drm_gem_object_put_unlocked(obj);
847
848 return ret;
849 }
850
851 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
852 struct drm_file *file)
853 {
854 struct drm_msm_gem_cpu_fini *args = data;
855 struct drm_gem_object *obj;
856 int ret;
857
858 obj = drm_gem_object_lookup(file, args->handle);
859 if (!obj)
860 return -ENOENT;
861
862 ret = msm_gem_cpu_fini(obj);
863
864 drm_gem_object_put_unlocked(obj);
865
866 return ret;
867 }
868
869 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
870 struct drm_gem_object *obj, uint64_t *iova)
871 {
872 struct msm_drm_private *priv = dev->dev_private;
873
874 if (!priv->gpu)
875 return -EINVAL;
876
877 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
878 }
879
880 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
881 struct drm_file *file)
882 {
883 struct drm_msm_gem_info *args = data;
884 struct drm_gem_object *obj;
885 int ret = 0;
886
887 if (args->flags & ~MSM_INFO_FLAGS)
888 return -EINVAL;
889
890 obj = drm_gem_object_lookup(file, args->handle);
891 if (!obj)
892 return -ENOENT;
893
894 if (args->flags & MSM_INFO_IOVA) {
895 uint64_t iova;
896
897 ret = msm_ioctl_gem_info_iova(dev, obj, &iova);
898 if (!ret)
899 args->offset = iova;
900 } else {
901 args->offset = msm_gem_mmap_offset(obj);
902 }
903
904 drm_gem_object_put_unlocked(obj);
905
906 return ret;
907 }
908
909 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
910 struct drm_file *file)
911 {
912 struct msm_drm_private *priv = dev->dev_private;
913 struct drm_msm_wait_fence *args = data;
914 ktime_t timeout = to_ktime(args->timeout);
915 struct msm_gpu_submitqueue *queue;
916 struct msm_gpu *gpu = priv->gpu;
917 int ret;
918
919 if (args->pad) {
920 DRM_ERROR("invalid pad: %08x\n", args->pad);
921 return -EINVAL;
922 }
923
924 if (!gpu)
925 return 0;
926
927 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
928 if (!queue)
929 return -ENOENT;
930
931 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
932 true);
933
934 msm_submitqueue_put(queue);
935 return ret;
936 }
937
938 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
939 struct drm_file *file)
940 {
941 struct drm_msm_gem_madvise *args = data;
942 struct drm_gem_object *obj;
943 int ret;
944
945 switch (args->madv) {
946 case MSM_MADV_DONTNEED:
947 case MSM_MADV_WILLNEED:
948 break;
949 default:
950 return -EINVAL;
951 }
952
953 ret = mutex_lock_interruptible(&dev->struct_mutex);
954 if (ret)
955 return ret;
956
957 obj = drm_gem_object_lookup(file, args->handle);
958 if (!obj) {
959 ret = -ENOENT;
960 goto unlock;
961 }
962
963 ret = msm_gem_madvise(obj, args->madv);
964 if (ret >= 0) {
965 args->retained = ret;
966 ret = 0;
967 }
968
969 drm_gem_object_put(obj);
970
971 unlock:
972 mutex_unlock(&dev->struct_mutex);
973 return ret;
974 }
975
976
977 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
978 struct drm_file *file)
979 {
980 struct drm_msm_submitqueue *args = data;
981
982 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
983 return -EINVAL;
984
985 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
986 args->flags, &args->id);
987 }
988
989
990 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
991 struct drm_file *file)
992 {
993 u32 id = *(u32 *) data;
994
995 return msm_submitqueue_remove(file->driver_priv, id);
996 }
997
998 static const struct drm_ioctl_desc msm_ioctls[] = {
999 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
1000 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
1001 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
1002 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
1003 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
1004 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
1005 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
1006 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
1007 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
1008 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
1009 };
1010
1011 static const struct vm_operations_struct vm_ops = {
1012 .fault = msm_gem_fault,
1013 .open = drm_gem_vm_open,
1014 .close = drm_gem_vm_close,
1015 };
1016
1017 static const struct file_operations fops = {
1018 .owner = THIS_MODULE,
1019 .open = drm_open,
1020 .release = drm_release,
1021 .unlocked_ioctl = drm_ioctl,
1022 .compat_ioctl = drm_compat_ioctl,
1023 .poll = drm_poll,
1024 .read = drm_read,
1025 .llseek = no_llseek,
1026 .mmap = msm_gem_mmap,
1027 };
1028
1029 static struct drm_driver msm_driver = {
1030 .driver_features = DRIVER_HAVE_IRQ |
1031 DRIVER_GEM |
1032 DRIVER_PRIME |
1033 DRIVER_RENDER |
1034 DRIVER_ATOMIC |
1035 DRIVER_MODESET,
1036 .open = msm_open,
1037 .postclose = msm_postclose,
1038 .lastclose = drm_fb_helper_lastclose,
1039 .irq_handler = msm_irq,
1040 .irq_preinstall = msm_irq_preinstall,
1041 .irq_postinstall = msm_irq_postinstall,
1042 .irq_uninstall = msm_irq_uninstall,
1043 .enable_vblank = msm_enable_vblank,
1044 .disable_vblank = msm_disable_vblank,
1045 .gem_free_object = msm_gem_free_object,
1046 .gem_vm_ops = &vm_ops,
1047 .dumb_create = msm_gem_dumb_create,
1048 .dumb_map_offset = msm_gem_dumb_map_offset,
1049 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1050 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1051 .gem_prime_export = drm_gem_prime_export,
1052 .gem_prime_import = drm_gem_prime_import,
1053 .gem_prime_res_obj = msm_gem_prime_res_obj,
1054 .gem_prime_pin = msm_gem_prime_pin,
1055 .gem_prime_unpin = msm_gem_prime_unpin,
1056 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1057 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1058 .gem_prime_vmap = msm_gem_prime_vmap,
1059 .gem_prime_vunmap = msm_gem_prime_vunmap,
1060 .gem_prime_mmap = msm_gem_prime_mmap,
1061 #ifdef CONFIG_DEBUG_FS
1062 .debugfs_init = msm_debugfs_init,
1063 #endif
1064 .ioctls = msm_ioctls,
1065 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1066 .fops = &fops,
1067 .name = "msm",
1068 .desc = "MSM Snapdragon DRM",
1069 .date = "20130625",
1070 .major = MSM_VERSION_MAJOR,
1071 .minor = MSM_VERSION_MINOR,
1072 .patchlevel = MSM_VERSION_PATCHLEVEL,
1073 };
1074
1075 #ifdef CONFIG_PM_SLEEP
1076 static int msm_pm_suspend(struct device *dev)
1077 {
1078 struct drm_device *ddev = dev_get_drvdata(dev);
1079 struct msm_drm_private *priv = ddev->dev_private;
1080 struct msm_kms *kms = priv->kms;
1081
1082 /* TODO: Use atomic helper suspend/resume */
1083 if (kms && kms->funcs && kms->funcs->pm_suspend)
1084 return kms->funcs->pm_suspend(dev);
1085
1086 drm_kms_helper_poll_disable(ddev);
1087
1088 priv->pm_state = drm_atomic_helper_suspend(ddev);
1089 if (IS_ERR(priv->pm_state)) {
1090 drm_kms_helper_poll_enable(ddev);
1091 return PTR_ERR(priv->pm_state);
1092 }
1093
1094 return 0;
1095 }
1096
1097 static int msm_pm_resume(struct device *dev)
1098 {
1099 struct drm_device *ddev = dev_get_drvdata(dev);
1100 struct msm_drm_private *priv = ddev->dev_private;
1101 struct msm_kms *kms = priv->kms;
1102
1103 /* TODO: Use atomic helper suspend/resume */
1104 if (kms && kms->funcs && kms->funcs->pm_resume)
1105 return kms->funcs->pm_resume(dev);
1106
1107 drm_atomic_helper_resume(ddev, priv->pm_state);
1108 drm_kms_helper_poll_enable(ddev);
1109
1110 return 0;
1111 }
1112 #endif
1113
1114 #ifdef CONFIG_PM
1115 static int msm_runtime_suspend(struct device *dev)
1116 {
1117 struct drm_device *ddev = dev_get_drvdata(dev);
1118 struct msm_drm_private *priv = ddev->dev_private;
1119 struct msm_mdss *mdss = priv->mdss;
1120
1121 DBG("");
1122
1123 if (mdss && mdss->funcs)
1124 return mdss->funcs->disable(mdss);
1125
1126 return 0;
1127 }
1128
1129 static int msm_runtime_resume(struct device *dev)
1130 {
1131 struct drm_device *ddev = dev_get_drvdata(dev);
1132 struct msm_drm_private *priv = ddev->dev_private;
1133 struct msm_mdss *mdss = priv->mdss;
1134
1135 DBG("");
1136
1137 if (mdss && mdss->funcs)
1138 return mdss->funcs->enable(mdss);
1139
1140 return 0;
1141 }
1142 #endif
1143
1144 static const struct dev_pm_ops msm_pm_ops = {
1145 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1146 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1147 };
1148
1149 /*
1150 * Componentized driver support:
1151 */
1152
1153 /*
1154 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1155 * so probably some room for some helpers
1156 */
1157 static int compare_of(struct device *dev, void *data)
1158 {
1159 return dev->of_node == data;
1160 }
1161
1162 /*
1163 * Identify what components need to be added by parsing what remote-endpoints
1164 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1165 * is no external component that we need to add since LVDS is within MDP4
1166 * itself.
1167 */
1168 static int add_components_mdp(struct device *mdp_dev,
1169 struct component_match **matchptr)
1170 {
1171 struct device_node *np = mdp_dev->of_node;
1172 struct device_node *ep_node;
1173 struct device *master_dev;
1174
1175 /*
1176 * on MDP4 based platforms, the MDP platform device is the component
1177 * master that adds other display interface components to itself.
1178 *
1179 * on MDP5 based platforms, the MDSS platform device is the component
1180 * master that adds MDP5 and other display interface components to
1181 * itself.
1182 */
1183 if (of_device_is_compatible(np, "qcom,mdp4"))
1184 master_dev = mdp_dev;
1185 else
1186 master_dev = mdp_dev->parent;
1187
1188 for_each_endpoint_of_node(np, ep_node) {
1189 struct device_node *intf;
1190 struct of_endpoint ep;
1191 int ret;
1192
1193 ret = of_graph_parse_endpoint(ep_node, &ep);
1194 if (ret) {
1195 dev_err(mdp_dev, "unable to parse port endpoint\n");
1196 of_node_put(ep_node);
1197 return ret;
1198 }
1199
1200 /*
1201 * The LCDC/LVDS port on MDP4 is a speacial case where the
1202 * remote-endpoint isn't a component that we need to add
1203 */
1204 if (of_device_is_compatible(np, "qcom,mdp4") &&
1205 ep.port == 0)
1206 continue;
1207
1208 /*
1209 * It's okay if some of the ports don't have a remote endpoint
1210 * specified. It just means that the port isn't connected to
1211 * any external interface.
1212 */
1213 intf = of_graph_get_remote_port_parent(ep_node);
1214 if (!intf)
1215 continue;
1216
1217 drm_of_component_match_add(master_dev, matchptr, compare_of,
1218 intf);
1219 of_node_put(intf);
1220 }
1221
1222 return 0;
1223 }
1224
1225 static int compare_name_mdp(struct device *dev, void *data)
1226 {
1227 return (strstr(dev_name(dev), "mdp") != NULL);
1228 }
1229
1230 static int add_display_components(struct device *dev,
1231 struct component_match **matchptr)
1232 {
1233 struct device *mdp_dev;
1234 int ret;
1235
1236 /*
1237 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1238 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1239 * Populate the children devices, find the MDP5/DPU node, and then add
1240 * the interfaces to our components list.
1241 */
1242 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1243 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1244 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1245 if (ret) {
1246 dev_err(dev, "failed to populate children devices\n");
1247 return ret;
1248 }
1249
1250 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1251 if (!mdp_dev) {
1252 dev_err(dev, "failed to find MDSS MDP node\n");
1253 of_platform_depopulate(dev);
1254 return -ENODEV;
1255 }
1256
1257 put_device(mdp_dev);
1258
1259 /* add the MDP component itself */
1260 drm_of_component_match_add(dev, matchptr, compare_of,
1261 mdp_dev->of_node);
1262 } else {
1263 /* MDP4 */
1264 mdp_dev = dev;
1265 }
1266
1267 ret = add_components_mdp(mdp_dev, matchptr);
1268 if (ret)
1269 of_platform_depopulate(dev);
1270
1271 return ret;
1272 }
1273
1274 /*
1275 * We don't know what's the best binding to link the gpu with the drm device.
1276 * Fow now, we just hunt for all the possible gpus that we support, and add them
1277 * as components.
1278 */
1279 static const struct of_device_id msm_gpu_match[] = {
1280 { .compatible = "qcom,adreno" },
1281 { .compatible = "qcom,adreno-3xx" },
1282 { .compatible = "qcom,kgsl-3d0" },
1283 { },
1284 };
1285
1286 static int add_gpu_components(struct device *dev,
1287 struct component_match **matchptr)
1288 {
1289 struct device_node *np;
1290
1291 np = of_find_matching_node(NULL, msm_gpu_match);
1292 if (!np)
1293 return 0;
1294
1295 if (of_device_is_available(np))
1296 drm_of_component_match_add(dev, matchptr, compare_of, np);
1297
1298 of_node_put(np);
1299
1300 return 0;
1301 }
1302
1303 static int msm_drm_bind(struct device *dev)
1304 {
1305 return msm_drm_init(dev, &msm_driver);
1306 }
1307
1308 static void msm_drm_unbind(struct device *dev)
1309 {
1310 msm_drm_uninit(dev);
1311 }
1312
1313 static const struct component_master_ops msm_drm_ops = {
1314 .bind = msm_drm_bind,
1315 .unbind = msm_drm_unbind,
1316 };
1317
1318 /*
1319 * Platform driver:
1320 */
1321
1322 static int msm_pdev_probe(struct platform_device *pdev)
1323 {
1324 struct component_match *match = NULL;
1325 int ret;
1326
1327 ret = add_display_components(&pdev->dev, &match);
1328 if (ret)
1329 return ret;
1330
1331 ret = add_gpu_components(&pdev->dev, &match);
1332 if (ret)
1333 goto fail;
1334
1335 /* on all devices that I am aware of, iommu's which can map
1336 * any address the cpu can see are used:
1337 */
1338 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1339 if (ret)
1340 goto fail;
1341
1342 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1343 if (ret)
1344 goto fail;
1345
1346 return 0;
1347
1348 fail:
1349 of_platform_depopulate(&pdev->dev);
1350 return ret;
1351 }
1352
1353 static int msm_pdev_remove(struct platform_device *pdev)
1354 {
1355 component_master_del(&pdev->dev, &msm_drm_ops);
1356 of_platform_depopulate(&pdev->dev);
1357
1358 return 0;
1359 }
1360
1361 static const struct of_device_id dt_match[] = {
1362 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1363 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1364 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1365 {}
1366 };
1367 MODULE_DEVICE_TABLE(of, dt_match);
1368
1369 static struct platform_driver msm_platform_driver = {
1370 .probe = msm_pdev_probe,
1371 .remove = msm_pdev_remove,
1372 .driver = {
1373 .name = "msm",
1374 .of_match_table = dt_match,
1375 .pm = &msm_pm_ops,
1376 },
1377 };
1378
1379 static int __init msm_drm_register(void)
1380 {
1381 if (!modeset)
1382 return -EINVAL;
1383
1384 DBG("init");
1385 msm_mdp_register();
1386 msm_dpu_register();
1387 msm_dsi_register();
1388 msm_edp_register();
1389 msm_hdmi_register();
1390 adreno_register();
1391 return platform_driver_register(&msm_platform_driver);
1392 }
1393
1394 static void __exit msm_drm_unregister(void)
1395 {
1396 DBG("fini");
1397 platform_driver_unregister(&msm_platform_driver);
1398 msm_hdmi_unregister();
1399 adreno_unregister();
1400 msm_edp_unregister();
1401 msm_dsi_unregister();
1402 msm_mdp_unregister();
1403 msm_dpu_unregister();
1404 }
1405
1406 module_init(msm_drm_register);
1407 module_exit(msm_drm_unregister);
1408
1409 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1410 MODULE_DESCRIPTION("MSM DRM Driver");
1411 MODULE_LICENSE("GPL");
Linux with added FPC-III support