drivers/gpu/ipu-v3/ipu-pre.c

   1 /*
   2  * Copyright (c) 2017 Lucas Stach, Pengutronix
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  */
  13
  14 #include <drm/drm_fourcc.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/genalloc.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <video/imx-ipu-v3.h>
  22
  23 #include "ipu-prv.h"
  24
  25 #define IPU_PRE_MAX_WIDTH       2048
  26 #define IPU_PRE_NUM_SCANLINES   8
  27
  28 #define IPU_PRE_CTRL                                    0x000
  29 #define IPU_PRE_CTRL_SET                                0x004
  30 #define  IPU_PRE_CTRL_ENABLE                            (1 << 0)
  31 #define  IPU_PRE_CTRL_BLOCK_EN                          (1 << 1)
  32 #define  IPU_PRE_CTRL_BLOCK_16                          (1 << 2)
  33 #define  IPU_PRE_CTRL_SDW_UPDATE                        (1 << 4)
  34 #define  IPU_PRE_CTRL_VFLIP                             (1 << 5)
  35 #define  IPU_PRE_CTRL_SO                                (1 << 6)
  36 #define  IPU_PRE_CTRL_INTERLACED_FIELD                  (1 << 7)
  37 #define  IPU_PRE_CTRL_HANDSHAKE_EN                      (1 << 8)
  38 #define  IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v)             ((v & 0x3) << 9)
  39 #define  IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN           (1 << 11)
  40 #define  IPU_PRE_CTRL_EN_REPEAT                         (1 << 28)
  41 #define  IPU_PRE_CTRL_TPR_REST_SEL                      (1 << 29)
  42 #define  IPU_PRE_CTRL_CLKGATE                           (1 << 30)
  43 #define  IPU_PRE_CTRL_SFTRST                            (1 << 31)
  44
  45 #define IPU_PRE_CUR_BUF                                 0x030
  46
  47 #define IPU_PRE_NEXT_BUF                                0x040
  48
  49 #define IPU_PRE_TPR_CTRL                                0x070
  50 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT(v)                ((v & 0xff) << 0)
  51 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK              0xff
  52 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT            (1 << 0)
  53 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SPLIT_BUF         (1 << 4)
  54 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF        (1 << 5)
  55 #define  IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED       (1 << 6)
  56
  57 #define IPU_PRE_PREFETCH_ENG_CTRL                       0x080
  58 #define  IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN              (1 << 0)
  59 #define  IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v)          ((v & 0x7) << 1)
  60 #define  IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v)      ((v & 0x3) << 4)
  61 #define  IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v)    ((v & 0x7) << 8)
  62 #define  IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS             (1 << 11)
  63 #define  IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE            (1 << 12)
  64 #define  IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP          (1 << 14)
  65 #define  IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN       (1 << 15)
  66
  67 #define IPU_PRE_PREFETCH_ENG_INPUT_SIZE                 0x0a0
  68 #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v)       ((v & 0xffff) << 0)
  69 #define  IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v)      ((v & 0xffff) << 16)
  70
  71 #define IPU_PRE_PREFETCH_ENG_PITCH                      0x0d0
  72 #define  IPU_PRE_PREFETCH_ENG_PITCH_Y(v)                ((v & 0xffff) << 0)
  73 #define  IPU_PRE_PREFETCH_ENG_PITCH_UV(v)               ((v & 0xffff) << 16)
  74
  75 #define IPU_PRE_STORE_ENG_CTRL                          0x110
  76 #define  IPU_PRE_STORE_ENG_CTRL_STORE_EN                (1 << 0)
  77 #define  IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v)         ((v & 0x7) << 1)
  78 #define  IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v)    ((v & 0x3) << 4)
  79
  80 #define IPU_PRE_STORE_ENG_STATUS                        0x120
  81 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK    0xffff
  82 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT   0
  83 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK    0x3fff
  84 #define  IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT   16
  85 #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL       (1 << 30)
  86 #define  IPU_PRE_STORE_ENG_STATUS_STORE_FIELD           (1 << 31)
  87
  88 #define IPU_PRE_STORE_ENG_SIZE                          0x130
  89 #define  IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v)          ((v & 0xffff) << 0)
  90 #define  IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v)         ((v & 0xffff) << 16)
  91
  92 #define IPU_PRE_STORE_ENG_PITCH                         0x140
  93 #define  IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v)           ((v & 0xffff) << 0)
  94
  95 #define IPU_PRE_STORE_ENG_ADDR                          0x150
  96
  97 struct ipu_pre {
  98         struct list_head        list;
  99         struct device           *dev;
 100
 101         void __iomem            *regs;
 102         struct clk              *clk_axi;
 103         struct gen_pool         *iram;
 104
 105         dma_addr_t              buffer_paddr;
 106         void                    *buffer_virt;
 107         bool                    in_use;
 108         unsigned int            safe_window_end;
 109         unsigned int            last_bufaddr;
 110 };
 111
 112 static DEFINE_MUTEX(ipu_pre_list_mutex);
 113 static LIST_HEAD(ipu_pre_list);
 114 static int available_pres;
 115
 116 int ipu_pre_get_available_count(void)
 117 {
 118         return available_pres;
 119 }
 120
 121 struct ipu_pre *
 122 ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index)
 123 {
 124         struct device_node *pre_node = of_parse_phandle(dev->of_node,
 125                                                         name, index);
 126         struct ipu_pre *pre;
 127
 128         mutex_lock(&ipu_pre_list_mutex);
 129         list_for_each_entry(pre, &ipu_pre_list, list) {
 130                 if (pre_node == pre->dev->of_node) {
 131                         mutex_unlock(&ipu_pre_list_mutex);
 132                         device_link_add(dev, pre->dev,
 133                                         DL_FLAG_AUTOREMOVE_CONSUMER);
 134                         of_node_put(pre_node);
 135                         return pre;
 136                 }
 137         }
 138         mutex_unlock(&ipu_pre_list_mutex);
 139
 140         of_node_put(pre_node);
 141
 142         return NULL;
 143 }
 144
 145 int ipu_pre_get(struct ipu_pre *pre)
 146 {
 147         u32 val;
 148
 149         if (pre->in_use)
 150                 return -EBUSY;
 151
 152         /* first get the engine out of reset and remove clock gating */
 153         writel(0, pre->regs + IPU_PRE_CTRL);
 154
 155         /* init defaults that should be applied to all streams */
 156         val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN |
 157               IPU_PRE_CTRL_HANDSHAKE_EN |
 158               IPU_PRE_CTRL_TPR_REST_SEL |
 159               IPU_PRE_CTRL_SDW_UPDATE;
 160         writel(val, pre->regs + IPU_PRE_CTRL);
 161
 162         pre->in_use = true;
 163         return 0;
 164 }
 165
 166 void ipu_pre_put(struct ipu_pre *pre)
 167 {
 168         writel(IPU_PRE_CTRL_SFTRST, pre->regs + IPU_PRE_CTRL);
 169
 170         pre->in_use = false;
 171 }
 172
 173 void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
 174                        unsigned int height, unsigned int stride, u32 format,
 175                        uint64_t modifier, unsigned int bufaddr)
 176 {
 177         const struct drm_format_info *info = drm_format_info(format);
 178         u32 active_bpp = info->cpp[0] >> 1;
 179         u32 val;
 180
 181         /* calculate safe window for ctrl register updates */
 182         if (modifier == DRM_FORMAT_MOD_LINEAR)
 183                 pre->safe_window_end = height - 2;
 184         else
 185                 pre->safe_window_end = DIV_ROUND_UP(height, 4) - 1;
 186
 187         writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
 188         writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
 189         pre->last_bufaddr = bufaddr;
 190
 191         val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
 192               IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
 193               IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) |
 194               IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS |
 195               IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN;
 196         writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL);
 197
 198         val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) |
 199               IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height);
 200         writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE);
 201
 202         val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride);
 203         writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH);
 204
 205         val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) |
 206               IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) |
 207               IPU_PRE_STORE_ENG_CTRL_STORE_EN;
 208         writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL);
 209
 210         val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) |
 211               IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height);
 212         writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE);
 213
 214         val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride);
 215         writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH);
 216
 217         writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR);
 218
 219         val = readl(pre->regs + IPU_PRE_TPR_CTRL);
 220         val &= ~IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK;
 221         if (modifier != DRM_FORMAT_MOD_LINEAR) {
 222                 /* only support single buffer formats for now */
 223                 val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SINGLE_BUF;
 224                 if (modifier == DRM_FORMAT_MOD_VIVANTE_SUPER_TILED)
 225                         val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_SUPER_TILED;
 226                 if (info->cpp[0] == 2)
 227                         val |= IPU_PRE_TPR_CTRL_TILE_FORMAT_16_BIT;
 228         }
 229         writel(val, pre->regs + IPU_PRE_TPR_CTRL);
 230
 231         val = readl(pre->regs + IPU_PRE_CTRL);
 232         val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE |
 233                IPU_PRE_CTRL_SDW_UPDATE;
 234         if (modifier == DRM_FORMAT_MOD_LINEAR)
 235                 val &= ~IPU_PRE_CTRL_BLOCK_EN;
 236         else
 237                 val |= IPU_PRE_CTRL_BLOCK_EN;
 238         writel(val, pre->regs + IPU_PRE_CTRL);
 239 }
 240
 241 void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
 242 {
 243         unsigned long timeout = jiffies + msecs_to_jiffies(5);
 244         unsigned short current_yblock;
 245         u32 val;
 246
 247         if (bufaddr == pre->last_bufaddr)
 248                 return;
 249
 250         writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
 251         pre->last_bufaddr = bufaddr;
 252
 253         do {
 254                 if (time_after(jiffies, timeout)) {
 255                         dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
 256                         return;
 257                 }
 258
 259                 val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
 260                 current_yblock =
 261                         (val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
 262                         IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
 263         } while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
 264
 265         writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
 266 }
 267
 268 u32 ipu_pre_get_baddr(struct ipu_pre *pre)
 269 {
 270         return (u32)pre->buffer_paddr;
 271 }
 272
 273 static int ipu_pre_probe(struct platform_device *pdev)
 274 {
 275         struct device *dev = &pdev->dev;
 276         struct resource *res;
 277         struct ipu_pre *pre;
 278
 279         pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL);
 280         if (!pre)
 281                 return -ENOMEM;
 282
 283         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 284         pre->regs = devm_ioremap_resource(&pdev->dev, res);
 285         if (IS_ERR(pre->regs))
 286                 return PTR_ERR(pre->regs);
 287
 288         pre->clk_axi = devm_clk_get(dev, "axi");
 289         if (IS_ERR(pre->clk_axi))
 290                 return PTR_ERR(pre->clk_axi);
 291
 292         pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0);
 293         if (!pre->iram)
 294                 return -EPROBE_DEFER;
 295
 296         /*
 297          * Allocate IRAM buffer with maximum size. This could be made dynamic,
 298          * but as there is no other user of this IRAM region and we can fit all
 299          * max sized buffers into it, there is no need yet.
 300          */
 301         pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH *
 302                                               IPU_PRE_NUM_SCANLINES * 4,
 303                                               &pre->buffer_paddr);
 304         if (!pre->buffer_virt)
 305                 return -ENOMEM;
 306
 307         clk_prepare_enable(pre->clk_axi);
 308
 309         pre->dev = dev;
 310         platform_set_drvdata(pdev, pre);
 311         mutex_lock(&ipu_pre_list_mutex);
 312         list_add(&pre->list, &ipu_pre_list);
 313         available_pres++;
 314         mutex_unlock(&ipu_pre_list_mutex);
 315
 316         return 0;
 317 }
 318
 319 static int ipu_pre_remove(struct platform_device *pdev)
 320 {
 321         struct ipu_pre *pre = platform_get_drvdata(pdev);
 322
 323         mutex_lock(&ipu_pre_list_mutex);
 324         list_del(&pre->list);
 325         available_pres--;
 326         mutex_unlock(&ipu_pre_list_mutex);
 327
 328         clk_disable_unprepare(pre->clk_axi);
 329
 330         if (pre->buffer_virt)
 331                 gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt,
 332                               IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4);
 333         return 0;
 334 }
 335
 336 static const struct of_device_id ipu_pre_dt_ids[] = {
 337         { .compatible = "fsl,imx6qp-pre", },
 338         { /* sentinel */ },
 339 };
 340
 341 struct platform_driver ipu_pre_drv = {
 342         .probe          = ipu_pre_probe,
 343         .remove         = ipu_pre_remove,
 344         .driver         = {
 345                 .name   = "imx-ipu-pre",
 346                 .of_match_table = ipu_pre_dt_ids,
 347         },
 348 };