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Linux 4.19.133
[linux/fpc-iii.git] / drivers / hwmon / nct6775.c
blob559101a1c1367a69b2d5402fcac24ff67c5f4de5
1 /*
2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
4 *
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
6 *
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
14 *
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 *
33 * Supports the following chips:
34 *
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
45 *
46 * #temp lists the number of monitored temperature sources (first value) plus
47 * the number of directly connectable temperature sensors (second value).
48 */
49
50 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51
52 #include <linux/module.h>
53 #include <linux/init.h>
54 #include <linux/slab.h>
55 #include <linux/jiffies.h>
56 #include <linux/platform_device.h>
57 #include <linux/hwmon.h>
58 #include <linux/hwmon-sysfs.h>
59 #include <linux/hwmon-vid.h>
60 #include <linux/err.h>
61 #include <linux/mutex.h>
62 #include <linux/acpi.h>
63 #include <linux/bitops.h>
64 #include <linux/dmi.h>
65 #include <linux/io.h>
66 #include <linux/nospec.h>
67 #include "lm75.h"
68
69 #define USE_ALTERNATE
70
71 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
72 nct6795, nct6796 };
73
74 /* used to set data->name = nct6775_device_names[data->sio_kind] */
75 static const char * const nct6775_device_names[] = {
76 "nct6106",
77 "nct6775",
78 "nct6776",
79 "nct6779",
80 "nct6791",
81 "nct6792",
82 "nct6793",
83 "nct6795",
84 "nct6796",
85 };
86
87 static const char * const nct6775_sio_names[] __initconst = {
88 "NCT6106D",
89 "NCT6775F",
90 "NCT6776D/F",
91 "NCT6779D",
92 "NCT6791D",
93 "NCT6792D",
94 "NCT6793D",
95 "NCT6795D",
96 "NCT6796D",
97 };
98
99 static unsigned short force_id;
100 module_param(force_id, ushort, 0);
101 MODULE_PARM_DESC(force_id, "Override the detected device ID");
102
103 static unsigned short fan_debounce;
104 module_param(fan_debounce, ushort, 0);
105 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
106
107 #define DRVNAME "nct6775"
108
109 /*
110 * Super-I/O constants and functions
111 */
112
113 #define NCT6775_LD_ACPI 0x0a
114 #define NCT6775_LD_HWM 0x0b
115 #define NCT6775_LD_VID 0x0d
116 #define NCT6775_LD_12 0x12
117
118 #define SIO_REG_LDSEL 0x07 /* Logical device select */
119 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
120 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
121 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
122
123 #define SIO_NCT6106_ID 0xc450
124 #define SIO_NCT6775_ID 0xb470
125 #define SIO_NCT6776_ID 0xc330
126 #define SIO_NCT6779_ID 0xc560
127 #define SIO_NCT6791_ID 0xc800
128 #define SIO_NCT6792_ID 0xc910
129 #define SIO_NCT6793_ID 0xd120
130 #define SIO_NCT6795_ID 0xd350
131 #define SIO_NCT6796_ID 0xd420
132 #define SIO_ID_MASK 0xFFF0
133
134 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
135
136 static inline void
137 superio_outb(int ioreg, int reg, int val)
138 {
139 outb(reg, ioreg);
140 outb(val, ioreg + 1);
141 }
142
143 static inline int
144 superio_inb(int ioreg, int reg)
145 {
146 outb(reg, ioreg);
147 return inb(ioreg + 1);
148 }
149
150 static inline void
151 superio_select(int ioreg, int ld)
152 {
153 outb(SIO_REG_LDSEL, ioreg);
154 outb(ld, ioreg + 1);
155 }
156
157 static inline int
158 superio_enter(int ioreg)
159 {
160 /*
161 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
162 */
163 if (!request_muxed_region(ioreg, 2, DRVNAME))
164 return -EBUSY;
165
166 outb(0x87, ioreg);
167 outb(0x87, ioreg);
168
169 return 0;
170 }
171
172 static inline void
173 superio_exit(int ioreg)
174 {
175 outb(0xaa, ioreg);
176 outb(0x02, ioreg);
177 outb(0x02, ioreg + 1);
178 release_region(ioreg, 2);
179 }
180
181 /*
182 * ISA constants
183 */
184
185 #define IOREGION_ALIGNMENT (~7)
186 #define IOREGION_OFFSET 5
187 #define IOREGION_LENGTH 2
188 #define ADDR_REG_OFFSET 0
189 #define DATA_REG_OFFSET 1
190
191 #define NCT6775_REG_BANK 0x4E
192 #define NCT6775_REG_CONFIG 0x40
193
194 /*
195 * Not currently used:
196 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
197 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
198 * REG_MAN_ID is at port 0x4f
199 * REG_CHIP_ID is at port 0x58
200 */
201
202 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
203 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
204
205 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
206 #define NUM_REG_BEEP 5 /* Max number of beep registers */
207
208 #define NUM_FAN 7
209
210 /* Common and NCT6775 specific data */
211
212 /* Voltage min/max registers for nr=7..14 are in bank 5 */
213
214 static const u16 NCT6775_REG_IN_MAX[] = {
215 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
216 0x55c, 0x55e, 0x560, 0x562 };
217 static const u16 NCT6775_REG_IN_MIN[] = {
218 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
219 0x55d, 0x55f, 0x561, 0x563 };
220 static const u16 NCT6775_REG_IN[] = {
221 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
222 };
223
224 #define NCT6775_REG_VBAT 0x5D
225 #define NCT6775_REG_DIODE 0x5E
226 #define NCT6775_DIODE_MASK 0x02
227
228 #define NCT6775_REG_FANDIV1 0x506
229 #define NCT6775_REG_FANDIV2 0x507
230
231 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
232
233 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
234
235 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
236
237 static const s8 NCT6775_ALARM_BITS[] = {
238 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
239 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
240 -1, /* unused */
241 6, 7, 11, -1, -1, /* fan1..fan5 */
242 -1, -1, -1, /* unused */
243 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
244 12, -1 }; /* intrusion0, intrusion1 */
245
246 #define FAN_ALARM_BASE 16
247 #define TEMP_ALARM_BASE 24
248 #define INTRUSION_ALARM_BASE 30
249
250 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
251
252 /*
253 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
254 * 30..31 intrusion
255 */
256 static const s8 NCT6775_BEEP_BITS[] = {
257 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
258 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
259 21, /* global beep enable */
260 6, 7, 11, 28, -1, /* fan1..fan5 */
261 -1, -1, -1, /* unused */
262 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
263 12, -1 }; /* intrusion0, intrusion1 */
264
265 #define BEEP_ENABLE_BASE 15
266
267 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
268 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
269
270 /* DC or PWM output fan configuration */
271 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
272 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
273
274 /* Advanced Fan control, some values are common for all fans */
275
276 static const u16 NCT6775_REG_TARGET[] = {
277 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
278 static const u16 NCT6775_REG_FAN_MODE[] = {
279 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
280 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
281 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
282 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
283 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
284 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
285 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
286 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
287 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
288 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
289 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
290
291 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
292 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
293 static const u16 NCT6775_REG_PWM[] = {
294 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
295 static const u16 NCT6775_REG_PWM_READ[] = {
296 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
297
298 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
299 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
300 static const u16 NCT6775_REG_FAN_PULSES[NUM_FAN] = {
301 0x641, 0x642, 0x643, 0x644 };
302 static const u16 NCT6775_FAN_PULSE_SHIFT[NUM_FAN] = { };
303
304 static const u16 NCT6775_REG_TEMP[] = {
305 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
306
307 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
308
309 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
310 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
311 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
312 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
313 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
314 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
315
316 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
317 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
318
319 static const u16 NCT6775_REG_TEMP_SEL[] = {
320 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
321
322 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
323 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
324 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
325 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
326 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
327 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
328 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
329 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
330 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
331 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
332
333 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
334
335 static const u16 NCT6775_REG_AUTO_TEMP[] = {
336 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
337 static const u16 NCT6775_REG_AUTO_PWM[] = {
338 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
339
340 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
341 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
342
343 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
344
345 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
346 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
347 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
348 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
349
350 static const char *const nct6775_temp_label[] = {
351 "",
352 "SYSTIN",
353 "CPUTIN",
354 "AUXTIN",
355 "AMD SB-TSI",
356 "PECI Agent 0",
357 "PECI Agent 1",
358 "PECI Agent 2",
359 "PECI Agent 3",
360 "PECI Agent 4",
361 "PECI Agent 5",
362 "PECI Agent 6",
363 "PECI Agent 7",
364 "PCH_CHIP_CPU_MAX_TEMP",
365 "PCH_CHIP_TEMP",
366 "PCH_CPU_TEMP",
367 "PCH_MCH_TEMP",
368 "PCH_DIM0_TEMP",
369 "PCH_DIM1_TEMP",
370 "PCH_DIM2_TEMP",
371 "PCH_DIM3_TEMP"
372 };
373
374 #define NCT6775_TEMP_MASK 0x001ffffe
375 #define NCT6775_VIRT_TEMP_MASK 0x00000000
376
377 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
378 [13] = 0x661,
379 [14] = 0x662,
380 [15] = 0x664,
381 };
382
383 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
384 [4] = 0xa00,
385 [5] = 0xa01,
386 [6] = 0xa02,
387 [7] = 0xa03,
388 [8] = 0xa04,
389 [9] = 0xa05,
390 [10] = 0xa06,
391 [11] = 0xa07
392 };
393
394 /* NCT6776 specific data */
395
396 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
397 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
398 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
399
400 static const s8 NCT6776_ALARM_BITS[] = {
401 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
402 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
403 -1, /* unused */
404 6, 7, 11, 10, 23, /* fan1..fan5 */
405 -1, -1, -1, /* unused */
406 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
407 12, 9 }; /* intrusion0, intrusion1 */
408
409 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
410
411 static const s8 NCT6776_BEEP_BITS[] = {
412 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
413 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
414 24, /* global beep enable */
415 25, 26, 27, 28, 29, /* fan1..fan5 */
416 -1, -1, -1, /* unused */
417 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
418 30, 31 }; /* intrusion0, intrusion1 */
419
420 static const u16 NCT6776_REG_TOLERANCE_H[] = {
421 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
422
423 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
424 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
425
426 static const u16 NCT6776_REG_FAN_MIN[] = {
427 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
428 static const u16 NCT6776_REG_FAN_PULSES[NUM_FAN] = {
429 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
430
431 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
432 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
433
434 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
435 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
436
437 static const char *const nct6776_temp_label[] = {
438 "",
439 "SYSTIN",
440 "CPUTIN",
441 "AUXTIN",
442 "SMBUSMASTER 0",
443 "SMBUSMASTER 1",
444 "SMBUSMASTER 2",
445 "SMBUSMASTER 3",
446 "SMBUSMASTER 4",
447 "SMBUSMASTER 5",
448 "SMBUSMASTER 6",
449 "SMBUSMASTER 7",
450 "PECI Agent 0",
451 "PECI Agent 1",
452 "PCH_CHIP_CPU_MAX_TEMP",
453 "PCH_CHIP_TEMP",
454 "PCH_CPU_TEMP",
455 "PCH_MCH_TEMP",
456 "PCH_DIM0_TEMP",
457 "PCH_DIM1_TEMP",
458 "PCH_DIM2_TEMP",
459 "PCH_DIM3_TEMP",
460 "BYTE_TEMP"
461 };
462
463 #define NCT6776_TEMP_MASK 0x007ffffe
464 #define NCT6776_VIRT_TEMP_MASK 0x00000000
465
466 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
467 [14] = 0x401,
468 [15] = 0x402,
469 [16] = 0x404,
470 };
471
472 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
473 [11] = 0x709,
474 [12] = 0x70a,
475 };
476
477 /* NCT6779 specific data */
478
479 static const u16 NCT6779_REG_IN[] = {
480 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
481 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
482
483 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
484 0x459, 0x45A, 0x45B, 0x568 };
485
486 static const s8 NCT6779_ALARM_BITS[] = {
487 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
488 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
489 -1, /* unused */
490 6, 7, 11, 10, 23, /* fan1..fan5 */
491 -1, -1, -1, /* unused */
492 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
493 12, 9 }; /* intrusion0, intrusion1 */
494
495 static const s8 NCT6779_BEEP_BITS[] = {
496 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
497 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
498 24, /* global beep enable */
499 25, 26, 27, 28, 29, /* fan1..fan5 */
500 -1, -1, -1, /* unused */
501 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
502 30, 31 }; /* intrusion0, intrusion1 */
503
504 static const u16 NCT6779_REG_FAN[] = {
505 0x4c0, 0x4c2, 0x4c4, 0x4c6, 0x4c8, 0x4ca, 0x4ce };
506 static const u16 NCT6779_REG_FAN_PULSES[NUM_FAN] = {
507 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
508
509 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
510 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
511 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
512 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
513 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
514
515 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
516 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
517 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
518 0x18, 0x152 };
519 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
520 0x3a, 0x153 };
521 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
522 0x39, 0x155 };
523
524 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
525 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
526
527 static const char *const nct6779_temp_label[] = {
528 "",
529 "SYSTIN",
530 "CPUTIN",
531 "AUXTIN0",
532 "AUXTIN1",
533 "AUXTIN2",
534 "AUXTIN3",
535 "",
536 "SMBUSMASTER 0",
537 "SMBUSMASTER 1",
538 "SMBUSMASTER 2",
539 "SMBUSMASTER 3",
540 "SMBUSMASTER 4",
541 "SMBUSMASTER 5",
542 "SMBUSMASTER 6",
543 "SMBUSMASTER 7",
544 "PECI Agent 0",
545 "PECI Agent 1",
546 "PCH_CHIP_CPU_MAX_TEMP",
547 "PCH_CHIP_TEMP",
548 "PCH_CPU_TEMP",
549 "PCH_MCH_TEMP",
550 "PCH_DIM0_TEMP",
551 "PCH_DIM1_TEMP",
552 "PCH_DIM2_TEMP",
553 "PCH_DIM3_TEMP",
554 "BYTE_TEMP",
555 "",
556 "",
557 "",
558 "",
559 "Virtual_TEMP"
560 };
561
562 #define NCT6779_TEMP_MASK 0x07ffff7e
563 #define NCT6779_VIRT_TEMP_MASK 0x00000000
564 #define NCT6791_TEMP_MASK 0x87ffff7e
565 #define NCT6791_VIRT_TEMP_MASK 0x80000000
566
567 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
568 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
569 0, 0, 0, 0, 0, 0, 0, 0,
570 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
571 0x408, 0 };
572
573 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
574 [15] = 0x709,
575 [16] = 0x70a,
576 };
577
578 /* NCT6791 specific data */
579
580 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
581
582 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
583 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
584 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
585 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
586 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
587 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
588
589 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
590 0x459, 0x45A, 0x45B, 0x568, 0x45D };
591
592 static const s8 NCT6791_ALARM_BITS[] = {
593 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
594 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
595 -1, /* unused */
596 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
597 -1, -1, /* unused */
598 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
599 12, 9 }; /* intrusion0, intrusion1 */
600
601 /* NCT6792/NCT6793 specific data */
602
603 static const u16 NCT6792_REG_TEMP_MON[] = {
604 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
605 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
606 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
607
608 static const char *const nct6792_temp_label[] = {
609 "",
610 "SYSTIN",
611 "CPUTIN",
612 "AUXTIN0",
613 "AUXTIN1",
614 "AUXTIN2",
615 "AUXTIN3",
616 "",
617 "SMBUSMASTER 0",
618 "SMBUSMASTER 1",
619 "SMBUSMASTER 2",
620 "SMBUSMASTER 3",
621 "SMBUSMASTER 4",
622 "SMBUSMASTER 5",
623 "SMBUSMASTER 6",
624 "SMBUSMASTER 7",
625 "PECI Agent 0",
626 "PECI Agent 1",
627 "PCH_CHIP_CPU_MAX_TEMP",
628 "PCH_CHIP_TEMP",
629 "PCH_CPU_TEMP",
630 "PCH_MCH_TEMP",
631 "PCH_DIM0_TEMP",
632 "PCH_DIM1_TEMP",
633 "PCH_DIM2_TEMP",
634 "PCH_DIM3_TEMP",
635 "BYTE_TEMP",
636 "PECI Agent 0 Calibration",
637 "PECI Agent 1 Calibration",
638 "",
639 "",
640 "Virtual_TEMP"
641 };
642
643 #define NCT6792_TEMP_MASK 0x9fffff7e
644 #define NCT6792_VIRT_TEMP_MASK 0x80000000
645
646 static const char *const nct6793_temp_label[] = {
647 "",
648 "SYSTIN",
649 "CPUTIN",
650 "AUXTIN0",
651 "AUXTIN1",
652 "AUXTIN2",
653 "AUXTIN3",
654 "",
655 "SMBUSMASTER 0",
656 "SMBUSMASTER 1",
657 "",
658 "",
659 "",
660 "",
661 "",
662 "",
663 "PECI Agent 0",
664 "PECI Agent 1",
665 "PCH_CHIP_CPU_MAX_TEMP",
666 "PCH_CHIP_TEMP",
667 "PCH_CPU_TEMP",
668 "PCH_MCH_TEMP",
669 "Agent0 Dimm0 ",
670 "Agent0 Dimm1",
671 "Agent1 Dimm0",
672 "Agent1 Dimm1",
673 "BYTE_TEMP0",
674 "BYTE_TEMP1",
675 "PECI Agent 0 Calibration",
676 "PECI Agent 1 Calibration",
677 "",
678 "Virtual_TEMP"
679 };
680
681 #define NCT6793_TEMP_MASK 0xbfff037e
682 #define NCT6793_VIRT_TEMP_MASK 0x80000000
683
684 static const char *const nct6795_temp_label[] = {
685 "",
686 "SYSTIN",
687 "CPUTIN",
688 "AUXTIN0",
689 "AUXTIN1",
690 "AUXTIN2",
691 "AUXTIN3",
692 "",
693 "SMBUSMASTER 0",
694 "SMBUSMASTER 1",
695 "SMBUSMASTER 2",
696 "SMBUSMASTER 3",
697 "SMBUSMASTER 4",
698 "SMBUSMASTER 5",
699 "SMBUSMASTER 6",
700 "SMBUSMASTER 7",
701 "PECI Agent 0",
702 "PECI Agent 1",
703 "PCH_CHIP_CPU_MAX_TEMP",
704 "PCH_CHIP_TEMP",
705 "PCH_CPU_TEMP",
706 "PCH_MCH_TEMP",
707 "Agent0 Dimm0",
708 "Agent0 Dimm1",
709 "Agent1 Dimm0",
710 "Agent1 Dimm1",
711 "BYTE_TEMP0",
712 "BYTE_TEMP1",
713 "PECI Agent 0 Calibration",
714 "PECI Agent 1 Calibration",
715 "",
716 "Virtual_TEMP"
717 };
718
719 #define NCT6795_TEMP_MASK 0xbfffff7e
720 #define NCT6795_VIRT_TEMP_MASK 0x80000000
721
722 static const char *const nct6796_temp_label[] = {
723 "",
724 "SYSTIN",
725 "CPUTIN",
726 "AUXTIN0",
727 "AUXTIN1",
728 "AUXTIN2",
729 "AUXTIN3",
730 "AUXTIN4",
731 "SMBUSMASTER 0",
732 "SMBUSMASTER 1",
733 "Virtual_TEMP",
734 "Virtual_TEMP",
735 "",
736 "",
737 "",
738 "",
739 "PECI Agent 0",
740 "PECI Agent 1",
741 "PCH_CHIP_CPU_MAX_TEMP",
742 "PCH_CHIP_TEMP",
743 "PCH_CPU_TEMP",
744 "PCH_MCH_TEMP",
745 "Agent0 Dimm0",
746 "Agent0 Dimm1",
747 "Agent1 Dimm0",
748 "Agent1 Dimm1",
749 "BYTE_TEMP0",
750 "BYTE_TEMP1",
751 "PECI Agent 0 Calibration",
752 "PECI Agent 1 Calibration",
753 "",
754 "Virtual_TEMP"
755 };
756
757 #define NCT6796_TEMP_MASK 0xbfff0ffe
758 #define NCT6796_VIRT_TEMP_MASK 0x80000c00
759
760 /* NCT6102D/NCT6106D specific data */
761
762 #define NCT6106_REG_VBAT 0x318
763 #define NCT6106_REG_DIODE 0x319
764 #define NCT6106_DIODE_MASK 0x01
765
766 static const u16 NCT6106_REG_IN_MAX[] = {
767 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
768 static const u16 NCT6106_REG_IN_MIN[] = {
769 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
770 static const u16 NCT6106_REG_IN[] = {
771 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
772
773 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
774 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
775 static const u16 NCT6106_REG_TEMP_HYST[] = {
776 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
777 static const u16 NCT6106_REG_TEMP_OVER[] = {
778 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
779 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
780 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
781 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
782 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
783 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
784 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
785 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
786
787 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
788 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
789 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6 };
790 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4 };
791
792 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
793 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
794 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
795 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
796 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
797 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
798 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
799 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
800
801 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
802 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
803 0x11b, 0x12b, 0x13b };
804
805 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
806 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
807 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
808
809 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
810 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
811 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
812 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
813 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
814 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
815
816 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
817
818 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
819 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
820 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
821 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x18b };
822 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
823 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
824
825 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
826 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
827
828 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
829 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
830
831 static const s8 NCT6106_ALARM_BITS[] = {
832 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
833 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
834 -1, /* unused */
835 32, 33, 34, -1, -1, /* fan1..fan5 */
836 -1, -1, -1, /* unused */
837 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
838 48, -1 /* intrusion0, intrusion1 */
839 };
840
841 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
842 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
843
844 static const s8 NCT6106_BEEP_BITS[] = {
845 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
846 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
847 32, /* global beep enable */
848 24, 25, 26, 27, 28, /* fan1..fan5 */
849 -1, -1, -1, /* unused */
850 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
851 34, -1 /* intrusion0, intrusion1 */
852 };
853
854 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
855 [14] = 0x51,
856 [15] = 0x52,
857 [16] = 0x54,
858 };
859
860 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
861 [11] = 0x204,
862 [12] = 0x205,
863 };
864
865 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
866 {
867 if (mode == 0 && pwm == 255)
868 return off;
869 return mode + 1;
870 }
871
872 static int pwm_enable_to_reg(enum pwm_enable mode)
873 {
874 if (mode == off)
875 return 0;
876 return mode - 1;
877 }
878
879 /*
880 * Conversions
881 */
882
883 /* 1 is DC mode, output in ms */
884 static unsigned int step_time_from_reg(u8 reg, u8 mode)
885 {
886 return mode ? 400 * reg : 100 * reg;
887 }
888
889 static u8 step_time_to_reg(unsigned int msec, u8 mode)
890 {
891 return clamp_val((mode ? (msec + 200) / 400 :
892 (msec + 50) / 100), 1, 255);
893 }
894
895 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
896 {
897 if (reg == 0 || reg == 255)
898 return 0;
899 return 1350000U / (reg << divreg);
900 }
901
902 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
903 {
904 if ((reg & 0xff1f) == 0xff1f)
905 return 0;
906
907 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
908
909 if (reg == 0)
910 return 0;
911
912 return 1350000U / reg;
913 }
914
915 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
916 {
917 if (reg == 0 || reg == 0xffff)
918 return 0;
919
920 /*
921 * Even though the registers are 16 bit wide, the fan divisor
922 * still applies.
923 */
924 return 1350000U / (reg << divreg);
925 }
926
927 static unsigned int fan_from_reg_rpm(u16 reg, unsigned int divreg)
928 {
929 return reg;
930 }
931
932 static u16 fan_to_reg(u32 fan, unsigned int divreg)
933 {
934 if (!fan)
935 return 0;
936
937 return (1350000U / fan) >> divreg;
938 }
939
940 static inline unsigned int
941 div_from_reg(u8 reg)
942 {
943 return BIT(reg);
944 }
945
946 /*
947 * Some of the voltage inputs have internal scaling, the tables below
948 * contain 8 (the ADC LSB in mV) * scaling factor * 100
949 */
950 static const u16 scale_in[15] = {
951 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
952 800, 800
953 };
954
955 static inline long in_from_reg(u8 reg, u8 nr)
956 {
957 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
958 }
959
960 static inline u8 in_to_reg(u32 val, u8 nr)
961 {
962 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
963 }
964
965 /*
966 * Data structures and manipulation thereof
967 */
968
969 struct nct6775_data {
970 int addr; /* IO base of hw monitor block */
971 int sioreg; /* SIO register address */
972 enum kinds kind;
973 const char *name;
974
975 const struct attribute_group *groups[6];
976
977 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
978 * 3=temp_crit, 4=temp_lcrit
979 */
980 u8 temp_src[NUM_TEMP];
981 u16 reg_temp_config[NUM_TEMP];
982 const char * const *temp_label;
983 u32 temp_mask;
984 u32 virt_temp_mask;
985
986 u16 REG_CONFIG;
987 u16 REG_VBAT;
988 u16 REG_DIODE;
989 u8 DIODE_MASK;
990
991 const s8 *ALARM_BITS;
992 const s8 *BEEP_BITS;
993
994 const u16 *REG_VIN;
995 const u16 *REG_IN_MINMAX[2];
996
997 const u16 *REG_TARGET;
998 const u16 *REG_FAN;
999 const u16 *REG_FAN_MODE;
1000 const u16 *REG_FAN_MIN;
1001 const u16 *REG_FAN_PULSES;
1002 const u16 *FAN_PULSE_SHIFT;
1003 const u16 *REG_FAN_TIME[3];
1004
1005 const u16 *REG_TOLERANCE_H;
1006
1007 const u8 *REG_PWM_MODE;
1008 const u8 *PWM_MODE_MASK;
1009
1010 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1011 * [3]=pwm_max, [4]=pwm_step,
1012 * [5]=weight_duty_step, [6]=weight_duty_base
1013 */
1014 const u16 *REG_PWM_READ;
1015
1016 const u16 *REG_CRITICAL_PWM_ENABLE;
1017 u8 CRITICAL_PWM_ENABLE_MASK;
1018 const u16 *REG_CRITICAL_PWM;
1019
1020 const u16 *REG_AUTO_TEMP;
1021 const u16 *REG_AUTO_PWM;
1022
1023 const u16 *REG_CRITICAL_TEMP;
1024 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1025
1026 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1027 const u16 *REG_TEMP_SEL;
1028 const u16 *REG_WEIGHT_TEMP_SEL;
1029 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1030
1031 const u16 *REG_TEMP_OFFSET;
1032
1033 const u16 *REG_ALARM;
1034 const u16 *REG_BEEP;
1035
1036 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1037 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1038
1039 struct mutex update_lock;
1040 bool valid; /* true if following fields are valid */
1041 unsigned long last_updated; /* In jiffies */
1042
1043 /* Register values */
1044 u8 bank; /* current register bank */
1045 u8 in_num; /* number of in inputs we have */
1046 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1047 unsigned int rpm[NUM_FAN];
1048 u16 fan_min[NUM_FAN];
1049 u8 fan_pulses[NUM_FAN];
1050 u8 fan_div[NUM_FAN];
1051 u8 has_pwm;
1052 u8 has_fan; /* some fan inputs can be disabled */
1053 u8 has_fan_min; /* some fans don't have min register */
1054 bool has_fan_div;
1055
1056 u8 num_temp_alarms; /* 2, 3, or 6 */
1057 u8 num_temp_beeps; /* 2, 3, or 6 */
1058 u8 temp_fixed_num; /* 3 or 6 */
1059 u8 temp_type[NUM_TEMP_FIXED];
1060 s8 temp_offset[NUM_TEMP_FIXED];
1061 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1062 * 3=temp_crit, 4=temp_lcrit */
1063 u64 alarms;
1064 u64 beeps;
1065
1066 u8 pwm_num; /* number of pwm */
1067 u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage,
1068 * 1->PWM variable duty cycle
1069 */
1070 enum pwm_enable pwm_enable[NUM_FAN];
1071 /* 0->off
1072 * 1->manual
1073 * 2->thermal cruise mode (also called SmartFan I)
1074 * 3->fan speed cruise mode
1075 * 4->SmartFan III
1076 * 5->enhanced variable thermal cruise (SmartFan IV)
1077 */
1078 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1079 * [3]=pwm_max, [4]=pwm_step,
1080 * [5]=weight_duty_step, [6]=weight_duty_base
1081 */
1082
1083 u8 target_temp[NUM_FAN];
1084 u8 target_temp_mask;
1085 u32 target_speed[NUM_FAN];
1086 u32 target_speed_tolerance[NUM_FAN];
1087 u8 speed_tolerance_limit;
1088
1089 u8 temp_tolerance[2][NUM_FAN];
1090 u8 tolerance_mask;
1091
1092 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1093
1094 /* Automatic fan speed control registers */
1095 int auto_pwm_num;
1096 u8 auto_pwm[NUM_FAN][7];
1097 u8 auto_temp[NUM_FAN][7];
1098 u8 pwm_temp_sel[NUM_FAN];
1099 u8 pwm_weight_temp_sel[NUM_FAN];
1100 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1101 * 2->temp_base
1102 */
1103
1104 u8 vid;
1105 u8 vrm;
1106
1107 bool have_vid;
1108
1109 u16 have_temp;
1110 u16 have_temp_fixed;
1111 u16 have_in;
1112
1113 /* Remember extra register values over suspend/resume */
1114 u8 vbat;
1115 u8 fandiv1;
1116 u8 fandiv2;
1117 u8 sio_reg_enable;
1118 };
1119
1120 struct nct6775_sio_data {
1121 int sioreg;
1122 enum kinds kind;
1123 };
1124
1125 struct sensor_device_template {
1126 struct device_attribute dev_attr;
1127 union {
1128 struct {
1129 u8 nr;
1130 u8 index;
1131 } s;
1132 int index;
1133 } u;
1134 bool s2; /* true if both index and nr are used */
1135 };
1136
1137 struct sensor_device_attr_u {
1138 union {
1139 struct sensor_device_attribute a1;
1140 struct sensor_device_attribute_2 a2;
1141 } u;
1142 char name[32];
1143 };
1144
1145 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1146 .attr = {.name = _template, .mode = _mode }, \
1147 .show = _show, \
1148 .store = _store, \
1149 }
1150
1151 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1152 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1153 .u.index = _index, \
1154 .s2 = false }
1155
1156 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1157 _nr, _index) \
1158 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1159 .u.s.index = _index, \
1160 .u.s.nr = _nr, \
1161 .s2 = true }
1162
1163 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1164 static struct sensor_device_template sensor_dev_template_##_name \
1165 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1166 _index)
1167
1168 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1169 _nr, _index) \
1170 static struct sensor_device_template sensor_dev_template_##_name \
1171 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1172 _nr, _index)
1173
1174 struct sensor_template_group {
1175 struct sensor_device_template **templates;
1176 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1177 int base;
1178 };
1179
1180 static struct attribute_group *
1181 nct6775_create_attr_group(struct device *dev,
1182 const struct sensor_template_group *tg,
1183 int repeat)
1184 {
1185 struct attribute_group *group;
1186 struct sensor_device_attr_u *su;
1187 struct sensor_device_attribute *a;
1188 struct sensor_device_attribute_2 *a2;
1189 struct attribute **attrs;
1190 struct sensor_device_template **t;
1191 int i, count;
1192
1193 if (repeat <= 0)
1194 return ERR_PTR(-EINVAL);
1195
1196 t = tg->templates;
1197 for (count = 0; *t; t++, count++)
1198 ;
1199
1200 if (count == 0)
1201 return ERR_PTR(-EINVAL);
1202
1203 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1204 if (group == NULL)
1205 return ERR_PTR(-ENOMEM);
1206
1207 attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1208 GFP_KERNEL);
1209 if (attrs == NULL)
1210 return ERR_PTR(-ENOMEM);
1211
1212 su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1213 GFP_KERNEL);
1214 if (su == NULL)
1215 return ERR_PTR(-ENOMEM);
1216
1217 group->attrs = attrs;
1218 group->is_visible = tg->is_visible;
1219
1220 for (i = 0; i < repeat; i++) {
1221 t = tg->templates;
1222 while (*t != NULL) {
1223 snprintf(su->name, sizeof(su->name),
1224 (*t)->dev_attr.attr.name, tg->base + i);
1225 if ((*t)->s2) {
1226 a2 = &su->u.a2;
1227 sysfs_attr_init(&a2->dev_attr.attr);
1228 a2->dev_attr.attr.name = su->name;
1229 a2->nr = (*t)->u.s.nr + i;
1230 a2->index = (*t)->u.s.index;
1231 a2->dev_attr.attr.mode =
1232 (*t)->dev_attr.attr.mode;
1233 a2->dev_attr.show = (*t)->dev_attr.show;
1234 a2->dev_attr.store = (*t)->dev_attr.store;
1235 *attrs = &a2->dev_attr.attr;
1236 } else {
1237 a = &su->u.a1;
1238 sysfs_attr_init(&a->dev_attr.attr);
1239 a->dev_attr.attr.name = su->name;
1240 a->index = (*t)->u.index + i;
1241 a->dev_attr.attr.mode =
1242 (*t)->dev_attr.attr.mode;
1243 a->dev_attr.show = (*t)->dev_attr.show;
1244 a->dev_attr.store = (*t)->dev_attr.store;
1245 *attrs = &a->dev_attr.attr;
1246 }
1247 attrs++;
1248 su++;
1249 t++;
1250 }
1251 }
1252
1253 return group;
1254 }
1255
1256 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1257 {
1258 switch (data->kind) {
1259 case nct6106:
1260 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1261 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1262 reg == 0x111 || reg == 0x121 || reg == 0x131;
1263 case nct6775:
1264 return (((reg & 0xff00) == 0x100 ||
1265 (reg & 0xff00) == 0x200) &&
1266 ((reg & 0x00ff) == 0x50 ||
1267 (reg & 0x00ff) == 0x53 ||
1268 (reg & 0x00ff) == 0x55)) ||
1269 (reg & 0xfff0) == 0x630 ||
1270 reg == 0x640 || reg == 0x642 ||
1271 reg == 0x662 ||
1272 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1273 reg == 0x73 || reg == 0x75 || reg == 0x77;
1274 case nct6776:
1275 return (((reg & 0xff00) == 0x100 ||
1276 (reg & 0xff00) == 0x200) &&
1277 ((reg & 0x00ff) == 0x50 ||
1278 (reg & 0x00ff) == 0x53 ||
1279 (reg & 0x00ff) == 0x55)) ||
1280 (reg & 0xfff0) == 0x630 ||
1281 reg == 0x402 ||
1282 reg == 0x640 || reg == 0x642 ||
1283 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1284 reg == 0x73 || reg == 0x75 || reg == 0x77;
1285 case nct6779:
1286 case nct6791:
1287 case nct6792:
1288 case nct6793:
1289 case nct6795:
1290 case nct6796:
1291 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1292 (reg & 0xfff0) == 0x4c0 ||
1293 reg == 0x402 ||
1294 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1295 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1296 reg == 0x64c ||
1297 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1298 reg == 0x7b || reg == 0x7d;
1299 }
1300 return false;
1301 }
1302
1303 /*
1304 * On older chips, only registers 0x50-0x5f are banked.
1305 * On more recent chips, all registers are banked.
1306 * Assume that is the case and set the bank number for each access.
1307 * Cache the bank number so it only needs to be set if it changes.
1308 */
1309 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1310 {
1311 u8 bank = reg >> 8;
1312
1313 if (data->bank != bank) {
1314 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1315 outb_p(bank, data->addr + DATA_REG_OFFSET);
1316 data->bank = bank;
1317 }
1318 }
1319
1320 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1321 {
1322 int res, word_sized = is_word_sized(data, reg);
1323
1324 nct6775_set_bank(data, reg);
1325 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1326 res = inb_p(data->addr + DATA_REG_OFFSET);
1327 if (word_sized) {
1328 outb_p((reg & 0xff) + 1,
1329 data->addr + ADDR_REG_OFFSET);
1330 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1331 }
1332 return res;
1333 }
1334
1335 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1336 {
1337 int word_sized = is_word_sized(data, reg);
1338
1339 nct6775_set_bank(data, reg);
1340 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1341 if (word_sized) {
1342 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1343 outb_p((reg & 0xff) + 1,
1344 data->addr + ADDR_REG_OFFSET);
1345 }
1346 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1347 return 0;
1348 }
1349
1350 /* We left-align 8-bit temperature values to make the code simpler */
1351 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1352 {
1353 u16 res;
1354
1355 res = nct6775_read_value(data, reg);
1356 if (!is_word_sized(data, reg))
1357 res <<= 8;
1358
1359 return res;
1360 }
1361
1362 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1363 {
1364 if (!is_word_sized(data, reg))
1365 value >>= 8;
1366 return nct6775_write_value(data, reg, value);
1367 }
1368
1369 /* This function assumes that the caller holds data->update_lock */
1370 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1371 {
1372 u8 reg;
1373
1374 switch (nr) {
1375 case 0:
1376 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1377 | (data->fan_div[0] & 0x7);
1378 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1379 break;
1380 case 1:
1381 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1382 | ((data->fan_div[1] << 4) & 0x70);
1383 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1384 break;
1385 case 2:
1386 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1387 | (data->fan_div[2] & 0x7);
1388 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1389 break;
1390 case 3:
1391 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1392 | ((data->fan_div[3] << 4) & 0x70);
1393 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1394 break;
1395 }
1396 }
1397
1398 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1399 {
1400 if (data->kind == nct6775)
1401 nct6775_write_fan_div(data, nr);
1402 }
1403
1404 static void nct6775_update_fan_div(struct nct6775_data *data)
1405 {
1406 u8 i;
1407
1408 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1409 data->fan_div[0] = i & 0x7;
1410 data->fan_div[1] = (i & 0x70) >> 4;
1411 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1412 data->fan_div[2] = i & 0x7;
1413 if (data->has_fan & BIT(3))
1414 data->fan_div[3] = (i & 0x70) >> 4;
1415 }
1416
1417 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1418 {
1419 if (data->kind == nct6775)
1420 nct6775_update_fan_div(data);
1421 }
1422
1423 static void nct6775_init_fan_div(struct nct6775_data *data)
1424 {
1425 int i;
1426
1427 nct6775_update_fan_div_common(data);
1428 /*
1429 * For all fans, start with highest divider value if the divider
1430 * register is not initialized. This ensures that we get a
1431 * reading from the fan count register, even if it is not optimal.
1432 * We'll compute a better divider later on.
1433 */
1434 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1435 if (!(data->has_fan & BIT(i)))
1436 continue;
1437 if (data->fan_div[i] == 0) {
1438 data->fan_div[i] = 7;
1439 nct6775_write_fan_div_common(data, i);
1440 }
1441 }
1442 }
1443
1444 static void nct6775_init_fan_common(struct device *dev,
1445 struct nct6775_data *data)
1446 {
1447 int i;
1448 u8 reg;
1449
1450 if (data->has_fan_div)
1451 nct6775_init_fan_div(data);
1452
1453 /*
1454 * If fan_min is not set (0), set it to 0xff to disable it. This
1455 * prevents the unnecessary warning when fanX_min is reported as 0.
1456 */
1457 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1458 if (data->has_fan_min & BIT(i)) {
1459 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1460 if (!reg)
1461 nct6775_write_value(data, data->REG_FAN_MIN[i],
1462 data->has_fan_div ? 0xff
1463 : 0xff1f);
1464 }
1465 }
1466 }
1467
1468 static void nct6775_select_fan_div(struct device *dev,
1469 struct nct6775_data *data, int nr, u16 reg)
1470 {
1471 u8 fan_div = data->fan_div[nr];
1472 u16 fan_min;
1473
1474 if (!data->has_fan_div)
1475 return;
1476
1477 /*
1478 * If we failed to measure the fan speed, or the reported value is not
1479 * in the optimal range, and the clock divider can be modified,
1480 * let's try that for next time.
1481 */
1482 if (reg == 0x00 && fan_div < 0x07)
1483 fan_div++;
1484 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1485 fan_div--;
1486
1487 if (fan_div != data->fan_div[nr]) {
1488 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1489 nr + 1, div_from_reg(data->fan_div[nr]),
1490 div_from_reg(fan_div));
1491
1492 /* Preserve min limit if possible */
1493 if (data->has_fan_min & BIT(nr)) {
1494 fan_min = data->fan_min[nr];
1495 if (fan_div > data->fan_div[nr]) {
1496 if (fan_min != 255 && fan_min > 1)
1497 fan_min >>= 1;
1498 } else {
1499 if (fan_min != 255) {
1500 fan_min <<= 1;
1501 if (fan_min > 254)
1502 fan_min = 254;
1503 }
1504 }
1505 if (fan_min != data->fan_min[nr]) {
1506 data->fan_min[nr] = fan_min;
1507 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1508 fan_min);
1509 }
1510 }
1511 data->fan_div[nr] = fan_div;
1512 nct6775_write_fan_div_common(data, nr);
1513 }
1514 }
1515
1516 static void nct6775_update_pwm(struct device *dev)
1517 {
1518 struct nct6775_data *data = dev_get_drvdata(dev);
1519 int i, j;
1520 int fanmodecfg, reg;
1521 bool duty_is_dc;
1522
1523 for (i = 0; i < data->pwm_num; i++) {
1524 if (!(data->has_pwm & BIT(i)))
1525 continue;
1526
1527 duty_is_dc = data->REG_PWM_MODE[i] &&
1528 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1529 & data->PWM_MODE_MASK[i]);
1530 data->pwm_mode[i] = !duty_is_dc;
1531
1532 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1533 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1534 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1535 data->pwm[j][i]
1536 = nct6775_read_value(data,
1537 data->REG_PWM[j][i]);
1538 }
1539 }
1540
1541 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1542 (fanmodecfg >> 4) & 7);
1543
1544 if (!data->temp_tolerance[0][i] ||
1545 data->pwm_enable[i] != speed_cruise)
1546 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1547 if (!data->target_speed_tolerance[i] ||
1548 data->pwm_enable[i] == speed_cruise) {
1549 u8 t = fanmodecfg & 0x0f;
1550
1551 if (data->REG_TOLERANCE_H) {
1552 t |= (nct6775_read_value(data,
1553 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1554 }
1555 data->target_speed_tolerance[i] = t;
1556 }
1557
1558 data->temp_tolerance[1][i] =
1559 nct6775_read_value(data,
1560 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1561
1562 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1563 data->pwm_temp_sel[i] = reg & 0x1f;
1564 /* If fan can stop, report floor as 0 */
1565 if (reg & 0x80)
1566 data->pwm[2][i] = 0;
1567
1568 if (!data->REG_WEIGHT_TEMP_SEL[i])
1569 continue;
1570
1571 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1572 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1573 /* If weight is disabled, report weight source as 0 */
1574 if (!(reg & 0x80))
1575 data->pwm_weight_temp_sel[i] = 0;
1576
1577 /* Weight temp data */
1578 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1579 data->weight_temp[j][i]
1580 = nct6775_read_value(data,
1581 data->REG_WEIGHT_TEMP[j][i]);
1582 }
1583 }
1584 }
1585
1586 static void nct6775_update_pwm_limits(struct device *dev)
1587 {
1588 struct nct6775_data *data = dev_get_drvdata(dev);
1589 int i, j;
1590 u8 reg;
1591 u16 reg_t;
1592
1593 for (i = 0; i < data->pwm_num; i++) {
1594 if (!(data->has_pwm & BIT(i)))
1595 continue;
1596
1597 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1598 data->fan_time[j][i] =
1599 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1600 }
1601
1602 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1603 /* Update only in matching mode or if never updated */
1604 if (!data->target_temp[i] ||
1605 data->pwm_enable[i] == thermal_cruise)
1606 data->target_temp[i] = reg_t & data->target_temp_mask;
1607 if (!data->target_speed[i] ||
1608 data->pwm_enable[i] == speed_cruise) {
1609 if (data->REG_TOLERANCE_H) {
1610 reg_t |= (nct6775_read_value(data,
1611 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1612 }
1613 data->target_speed[i] = reg_t;
1614 }
1615
1616 for (j = 0; j < data->auto_pwm_num; j++) {
1617 data->auto_pwm[i][j] =
1618 nct6775_read_value(data,
1619 NCT6775_AUTO_PWM(data, i, j));
1620 data->auto_temp[i][j] =
1621 nct6775_read_value(data,
1622 NCT6775_AUTO_TEMP(data, i, j));
1623 }
1624
1625 /* critical auto_pwm temperature data */
1626 data->auto_temp[i][data->auto_pwm_num] =
1627 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1628
1629 switch (data->kind) {
1630 case nct6775:
1631 reg = nct6775_read_value(data,
1632 NCT6775_REG_CRITICAL_ENAB[i]);
1633 data->auto_pwm[i][data->auto_pwm_num] =
1634 (reg & 0x02) ? 0xff : 0x00;
1635 break;
1636 case nct6776:
1637 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1638 break;
1639 case nct6106:
1640 case nct6779:
1641 case nct6791:
1642 case nct6792:
1643 case nct6793:
1644 case nct6795:
1645 case nct6796:
1646 reg = nct6775_read_value(data,
1647 data->REG_CRITICAL_PWM_ENABLE[i]);
1648 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1649 reg = nct6775_read_value(data,
1650 data->REG_CRITICAL_PWM[i]);
1651 else
1652 reg = 0xff;
1653 data->auto_pwm[i][data->auto_pwm_num] = reg;
1654 break;
1655 }
1656 }
1657 }
1658
1659 static struct nct6775_data *nct6775_update_device(struct device *dev)
1660 {
1661 struct nct6775_data *data = dev_get_drvdata(dev);
1662 int i, j;
1663
1664 mutex_lock(&data->update_lock);
1665
1666 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1667 || !data->valid) {
1668 /* Fan clock dividers */
1669 nct6775_update_fan_div_common(data);
1670
1671 /* Measured voltages and limits */
1672 for (i = 0; i < data->in_num; i++) {
1673 if (!(data->have_in & BIT(i)))
1674 continue;
1675
1676 data->in[i][0] = nct6775_read_value(data,
1677 data->REG_VIN[i]);
1678 data->in[i][1] = nct6775_read_value(data,
1679 data->REG_IN_MINMAX[0][i]);
1680 data->in[i][2] = nct6775_read_value(data,
1681 data->REG_IN_MINMAX[1][i]);
1682 }
1683
1684 /* Measured fan speeds and limits */
1685 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1686 u16 reg;
1687
1688 if (!(data->has_fan & BIT(i)))
1689 continue;
1690
1691 reg = nct6775_read_value(data, data->REG_FAN[i]);
1692 data->rpm[i] = data->fan_from_reg(reg,
1693 data->fan_div[i]);
1694
1695 if (data->has_fan_min & BIT(i))
1696 data->fan_min[i] = nct6775_read_value(data,
1697 data->REG_FAN_MIN[i]);
1698
1699 if (data->REG_FAN_PULSES[i]) {
1700 data->fan_pulses[i] =
1701 (nct6775_read_value(data,
1702 data->REG_FAN_PULSES[i])
1703 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1704 }
1705
1706 nct6775_select_fan_div(dev, data, i, reg);
1707 }
1708
1709 nct6775_update_pwm(dev);
1710 nct6775_update_pwm_limits(dev);
1711
1712 /* Measured temperatures and limits */
1713 for (i = 0; i < NUM_TEMP; i++) {
1714 if (!(data->have_temp & BIT(i)))
1715 continue;
1716 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1717 if (data->reg_temp[j][i])
1718 data->temp[j][i]
1719 = nct6775_read_temp(data,
1720 data->reg_temp[j][i]);
1721 }
1722 if (i >= NUM_TEMP_FIXED ||
1723 !(data->have_temp_fixed & BIT(i)))
1724 continue;
1725 data->temp_offset[i]
1726 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1727 }
1728
1729 data->alarms = 0;
1730 for (i = 0; i < NUM_REG_ALARM; i++) {
1731 u8 alarm;
1732
1733 if (!data->REG_ALARM[i])
1734 continue;
1735 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1736 data->alarms |= ((u64)alarm) << (i << 3);
1737 }
1738
1739 data->beeps = 0;
1740 for (i = 0; i < NUM_REG_BEEP; i++) {
1741 u8 beep;
1742
1743 if (!data->REG_BEEP[i])
1744 continue;
1745 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1746 data->beeps |= ((u64)beep) << (i << 3);
1747 }
1748
1749 data->last_updated = jiffies;
1750 data->valid = true;
1751 }
1752
1753 mutex_unlock(&data->update_lock);
1754 return data;
1755 }
1756
1757 /*
1758 * Sysfs callback functions
1759 */
1760 static ssize_t
1761 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1762 {
1763 struct nct6775_data *data = nct6775_update_device(dev);
1764 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1765 int index = sattr->index;
1766 int nr = sattr->nr;
1767
1768 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1769 }
1770
1771 static ssize_t
1772 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1773 size_t count)
1774 {
1775 struct nct6775_data *data = dev_get_drvdata(dev);
1776 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1777 int index = sattr->index;
1778 int nr = sattr->nr;
1779 unsigned long val;
1780 int err;
1781
1782 err = kstrtoul(buf, 10, &val);
1783 if (err < 0)
1784 return err;
1785 mutex_lock(&data->update_lock);
1786 data->in[nr][index] = in_to_reg(val, nr);
1787 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1788 data->in[nr][index]);
1789 mutex_unlock(&data->update_lock);
1790 return count;
1791 }
1792
1793 static ssize_t
1794 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1795 {
1796 struct nct6775_data *data = nct6775_update_device(dev);
1797 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1798 int nr = data->ALARM_BITS[sattr->index];
1799
1800 return sprintf(buf, "%u\n",
1801 (unsigned int)((data->alarms >> nr) & 0x01));
1802 }
1803
1804 static int find_temp_source(struct nct6775_data *data, int index, int count)
1805 {
1806 int source = data->temp_src[index];
1807 int nr;
1808
1809 for (nr = 0; nr < count; nr++) {
1810 int src;
1811
1812 src = nct6775_read_value(data,
1813 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1814 if (src == source)
1815 return nr;
1816 }
1817 return -ENODEV;
1818 }
1819
1820 static ssize_t
1821 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1822 {
1823 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1824 struct nct6775_data *data = nct6775_update_device(dev);
1825 unsigned int alarm = 0;
1826 int nr;
1827
1828 /*
1829 * For temperatures, there is no fixed mapping from registers to alarm
1830 * bits. Alarm bits are determined by the temperature source mapping.
1831 */
1832 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1833 if (nr >= 0) {
1834 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1835
1836 alarm = (data->alarms >> bit) & 0x01;
1837 }
1838 return sprintf(buf, "%u\n", alarm);
1839 }
1840
1841 static ssize_t
1842 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1843 {
1844 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1845 struct nct6775_data *data = nct6775_update_device(dev);
1846 int nr = data->BEEP_BITS[sattr->index];
1847
1848 return sprintf(buf, "%u\n",
1849 (unsigned int)((data->beeps >> nr) & 0x01));
1850 }
1851
1852 static ssize_t
1853 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1854 size_t count)
1855 {
1856 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1857 struct nct6775_data *data = dev_get_drvdata(dev);
1858 int nr = data->BEEP_BITS[sattr->index];
1859 int regindex = nr >> 3;
1860 unsigned long val;
1861 int err;
1862
1863 err = kstrtoul(buf, 10, &val);
1864 if (err < 0)
1865 return err;
1866 if (val > 1)
1867 return -EINVAL;
1868
1869 mutex_lock(&data->update_lock);
1870 if (val)
1871 data->beeps |= (1ULL << nr);
1872 else
1873 data->beeps &= ~(1ULL << nr);
1874 nct6775_write_value(data, data->REG_BEEP[regindex],
1875 (data->beeps >> (regindex << 3)) & 0xff);
1876 mutex_unlock(&data->update_lock);
1877 return count;
1878 }
1879
1880 static ssize_t
1881 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1882 {
1883 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1884 struct nct6775_data *data = nct6775_update_device(dev);
1885 unsigned int beep = 0;
1886 int nr;
1887
1888 /*
1889 * For temperatures, there is no fixed mapping from registers to beep
1890 * enable bits. Beep enable bits are determined by the temperature
1891 * source mapping.
1892 */
1893 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1894 if (nr >= 0) {
1895 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1896
1897 beep = (data->beeps >> bit) & 0x01;
1898 }
1899 return sprintf(buf, "%u\n", beep);
1900 }
1901
1902 static ssize_t
1903 store_temp_beep(struct device *dev, struct device_attribute *attr,
1904 const char *buf, size_t count)
1905 {
1906 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1907 struct nct6775_data *data = dev_get_drvdata(dev);
1908 int nr, bit, regindex;
1909 unsigned long val;
1910 int err;
1911
1912 err = kstrtoul(buf, 10, &val);
1913 if (err < 0)
1914 return err;
1915 if (val > 1)
1916 return -EINVAL;
1917
1918 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1919 if (nr < 0)
1920 return nr;
1921
1922 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1923 regindex = bit >> 3;
1924
1925 mutex_lock(&data->update_lock);
1926 if (val)
1927 data->beeps |= (1ULL << bit);
1928 else
1929 data->beeps &= ~(1ULL << bit);
1930 nct6775_write_value(data, data->REG_BEEP[regindex],
1931 (data->beeps >> (regindex << 3)) & 0xff);
1932 mutex_unlock(&data->update_lock);
1933
1934 return count;
1935 }
1936
1937 static umode_t nct6775_in_is_visible(struct kobject *kobj,
1938 struct attribute *attr, int index)
1939 {
1940 struct device *dev = container_of(kobj, struct device, kobj);
1941 struct nct6775_data *data = dev_get_drvdata(dev);
1942 int in = index / 5; /* voltage index */
1943
1944 if (!(data->have_in & BIT(in)))
1945 return 0;
1946
1947 return attr->mode;
1948 }
1949
1950 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
1951 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
1952 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
1953 0);
1954 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
1955 store_in_reg, 0, 1);
1956 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
1957 store_in_reg, 0, 2);
1958
1959 /*
1960 * nct6775_in_is_visible uses the index into the following array
1961 * to determine if attributes should be created or not.
1962 * Any change in order or content must be matched.
1963 */
1964 static struct sensor_device_template *nct6775_attributes_in_template[] = {
1965 &sensor_dev_template_in_input,
1966 &sensor_dev_template_in_alarm,
1967 &sensor_dev_template_in_beep,
1968 &sensor_dev_template_in_min,
1969 &sensor_dev_template_in_max,
1970 NULL
1971 };
1972
1973 static const struct sensor_template_group nct6775_in_template_group = {
1974 .templates = nct6775_attributes_in_template,
1975 .is_visible = nct6775_in_is_visible,
1976 };
1977
1978 static ssize_t
1979 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
1980 {
1981 struct nct6775_data *data = nct6775_update_device(dev);
1982 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1983 int nr = sattr->index;
1984
1985 return sprintf(buf, "%d\n", data->rpm[nr]);
1986 }
1987
1988 static ssize_t
1989 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
1990 {
1991 struct nct6775_data *data = nct6775_update_device(dev);
1992 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1993 int nr = sattr->index;
1994
1995 return sprintf(buf, "%d\n",
1996 data->fan_from_reg_min(data->fan_min[nr],
1997 data->fan_div[nr]));
1998 }
1999
2000 static ssize_t
2001 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
2002 {
2003 struct nct6775_data *data = nct6775_update_device(dev);
2004 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2005 int nr = sattr->index;
2006
2007 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
2008 }
2009
2010 static ssize_t
2011 store_fan_min(struct device *dev, struct device_attribute *attr,
2012 const char *buf, size_t count)
2013 {
2014 struct nct6775_data *data = dev_get_drvdata(dev);
2015 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2016 int nr = sattr->index;
2017 unsigned long val;
2018 unsigned int reg;
2019 u8 new_div;
2020 int err;
2021
2022 err = kstrtoul(buf, 10, &val);
2023 if (err < 0)
2024 return err;
2025
2026 mutex_lock(&data->update_lock);
2027 if (!data->has_fan_div) {
2028 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2029 if (!val) {
2030 val = 0xff1f;
2031 } else {
2032 if (val > 1350000U)
2033 val = 135000U;
2034 val = 1350000U / val;
2035 val = (val & 0x1f) | ((val << 3) & 0xff00);
2036 }
2037 data->fan_min[nr] = val;
2038 goto write_min; /* Leave fan divider alone */
2039 }
2040 if (!val) {
2041 /* No min limit, alarm disabled */
2042 data->fan_min[nr] = 255;
2043 new_div = data->fan_div[nr]; /* No change */
2044 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2045 goto write_div;
2046 }
2047 reg = 1350000U / val;
2048 if (reg >= 128 * 255) {
2049 /*
2050 * Speed below this value cannot possibly be represented,
2051 * even with the highest divider (128)
2052 */
2053 data->fan_min[nr] = 254;
2054 new_div = 7; /* 128 == BIT(7) */
2055 dev_warn(dev,
2056 "fan%u low limit %lu below minimum %u, set to minimum\n",
2057 nr + 1, val, data->fan_from_reg_min(254, 7));
2058 } else if (!reg) {
2059 /*
2060 * Speed above this value cannot possibly be represented,
2061 * even with the lowest divider (1)
2062 */
2063 data->fan_min[nr] = 1;
2064 new_div = 0; /* 1 == BIT(0) */
2065 dev_warn(dev,
2066 "fan%u low limit %lu above maximum %u, set to maximum\n",
2067 nr + 1, val, data->fan_from_reg_min(1, 0));
2068 } else {
2069 /*
2070 * Automatically pick the best divider, i.e. the one such
2071 * that the min limit will correspond to a register value
2072 * in the 96..192 range
2073 */
2074 new_div = 0;
2075 while (reg > 192 && new_div < 7) {
2076 reg >>= 1;
2077 new_div++;
2078 }
2079 data->fan_min[nr] = reg;
2080 }
2081
2082 write_div:
2083 /*
2084 * Write both the fan clock divider (if it changed) and the new
2085 * fan min (unconditionally)
2086 */
2087 if (new_div != data->fan_div[nr]) {
2088 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2089 nr + 1, div_from_reg(data->fan_div[nr]),
2090 div_from_reg(new_div));
2091 data->fan_div[nr] = new_div;
2092 nct6775_write_fan_div_common(data, nr);
2093 /* Give the chip time to sample a new speed value */
2094 data->last_updated = jiffies;
2095 }
2096
2097 write_min:
2098 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2099 mutex_unlock(&data->update_lock);
2100
2101 return count;
2102 }
2103
2104 static ssize_t
2105 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2106 {
2107 struct nct6775_data *data = nct6775_update_device(dev);
2108 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2109 int p = data->fan_pulses[sattr->index];
2110
2111 return sprintf(buf, "%d\n", p ? : 4);
2112 }
2113
2114 static ssize_t
2115 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2116 const char *buf, size_t count)
2117 {
2118 struct nct6775_data *data = dev_get_drvdata(dev);
2119 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2120 int nr = sattr->index;
2121 unsigned long val;
2122 int err;
2123 u8 reg;
2124
2125 err = kstrtoul(buf, 10, &val);
2126 if (err < 0)
2127 return err;
2128
2129 if (val > 4)
2130 return -EINVAL;
2131
2132 mutex_lock(&data->update_lock);
2133 data->fan_pulses[nr] = val & 3;
2134 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2135 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2136 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2137 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2138 mutex_unlock(&data->update_lock);
2139
2140 return count;
2141 }
2142
2143 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2144 struct attribute *attr, int index)
2145 {
2146 struct device *dev = container_of(kobj, struct device, kobj);
2147 struct nct6775_data *data = dev_get_drvdata(dev);
2148 int fan = index / 6; /* fan index */
2149 int nr = index % 6; /* attribute index */
2150
2151 if (!(data->has_fan & BIT(fan)))
2152 return 0;
2153
2154 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2155 return 0;
2156 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2157 return 0;
2158 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2159 return 0;
2160 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2161 return 0;
2162 if (nr == 5 && data->kind != nct6775)
2163 return 0;
2164
2165 return attr->mode;
2166 }
2167
2168 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2169 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2170 FAN_ALARM_BASE);
2171 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2172 store_beep, FAN_ALARM_BASE);
2173 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2174 store_fan_pulses, 0);
2175 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2176 store_fan_min, 0);
2177 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2178
2179 /*
2180 * nct6775_fan_is_visible uses the index into the following array
2181 * to determine if attributes should be created or not.
2182 * Any change in order or content must be matched.
2183 */
2184 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2185 &sensor_dev_template_fan_input,
2186 &sensor_dev_template_fan_alarm, /* 1 */
2187 &sensor_dev_template_fan_beep, /* 2 */
2188 &sensor_dev_template_fan_pulses,
2189 &sensor_dev_template_fan_min, /* 4 */
2190 &sensor_dev_template_fan_div, /* 5 */
2191 NULL
2192 };
2193
2194 static const struct sensor_template_group nct6775_fan_template_group = {
2195 .templates = nct6775_attributes_fan_template,
2196 .is_visible = nct6775_fan_is_visible,
2197 .base = 1,
2198 };
2199
2200 static ssize_t
2201 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2202 {
2203 struct nct6775_data *data = nct6775_update_device(dev);
2204 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2205 int nr = sattr->index;
2206
2207 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2208 }
2209
2210 static ssize_t
2211 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2212 {
2213 struct nct6775_data *data = nct6775_update_device(dev);
2214 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2215 int nr = sattr->nr;
2216 int index = sattr->index;
2217
2218 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2219 }
2220
2221 static ssize_t
2222 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2223 size_t count)
2224 {
2225 struct nct6775_data *data = dev_get_drvdata(dev);
2226 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2227 int nr = sattr->nr;
2228 int index = sattr->index;
2229 int err;
2230 long val;
2231
2232 err = kstrtol(buf, 10, &val);
2233 if (err < 0)
2234 return err;
2235
2236 mutex_lock(&data->update_lock);
2237 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2238 nct6775_write_temp(data, data->reg_temp[index][nr],
2239 data->temp[index][nr]);
2240 mutex_unlock(&data->update_lock);
2241 return count;
2242 }
2243
2244 static ssize_t
2245 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2246 {
2247 struct nct6775_data *data = nct6775_update_device(dev);
2248 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2249
2250 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2251 }
2252
2253 static ssize_t
2254 store_temp_offset(struct device *dev, struct device_attribute *attr,
2255 const char *buf, size_t count)
2256 {
2257 struct nct6775_data *data = dev_get_drvdata(dev);
2258 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2259 int nr = sattr->index;
2260 long val;
2261 int err;
2262
2263 err = kstrtol(buf, 10, &val);
2264 if (err < 0)
2265 return err;
2266
2267 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2268
2269 mutex_lock(&data->update_lock);
2270 data->temp_offset[nr] = val;
2271 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2272 mutex_unlock(&data->update_lock);
2273
2274 return count;
2275 }
2276
2277 static ssize_t
2278 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2279 {
2280 struct nct6775_data *data = nct6775_update_device(dev);
2281 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2282 int nr = sattr->index;
2283
2284 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2285 }
2286
2287 static ssize_t
2288 store_temp_type(struct device *dev, struct device_attribute *attr,
2289 const char *buf, size_t count)
2290 {
2291 struct nct6775_data *data = nct6775_update_device(dev);
2292 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2293 int nr = sattr->index;
2294 unsigned long val;
2295 int err;
2296 u8 vbat, diode, vbit, dbit;
2297
2298 err = kstrtoul(buf, 10, &val);
2299 if (err < 0)
2300 return err;
2301
2302 if (val != 1 && val != 3 && val != 4)
2303 return -EINVAL;
2304
2305 mutex_lock(&data->update_lock);
2306
2307 data->temp_type[nr] = val;
2308 vbit = 0x02 << nr;
2309 dbit = data->DIODE_MASK << nr;
2310 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2311 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2312 switch (val) {
2313 case 1: /* CPU diode (diode, current mode) */
2314 vbat |= vbit;
2315 diode |= dbit;
2316 break;
2317 case 3: /* diode, voltage mode */
2318 vbat |= dbit;
2319 break;
2320 case 4: /* thermistor */
2321 break;
2322 }
2323 nct6775_write_value(data, data->REG_VBAT, vbat);
2324 nct6775_write_value(data, data->REG_DIODE, diode);
2325
2326 mutex_unlock(&data->update_lock);
2327 return count;
2328 }
2329
2330 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2331 struct attribute *attr, int index)
2332 {
2333 struct device *dev = container_of(kobj, struct device, kobj);
2334 struct nct6775_data *data = dev_get_drvdata(dev);
2335 int temp = index / 10; /* temp index */
2336 int nr = index % 10; /* attribute index */
2337
2338 if (!(data->have_temp & BIT(temp)))
2339 return 0;
2340
2341 if (nr == 1 && !data->temp_label)
2342 return 0;
2343
2344 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2345 return 0; /* alarm */
2346
2347 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2348 return 0; /* beep */
2349
2350 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2351 return 0;
2352
2353 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2354 return 0;
2355
2356 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2357 return 0;
2358
2359 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2360 return 0;
2361
2362 /* offset and type only apply to fixed sensors */
2363 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2364 return 0;
2365
2366 return attr->mode;
2367 }
2368
2369 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2370 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2371 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2372 store_temp, 0, 1);
2373 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2374 show_temp, store_temp, 0, 2);
2375 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2376 store_temp, 0, 3);
2377 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2378 store_temp, 0, 4);
2379 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2380 show_temp_offset, store_temp_offset, 0);
2381 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2382 store_temp_type, 0);
2383 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2384 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2385 store_temp_beep, 0);
2386
2387 /*
2388 * nct6775_temp_is_visible uses the index into the following array
2389 * to determine if attributes should be created or not.
2390 * Any change in order or content must be matched.
2391 */
2392 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2393 &sensor_dev_template_temp_input,
2394 &sensor_dev_template_temp_label,
2395 &sensor_dev_template_temp_alarm, /* 2 */
2396 &sensor_dev_template_temp_beep, /* 3 */
2397 &sensor_dev_template_temp_max, /* 4 */
2398 &sensor_dev_template_temp_max_hyst, /* 5 */
2399 &sensor_dev_template_temp_crit, /* 6 */
2400 &sensor_dev_template_temp_lcrit, /* 7 */
2401 &sensor_dev_template_temp_offset, /* 8 */
2402 &sensor_dev_template_temp_type, /* 9 */
2403 NULL
2404 };
2405
2406 static const struct sensor_template_group nct6775_temp_template_group = {
2407 .templates = nct6775_attributes_temp_template,
2408 .is_visible = nct6775_temp_is_visible,
2409 .base = 1,
2410 };
2411
2412 static ssize_t
2413 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2414 {
2415 struct nct6775_data *data = nct6775_update_device(dev);
2416 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2417
2418 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2419 }
2420
2421 static ssize_t
2422 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2423 const char *buf, size_t count)
2424 {
2425 struct nct6775_data *data = dev_get_drvdata(dev);
2426 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2427 int nr = sattr->index;
2428 unsigned long val;
2429 int err;
2430 u8 reg;
2431
2432 err = kstrtoul(buf, 10, &val);
2433 if (err < 0)
2434 return err;
2435
2436 if (val > 1)
2437 return -EINVAL;
2438
2439 /* Setting DC mode (0) is not supported for all chips/channels */
2440 if (data->REG_PWM_MODE[nr] == 0) {
2441 if (!val)
2442 return -EINVAL;
2443 return count;
2444 }
2445
2446 mutex_lock(&data->update_lock);
2447 data->pwm_mode[nr] = val;
2448 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2449 reg &= ~data->PWM_MODE_MASK[nr];
2450 if (!val)
2451 reg |= data->PWM_MODE_MASK[nr];
2452 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2453 mutex_unlock(&data->update_lock);
2454 return count;
2455 }
2456
2457 static ssize_t
2458 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2459 {
2460 struct nct6775_data *data = nct6775_update_device(dev);
2461 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2462 int nr = sattr->nr;
2463 int index = sattr->index;
2464 int pwm;
2465
2466 /*
2467 * For automatic fan control modes, show current pwm readings.
2468 * Otherwise, show the configured value.
2469 */
2470 if (index == 0 && data->pwm_enable[nr] > manual)
2471 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2472 else
2473 pwm = data->pwm[index][nr];
2474
2475 return sprintf(buf, "%d\n", pwm);
2476 }
2477
2478 static ssize_t
2479 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2480 size_t count)
2481 {
2482 struct nct6775_data *data = dev_get_drvdata(dev);
2483 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2484 int nr = sattr->nr;
2485 int index = sattr->index;
2486 unsigned long val;
2487 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2488 int maxval[7]
2489 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2490 int err;
2491 u8 reg;
2492
2493 err = kstrtoul(buf, 10, &val);
2494 if (err < 0)
2495 return err;
2496 val = clamp_val(val, minval[index], maxval[index]);
2497
2498 mutex_lock(&data->update_lock);
2499 data->pwm[index][nr] = val;
2500 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2501 if (index == 2) { /* floor: disable if val == 0 */
2502 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2503 reg &= 0x7f;
2504 if (val)
2505 reg |= 0x80;
2506 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2507 }
2508 mutex_unlock(&data->update_lock);
2509 return count;
2510 }
2511
2512 /* Returns 0 if OK, -EINVAL otherwise */
2513 static int check_trip_points(struct nct6775_data *data, int nr)
2514 {
2515 int i;
2516
2517 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2518 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2519 return -EINVAL;
2520 }
2521 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2522 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2523 return -EINVAL;
2524 }
2525 /* validate critical temperature and pwm if enabled (pwm > 0) */
2526 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2527 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2528 data->auto_temp[nr][data->auto_pwm_num] ||
2529 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2530 data->auto_pwm[nr][data->auto_pwm_num])
2531 return -EINVAL;
2532 }
2533 return 0;
2534 }
2535
2536 static void pwm_update_registers(struct nct6775_data *data, int nr)
2537 {
2538 u8 reg;
2539
2540 switch (data->pwm_enable[nr]) {
2541 case off:
2542 case manual:
2543 break;
2544 case speed_cruise:
2545 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2546 reg = (reg & ~data->tolerance_mask) |
2547 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2548 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2549 nct6775_write_value(data, data->REG_TARGET[nr],
2550 data->target_speed[nr] & 0xff);
2551 if (data->REG_TOLERANCE_H) {
2552 reg = (data->target_speed[nr] >> 8) & 0x0f;
2553 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2554 nct6775_write_value(data,
2555 data->REG_TOLERANCE_H[nr],
2556 reg);
2557 }
2558 break;
2559 case thermal_cruise:
2560 nct6775_write_value(data, data->REG_TARGET[nr],
2561 data->target_temp[nr]);
2562 /* fall through */
2563 default:
2564 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2565 reg = (reg & ~data->tolerance_mask) |
2566 data->temp_tolerance[0][nr];
2567 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2568 break;
2569 }
2570 }
2571
2572 static ssize_t
2573 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2574 {
2575 struct nct6775_data *data = nct6775_update_device(dev);
2576 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2577
2578 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2579 }
2580
2581 static ssize_t
2582 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2583 const char *buf, size_t count)
2584 {
2585 struct nct6775_data *data = dev_get_drvdata(dev);
2586 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2587 int nr = sattr->index;
2588 unsigned long val;
2589 int err;
2590 u16 reg;
2591
2592 err = kstrtoul(buf, 10, &val);
2593 if (err < 0)
2594 return err;
2595
2596 if (val > sf4)
2597 return -EINVAL;
2598
2599 if (val == sf3 && data->kind != nct6775)
2600 return -EINVAL;
2601
2602 if (val == sf4 && check_trip_points(data, nr)) {
2603 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2604 dev_err(dev, "Adjust trip points and try again\n");
2605 return -EINVAL;
2606 }
2607
2608 mutex_lock(&data->update_lock);
2609 data->pwm_enable[nr] = val;
2610 if (val == off) {
2611 /*
2612 * turn off pwm control: select manual mode, set pwm to maximum
2613 */
2614 data->pwm[0][nr] = 255;
2615 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2616 }
2617 pwm_update_registers(data, nr);
2618 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2619 reg &= 0x0f;
2620 reg |= pwm_enable_to_reg(val) << 4;
2621 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2622 mutex_unlock(&data->update_lock);
2623 return count;
2624 }
2625
2626 static ssize_t
2627 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2628 {
2629 int i, sel = 0;
2630
2631 for (i = 0; i < NUM_TEMP; i++) {
2632 if (!(data->have_temp & BIT(i)))
2633 continue;
2634 if (src == data->temp_src[i]) {
2635 sel = i + 1;
2636 break;
2637 }
2638 }
2639
2640 return sprintf(buf, "%d\n", sel);
2641 }
2642
2643 static ssize_t
2644 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2645 {
2646 struct nct6775_data *data = nct6775_update_device(dev);
2647 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2648 int index = sattr->index;
2649
2650 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2651 }
2652
2653 static ssize_t
2654 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2655 const char *buf, size_t count)
2656 {
2657 struct nct6775_data *data = nct6775_update_device(dev);
2658 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2659 int nr = sattr->index;
2660 unsigned long val;
2661 int err, reg, src;
2662
2663 err = kstrtoul(buf, 10, &val);
2664 if (err < 0)
2665 return err;
2666 if (val == 0 || val > NUM_TEMP)
2667 return -EINVAL;
2668 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2669 return -EINVAL;
2670
2671 mutex_lock(&data->update_lock);
2672 src = data->temp_src[val - 1];
2673 data->pwm_temp_sel[nr] = src;
2674 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2675 reg &= 0xe0;
2676 reg |= src;
2677 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2678 mutex_unlock(&data->update_lock);
2679
2680 return count;
2681 }
2682
2683 static ssize_t
2684 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2685 char *buf)
2686 {
2687 struct nct6775_data *data = nct6775_update_device(dev);
2688 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2689 int index = sattr->index;
2690
2691 return show_pwm_temp_sel_common(data, buf,
2692 data->pwm_weight_temp_sel[index]);
2693 }
2694
2695 static ssize_t
2696 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2697 const char *buf, size_t count)
2698 {
2699 struct nct6775_data *data = nct6775_update_device(dev);
2700 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2701 int nr = sattr->index;
2702 unsigned long val;
2703 int err, reg, src;
2704
2705 err = kstrtoul(buf, 10, &val);
2706 if (err < 0)
2707 return err;
2708 if (val > NUM_TEMP)
2709 return -EINVAL;
2710 val = array_index_nospec(val, NUM_TEMP + 1);
2711 if (val && (!(data->have_temp & BIT(val - 1)) ||
2712 !data->temp_src[val - 1]))
2713 return -EINVAL;
2714
2715 mutex_lock(&data->update_lock);
2716 if (val) {
2717 src = data->temp_src[val - 1];
2718 data->pwm_weight_temp_sel[nr] = src;
2719 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2720 reg &= 0xe0;
2721 reg |= (src | 0x80);
2722 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2723 } else {
2724 data->pwm_weight_temp_sel[nr] = 0;
2725 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2726 reg &= 0x7f;
2727 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2728 }
2729 mutex_unlock(&data->update_lock);
2730
2731 return count;
2732 }
2733
2734 static ssize_t
2735 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2736 {
2737 struct nct6775_data *data = nct6775_update_device(dev);
2738 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2739
2740 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2741 }
2742
2743 static ssize_t
2744 store_target_temp(struct device *dev, struct device_attribute *attr,
2745 const char *buf, size_t count)
2746 {
2747 struct nct6775_data *data = dev_get_drvdata(dev);
2748 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2749 int nr = sattr->index;
2750 unsigned long val;
2751 int err;
2752
2753 err = kstrtoul(buf, 10, &val);
2754 if (err < 0)
2755 return err;
2756
2757 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2758 data->target_temp_mask);
2759
2760 mutex_lock(&data->update_lock);
2761 data->target_temp[nr] = val;
2762 pwm_update_registers(data, nr);
2763 mutex_unlock(&data->update_lock);
2764 return count;
2765 }
2766
2767 static ssize_t
2768 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2769 {
2770 struct nct6775_data *data = nct6775_update_device(dev);
2771 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2772 int nr = sattr->index;
2773
2774 return sprintf(buf, "%d\n",
2775 fan_from_reg16(data->target_speed[nr],
2776 data->fan_div[nr]));
2777 }
2778
2779 static ssize_t
2780 store_target_speed(struct device *dev, struct device_attribute *attr,
2781 const char *buf, size_t count)
2782 {
2783 struct nct6775_data *data = dev_get_drvdata(dev);
2784 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2785 int nr = sattr->index;
2786 unsigned long val;
2787 int err;
2788 u16 speed;
2789
2790 err = kstrtoul(buf, 10, &val);
2791 if (err < 0)
2792 return err;
2793
2794 val = clamp_val(val, 0, 1350000U);
2795 speed = fan_to_reg(val, data->fan_div[nr]);
2796
2797 mutex_lock(&data->update_lock);
2798 data->target_speed[nr] = speed;
2799 pwm_update_registers(data, nr);
2800 mutex_unlock(&data->update_lock);
2801 return count;
2802 }
2803
2804 static ssize_t
2805 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2806 char *buf)
2807 {
2808 struct nct6775_data *data = nct6775_update_device(dev);
2809 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2810 int nr = sattr->nr;
2811 int index = sattr->index;
2812
2813 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2814 }
2815
2816 static ssize_t
2817 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2818 const char *buf, size_t count)
2819 {
2820 struct nct6775_data *data = dev_get_drvdata(dev);
2821 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2822 int nr = sattr->nr;
2823 int index = sattr->index;
2824 unsigned long val;
2825 int err;
2826
2827 err = kstrtoul(buf, 10, &val);
2828 if (err < 0)
2829 return err;
2830
2831 /* Limit tolerance as needed */
2832 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2833
2834 mutex_lock(&data->update_lock);
2835 data->temp_tolerance[index][nr] = val;
2836 if (index)
2837 pwm_update_registers(data, nr);
2838 else
2839 nct6775_write_value(data,
2840 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2841 val);
2842 mutex_unlock(&data->update_lock);
2843 return count;
2844 }
2845
2846 /*
2847 * Fan speed tolerance is a tricky beast, since the associated register is
2848 * a tick counter, but the value is reported and configured as rpm.
2849 * Compute resulting low and high rpm values and report the difference.
2850 */
2851 static ssize_t
2852 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2853 char *buf)
2854 {
2855 struct nct6775_data *data = nct6775_update_device(dev);
2856 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2857 int nr = sattr->index;
2858 int low = data->target_speed[nr] - data->target_speed_tolerance[nr];
2859 int high = data->target_speed[nr] + data->target_speed_tolerance[nr];
2860 int tolerance;
2861
2862 if (low <= 0)
2863 low = 1;
2864 if (high > 0xffff)
2865 high = 0xffff;
2866 if (high < low)
2867 high = low;
2868
2869 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2870 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2871
2872 return sprintf(buf, "%d\n", tolerance);
2873 }
2874
2875 static ssize_t
2876 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2877 const char *buf, size_t count)
2878 {
2879 struct nct6775_data *data = dev_get_drvdata(dev);
2880 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2881 int nr = sattr->index;
2882 unsigned long val;
2883 int err;
2884 int low, high;
2885
2886 err = kstrtoul(buf, 10, &val);
2887 if (err < 0)
2888 return err;
2889
2890 high = fan_from_reg16(data->target_speed[nr],
2891 data->fan_div[nr]) + val;
2892 low = fan_from_reg16(data->target_speed[nr],
2893 data->fan_div[nr]) - val;
2894 if (low <= 0)
2895 low = 1;
2896 if (high < low)
2897 high = low;
2898
2899 val = (fan_to_reg(low, data->fan_div[nr]) -
2900 fan_to_reg(high, data->fan_div[nr])) / 2;
2901
2902 /* Limit tolerance as needed */
2903 val = clamp_val(val, 0, data->speed_tolerance_limit);
2904
2905 mutex_lock(&data->update_lock);
2906 data->target_speed_tolerance[nr] = val;
2907 pwm_update_registers(data, nr);
2908 mutex_unlock(&data->update_lock);
2909 return count;
2910 }
2911
2912 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2913 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2914 store_pwm_mode, 0);
2915 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2916 store_pwm_enable, 0);
2917 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2918 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2919 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2920 show_target_temp, store_target_temp, 0);
2921 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2922 show_target_speed, store_target_speed, 0);
2923 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2924 show_speed_tolerance, store_speed_tolerance, 0);
2925
2926 /* Smart Fan registers */
2927
2928 static ssize_t
2929 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2930 {
2931 struct nct6775_data *data = nct6775_update_device(dev);
2932 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2933 int nr = sattr->nr;
2934 int index = sattr->index;
2935
2936 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2937 }
2938
2939 static ssize_t
2940 store_weight_temp(struct device *dev, struct device_attribute *attr,
2941 const char *buf, size_t count)
2942 {
2943 struct nct6775_data *data = dev_get_drvdata(dev);
2944 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2945 int nr = sattr->nr;
2946 int index = sattr->index;
2947 unsigned long val;
2948 int err;
2949
2950 err = kstrtoul(buf, 10, &val);
2951 if (err < 0)
2952 return err;
2953
2954 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
2955
2956 mutex_lock(&data->update_lock);
2957 data->weight_temp[index][nr] = val;
2958 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
2959 mutex_unlock(&data->update_lock);
2960 return count;
2961 }
2962
2963 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
2964 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
2965 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
2966 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
2967 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
2968 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
2969 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
2970 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
2971 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
2972 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
2973 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
2974 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
2975
2976 static ssize_t
2977 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
2978 {
2979 struct nct6775_data *data = nct6775_update_device(dev);
2980 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2981 int nr = sattr->nr;
2982 int index = sattr->index;
2983
2984 return sprintf(buf, "%d\n",
2985 step_time_from_reg(data->fan_time[index][nr],
2986 data->pwm_mode[nr]));
2987 }
2988
2989 static ssize_t
2990 store_fan_time(struct device *dev, struct device_attribute *attr,
2991 const char *buf, size_t count)
2992 {
2993 struct nct6775_data *data = dev_get_drvdata(dev);
2994 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2995 int nr = sattr->nr;
2996 int index = sattr->index;
2997 unsigned long val;
2998 int err;
2999
3000 err = kstrtoul(buf, 10, &val);
3001 if (err < 0)
3002 return err;
3003
3004 val = step_time_to_reg(val, data->pwm_mode[nr]);
3005 mutex_lock(&data->update_lock);
3006 data->fan_time[index][nr] = val;
3007 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
3008 mutex_unlock(&data->update_lock);
3009 return count;
3010 }
3011
3012 static ssize_t
3013 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
3014 {
3015 struct nct6775_data *data = nct6775_update_device(dev);
3016 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3017
3018 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3019 }
3020
3021 static ssize_t
3022 store_auto_pwm(struct device *dev, struct device_attribute *attr,
3023 const char *buf, size_t count)
3024 {
3025 struct nct6775_data *data = dev_get_drvdata(dev);
3026 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3027 int nr = sattr->nr;
3028 int point = sattr->index;
3029 unsigned long val;
3030 int err;
3031 u8 reg;
3032
3033 err = kstrtoul(buf, 10, &val);
3034 if (err < 0)
3035 return err;
3036 if (val > 255)
3037 return -EINVAL;
3038
3039 if (point == data->auto_pwm_num) {
3040 if (data->kind != nct6775 && !val)
3041 return -EINVAL;
3042 if (data->kind != nct6779 && val)
3043 val = 0xff;
3044 }
3045
3046 mutex_lock(&data->update_lock);
3047 data->auto_pwm[nr][point] = val;
3048 if (point < data->auto_pwm_num) {
3049 nct6775_write_value(data,
3050 NCT6775_AUTO_PWM(data, nr, point),
3051 data->auto_pwm[nr][point]);
3052 } else {
3053 switch (data->kind) {
3054 case nct6775:
3055 /* disable if needed (pwm == 0) */
3056 reg = nct6775_read_value(data,
3057 NCT6775_REG_CRITICAL_ENAB[nr]);
3058 if (val)
3059 reg |= 0x02;
3060 else
3061 reg &= ~0x02;
3062 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3063 reg);
3064 break;
3065 case nct6776:
3066 break; /* always enabled, nothing to do */
3067 case nct6106:
3068 case nct6779:
3069 case nct6791:
3070 case nct6792:
3071 case nct6793:
3072 case nct6795:
3073 case nct6796:
3074 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3075 val);
3076 reg = nct6775_read_value(data,
3077 data->REG_CRITICAL_PWM_ENABLE[nr]);
3078 if (val == 255)
3079 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3080 else
3081 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3082 nct6775_write_value(data,
3083 data->REG_CRITICAL_PWM_ENABLE[nr],
3084 reg);
3085 break;
3086 }
3087 }
3088 mutex_unlock(&data->update_lock);
3089 return count;
3090 }
3091
3092 static ssize_t
3093 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3094 {
3095 struct nct6775_data *data = nct6775_update_device(dev);
3096 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3097 int nr = sattr->nr;
3098 int point = sattr->index;
3099
3100 /*
3101 * We don't know for sure if the temperature is signed or unsigned.
3102 * Assume it is unsigned.
3103 */
3104 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3105 }
3106
3107 static ssize_t
3108 store_auto_temp(struct device *dev, struct device_attribute *attr,
3109 const char *buf, size_t count)
3110 {
3111 struct nct6775_data *data = dev_get_drvdata(dev);
3112 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3113 int nr = sattr->nr;
3114 int point = sattr->index;
3115 unsigned long val;
3116 int err;
3117
3118 err = kstrtoul(buf, 10, &val);
3119 if (err)
3120 return err;
3121 if (val > 255000)
3122 return -EINVAL;
3123
3124 mutex_lock(&data->update_lock);
3125 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3126 if (point < data->auto_pwm_num) {
3127 nct6775_write_value(data,
3128 NCT6775_AUTO_TEMP(data, nr, point),
3129 data->auto_temp[nr][point]);
3130 } else {
3131 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3132 data->auto_temp[nr][point]);
3133 }
3134 mutex_unlock(&data->update_lock);
3135 return count;
3136 }
3137
3138 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3139 struct attribute *attr, int index)
3140 {
3141 struct device *dev = container_of(kobj, struct device, kobj);
3142 struct nct6775_data *data = dev_get_drvdata(dev);
3143 int pwm = index / 36; /* pwm index */
3144 int nr = index % 36; /* attribute index */
3145
3146 if (!(data->has_pwm & BIT(pwm)))
3147 return 0;
3148
3149 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3150 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3151 return 0;
3152 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3153 return 0;
3154 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3155 return 0;
3156 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3157 return 0;
3158
3159 if (nr >= 22 && nr <= 35) { /* auto point */
3160 int api = (nr - 22) / 2; /* auto point index */
3161
3162 if (api > data->auto_pwm_num)
3163 return 0;
3164 }
3165 return attr->mode;
3166 }
3167
3168 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3169 show_fan_time, store_fan_time, 0, 0);
3170 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3171 show_fan_time, store_fan_time, 0, 1);
3172 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3173 show_fan_time, store_fan_time, 0, 2);
3174 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3175 store_pwm, 0, 1);
3176 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3177 store_pwm, 0, 2);
3178 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3179 show_temp_tolerance, store_temp_tolerance, 0, 0);
3180 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3181 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3182 0, 1);
3183
3184 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3185 0, 3);
3186
3187 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3188 store_pwm, 0, 4);
3189
3190 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3191 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3192 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3193 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3194
3195 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3196 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3197 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3198 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3199
3200 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3201 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3202 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3203 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3204
3205 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3206 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3207 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3208 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3209
3210 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3211 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3212 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3213 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3214
3215 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3216 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3217 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3218 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3219
3220 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3221 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3222 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3223 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3224
3225 /*
3226 * nct6775_pwm_is_visible uses the index into the following array
3227 * to determine if attributes should be created or not.
3228 * Any change in order or content must be matched.
3229 */
3230 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3231 &sensor_dev_template_pwm,
3232 &sensor_dev_template_pwm_mode,
3233 &sensor_dev_template_pwm_enable,
3234 &sensor_dev_template_pwm_temp_sel,
3235 &sensor_dev_template_pwm_temp_tolerance,
3236 &sensor_dev_template_pwm_crit_temp_tolerance,
3237 &sensor_dev_template_pwm_target_temp,
3238 &sensor_dev_template_fan_target,
3239 &sensor_dev_template_fan_tolerance,
3240 &sensor_dev_template_pwm_stop_time,
3241 &sensor_dev_template_pwm_step_up_time,
3242 &sensor_dev_template_pwm_step_down_time,
3243 &sensor_dev_template_pwm_start,
3244 &sensor_dev_template_pwm_floor,
3245 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3246 &sensor_dev_template_pwm_weight_temp_step,
3247 &sensor_dev_template_pwm_weight_temp_step_tol,
3248 &sensor_dev_template_pwm_weight_temp_step_base,
3249 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3250 &sensor_dev_template_pwm_max, /* 19 */
3251 &sensor_dev_template_pwm_step, /* 20 */
3252 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3253 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3254 &sensor_dev_template_pwm_auto_point1_temp,
3255 &sensor_dev_template_pwm_auto_point2_pwm,
3256 &sensor_dev_template_pwm_auto_point2_temp,
3257 &sensor_dev_template_pwm_auto_point3_pwm,
3258 &sensor_dev_template_pwm_auto_point3_temp,
3259 &sensor_dev_template_pwm_auto_point4_pwm,
3260 &sensor_dev_template_pwm_auto_point4_temp,
3261 &sensor_dev_template_pwm_auto_point5_pwm,
3262 &sensor_dev_template_pwm_auto_point5_temp,
3263 &sensor_dev_template_pwm_auto_point6_pwm,
3264 &sensor_dev_template_pwm_auto_point6_temp,
3265 &sensor_dev_template_pwm_auto_point7_pwm,
3266 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3267
3268 NULL
3269 };
3270
3271 static const struct sensor_template_group nct6775_pwm_template_group = {
3272 .templates = nct6775_attributes_pwm_template,
3273 .is_visible = nct6775_pwm_is_visible,
3274 .base = 1,
3275 };
3276
3277 static ssize_t
3278 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3279 {
3280 struct nct6775_data *data = dev_get_drvdata(dev);
3281
3282 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3283 }
3284
3285 static DEVICE_ATTR_RO(cpu0_vid);
3286
3287 /* Case open detection */
3288
3289 static ssize_t
3290 clear_caseopen(struct device *dev, struct device_attribute *attr,
3291 const char *buf, size_t count)
3292 {
3293 struct nct6775_data *data = dev_get_drvdata(dev);
3294 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3295 unsigned long val;
3296 u8 reg;
3297 int ret;
3298
3299 if (kstrtoul(buf, 10, &val) || val != 0)
3300 return -EINVAL;
3301
3302 mutex_lock(&data->update_lock);
3303
3304 /*
3305 * Use CR registers to clear caseopen status.
3306 * The CR registers are the same for all chips, and not all chips
3307 * support clearing the caseopen status through "regular" registers.
3308 */
3309 ret = superio_enter(data->sioreg);
3310 if (ret) {
3311 count = ret;
3312 goto error;
3313 }
3314
3315 superio_select(data->sioreg, NCT6775_LD_ACPI);
3316 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3317 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3318 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3319 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3320 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3321 superio_exit(data->sioreg);
3322
3323 data->valid = false; /* Force cache refresh */
3324 error:
3325 mutex_unlock(&data->update_lock);
3326 return count;
3327 }
3328
3329 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3330 clear_caseopen, INTRUSION_ALARM_BASE);
3331 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3332 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3333 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3334 store_beep, INTRUSION_ALARM_BASE);
3335 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3336 store_beep, INTRUSION_ALARM_BASE + 1);
3337 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3338 store_beep, BEEP_ENABLE_BASE);
3339
3340 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3341 struct attribute *attr, int index)
3342 {
3343 struct device *dev = container_of(kobj, struct device, kobj);
3344 struct nct6775_data *data = dev_get_drvdata(dev);
3345
3346 if (index == 0 && !data->have_vid)
3347 return 0;
3348
3349 if (index == 1 || index == 2) {
3350 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3351 return 0;
3352 }
3353
3354 if (index == 3 || index == 4) {
3355 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3356 return 0;
3357 }
3358
3359 return attr->mode;
3360 }
3361
3362 /*
3363 * nct6775_other_is_visible uses the index into the following array
3364 * to determine if attributes should be created or not.
3365 * Any change in order or content must be matched.
3366 */
3367 static struct attribute *nct6775_attributes_other[] = {
3368 &dev_attr_cpu0_vid.attr, /* 0 */
3369 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3370 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3371 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3372 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3373 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3374
3375 NULL
3376 };
3377
3378 static const struct attribute_group nct6775_group_other = {
3379 .attrs = nct6775_attributes_other,
3380 .is_visible = nct6775_other_is_visible,
3381 };
3382
3383 static inline void nct6775_init_device(struct nct6775_data *data)
3384 {
3385 int i;
3386 u8 tmp, diode;
3387
3388 /* Start monitoring if needed */
3389 if (data->REG_CONFIG) {
3390 tmp = nct6775_read_value(data, data->REG_CONFIG);
3391 if (!(tmp & 0x01))
3392 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3393 }
3394
3395 /* Enable temperature sensors if needed */
3396 for (i = 0; i < NUM_TEMP; i++) {
3397 if (!(data->have_temp & BIT(i)))
3398 continue;
3399 if (!data->reg_temp_config[i])
3400 continue;
3401 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3402 if (tmp & 0x01)
3403 nct6775_write_value(data, data->reg_temp_config[i],
3404 tmp & 0xfe);
3405 }
3406
3407 /* Enable VBAT monitoring if needed */
3408 tmp = nct6775_read_value(data, data->REG_VBAT);
3409 if (!(tmp & 0x01))
3410 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3411
3412 diode = nct6775_read_value(data, data->REG_DIODE);
3413
3414 for (i = 0; i < data->temp_fixed_num; i++) {
3415 if (!(data->have_temp_fixed & BIT(i)))
3416 continue;
3417 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3418 data->temp_type[i]
3419 = 3 - ((diode >> i) & data->DIODE_MASK);
3420 else /* thermistor */
3421 data->temp_type[i] = 4;
3422 }
3423 }
3424
3425 static void
3426 nct6775_check_fan_inputs(struct nct6775_data *data)
3427 {
3428 bool fan3pin = false, fan4pin = false, fan4min = false;
3429 bool fan5pin = false, fan6pin = false, fan7pin = false;
3430 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3431 bool pwm6pin = false, pwm7pin = false;
3432 int sioreg = data->sioreg;
3433 int regval;
3434
3435 /* Store SIO_REG_ENABLE for use during resume */
3436 superio_select(sioreg, NCT6775_LD_HWM);
3437 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3438
3439 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3440 if (data->kind == nct6775) {
3441 regval = superio_inb(sioreg, 0x2c);
3442
3443 fan3pin = regval & BIT(6);
3444 pwm3pin = regval & BIT(7);
3445
3446 /* On NCT6775, fan4 shares pins with the fdc interface */
3447 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3448 } else if (data->kind == nct6776) {
3449 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3450 const char *board_vendor, *board_name;
3451
3452 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3453 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3454
3455 if (board_name && board_vendor &&
3456 !strcmp(board_vendor, "ASRock")) {
3457 /*
3458 * Auxiliary fan monitoring is not enabled on ASRock
3459 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3460 * Observed with BIOS version 2.00.
3461 */
3462 if (!strcmp(board_name, "Z77 Pro4-M")) {
3463 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3464 data->sio_reg_enable |= 0xe0;
3465 superio_outb(sioreg, SIO_REG_ENABLE,
3466 data->sio_reg_enable);
3467 }
3468 }
3469 }
3470
3471 if (data->sio_reg_enable & 0x80)
3472 fan3pin = gpok;
3473 else
3474 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3475
3476 if (data->sio_reg_enable & 0x40)
3477 fan4pin = gpok;
3478 else
3479 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3480
3481 if (data->sio_reg_enable & 0x20)
3482 fan5pin = gpok;
3483 else
3484 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3485
3486 fan4min = fan4pin;
3487 pwm3pin = fan3pin;
3488 } else if (data->kind == nct6106) {
3489 regval = superio_inb(sioreg, 0x24);
3490 fan3pin = !(regval & 0x80);
3491 pwm3pin = regval & 0x08;
3492 } else {
3493 /* NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D */
3494 int regval_1b, regval_2a, regval_2f;
3495 bool dsw_en;
3496
3497 regval = superio_inb(sioreg, 0x1c);
3498
3499 fan3pin = !(regval & BIT(5));
3500 fan4pin = !(regval & BIT(6));
3501 fan5pin = !(regval & BIT(7));
3502
3503 pwm3pin = !(regval & BIT(0));
3504 pwm4pin = !(regval & BIT(1));
3505 pwm5pin = !(regval & BIT(2));
3506
3507 regval = superio_inb(sioreg, 0x2d);
3508 switch (data->kind) {
3509 case nct6791:
3510 case nct6792:
3511 fan6pin = regval & BIT(1);
3512 pwm6pin = regval & BIT(0);
3513 break;
3514 case nct6793:
3515 case nct6795:
3516 case nct6796:
3517 regval_1b = superio_inb(sioreg, 0x1b);
3518 regval_2a = superio_inb(sioreg, 0x2a);
3519 regval_2f = superio_inb(sioreg, 0x2f);
3520 dsw_en = regval_2f & BIT(3);
3521
3522 if (!pwm5pin)
3523 pwm5pin = regval & BIT(7);
3524
3525 if (!fan5pin)
3526 fan5pin = regval_1b & BIT(5);
3527
3528 superio_select(sioreg, NCT6775_LD_12);
3529 if (data->kind != nct6796) {
3530 int regval_eb = superio_inb(sioreg, 0xeb);
3531
3532 if (!dsw_en) {
3533 fan6pin = regval & BIT(1);
3534 pwm6pin = regval & BIT(0);
3535 }
3536
3537 if (!fan5pin)
3538 fan5pin = regval_eb & BIT(5);
3539 if (!pwm5pin)
3540 pwm5pin = (regval_eb & BIT(4)) &&
3541 !(regval_2a & BIT(0));
3542 if (!fan6pin)
3543 fan6pin = regval_eb & BIT(3);
3544 if (!pwm6pin)
3545 pwm6pin = regval_eb & BIT(2);
3546 }
3547
3548 if (data->kind == nct6795 || data->kind == nct6796) {
3549 int regval_ed = superio_inb(sioreg, 0xed);
3550
3551 if (!fan6pin)
3552 fan6pin = (regval_2a & BIT(4)) &&
3553 (!dsw_en ||
3554 (dsw_en && (regval_ed & BIT(4))));
3555 if (!pwm6pin)
3556 pwm6pin = (regval_2a & BIT(3)) &&
3557 (regval_ed & BIT(2));
3558 }
3559
3560 if (data->kind == nct6796) {
3561 int regval_1d = superio_inb(sioreg, 0x1d);
3562 int regval_2b = superio_inb(sioreg, 0x2b);
3563
3564 fan7pin = !(regval_2b & BIT(2));
3565 pwm7pin = !(regval_1d & (BIT(2) | BIT(3)));
3566 }
3567
3568 break;
3569 default: /* NCT6779D */
3570 break;
3571 }
3572
3573 fan4min = fan4pin;
3574 }
3575
3576 /* fan 1 and 2 (0x03) are always present */
3577 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3578 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3579 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3580 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3581 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3582 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3583 }
3584
3585 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3586 int *available, int *mask)
3587 {
3588 int i;
3589 u8 src;
3590
3591 for (i = 0; i < data->pwm_num && *available; i++) {
3592 int index;
3593
3594 if (!regp[i])
3595 continue;
3596 src = nct6775_read_value(data, regp[i]);
3597 src &= 0x1f;
3598 if (!src || (*mask & BIT(src)))
3599 continue;
3600 if (!(data->temp_mask & BIT(src)))
3601 continue;
3602
3603 index = __ffs(*available);
3604 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3605 *available &= ~BIT(index);
3606 *mask |= BIT(src);
3607 }
3608 }
3609
3610 static int nct6775_probe(struct platform_device *pdev)
3611 {
3612 struct device *dev = &pdev->dev;
3613 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3614 struct nct6775_data *data;
3615 struct resource *res;
3616 int i, s, err = 0;
3617 int src, mask, available;
3618 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3619 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3620 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3621 int num_reg_temp, num_reg_temp_mon;
3622 u8 cr2a;
3623 struct attribute_group *group;
3624 struct device *hwmon_dev;
3625 int num_attr_groups = 0;
3626
3627 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3628 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3629 DRVNAME))
3630 return -EBUSY;
3631
3632 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3633 GFP_KERNEL);
3634 if (!data)
3635 return -ENOMEM;
3636
3637 data->kind = sio_data->kind;
3638 data->sioreg = sio_data->sioreg;
3639 data->addr = res->start;
3640 mutex_init(&data->update_lock);
3641 data->name = nct6775_device_names[data->kind];
3642 data->bank = 0xff; /* Force initial bank selection */
3643 platform_set_drvdata(pdev, data);
3644
3645 switch (data->kind) {
3646 case nct6106:
3647 data->in_num = 9;
3648 data->pwm_num = 3;
3649 data->auto_pwm_num = 4;
3650 data->temp_fixed_num = 3;
3651 data->num_temp_alarms = 6;
3652 data->num_temp_beeps = 6;
3653
3654 data->fan_from_reg = fan_from_reg13;
3655 data->fan_from_reg_min = fan_from_reg13;
3656
3657 data->temp_label = nct6776_temp_label;
3658 data->temp_mask = NCT6776_TEMP_MASK;
3659 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3660
3661 data->REG_VBAT = NCT6106_REG_VBAT;
3662 data->REG_DIODE = NCT6106_REG_DIODE;
3663 data->DIODE_MASK = NCT6106_DIODE_MASK;
3664 data->REG_VIN = NCT6106_REG_IN;
3665 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3666 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3667 data->REG_TARGET = NCT6106_REG_TARGET;
3668 data->REG_FAN = NCT6106_REG_FAN;
3669 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3670 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3671 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3672 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3673 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3674 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3675 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3676 data->REG_TOLERANCE_H = NCT6106_REG_TOLERANCE_H;
3677 data->REG_PWM[0] = NCT6106_REG_PWM;
3678 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3679 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3680 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3681 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3682 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3683 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3684 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3685 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3686 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3687 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3688 data->REG_CRITICAL_TEMP_TOLERANCE
3689 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3690 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3691 data->CRITICAL_PWM_ENABLE_MASK
3692 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3693 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3694 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3695 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3696 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3697 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3698 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3699 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3700 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3701 data->REG_ALARM = NCT6106_REG_ALARM;
3702 data->ALARM_BITS = NCT6106_ALARM_BITS;
3703 data->REG_BEEP = NCT6106_REG_BEEP;
3704 data->BEEP_BITS = NCT6106_BEEP_BITS;
3705
3706 reg_temp = NCT6106_REG_TEMP;
3707 reg_temp_mon = NCT6106_REG_TEMP_MON;
3708 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3709 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3710 reg_temp_over = NCT6106_REG_TEMP_OVER;
3711 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3712 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3713 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3714 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3715 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3716 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3717
3718 break;
3719 case nct6775:
3720 data->in_num = 9;
3721 data->pwm_num = 3;
3722 data->auto_pwm_num = 6;
3723 data->has_fan_div = true;
3724 data->temp_fixed_num = 3;
3725 data->num_temp_alarms = 3;
3726 data->num_temp_beeps = 3;
3727
3728 data->ALARM_BITS = NCT6775_ALARM_BITS;
3729 data->BEEP_BITS = NCT6775_BEEP_BITS;
3730
3731 data->fan_from_reg = fan_from_reg16;
3732 data->fan_from_reg_min = fan_from_reg8;
3733 data->target_temp_mask = 0x7f;
3734 data->tolerance_mask = 0x0f;
3735 data->speed_tolerance_limit = 15;
3736
3737 data->temp_label = nct6775_temp_label;
3738 data->temp_mask = NCT6775_TEMP_MASK;
3739 data->virt_temp_mask = NCT6775_VIRT_TEMP_MASK;
3740
3741 data->REG_CONFIG = NCT6775_REG_CONFIG;
3742 data->REG_VBAT = NCT6775_REG_VBAT;
3743 data->REG_DIODE = NCT6775_REG_DIODE;
3744 data->DIODE_MASK = NCT6775_DIODE_MASK;
3745 data->REG_VIN = NCT6775_REG_IN;
3746 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3747 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3748 data->REG_TARGET = NCT6775_REG_TARGET;
3749 data->REG_FAN = NCT6775_REG_FAN;
3750 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3751 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3752 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3753 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3754 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3755 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3756 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3757 data->REG_PWM[0] = NCT6775_REG_PWM;
3758 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3759 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3760 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3761 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3762 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3763 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3764 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3765 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3766 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3767 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3768 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3769 data->REG_CRITICAL_TEMP_TOLERANCE
3770 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3771 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3772 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3773 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3774 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3775 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3776 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3777 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3778 data->REG_ALARM = NCT6775_REG_ALARM;
3779 data->REG_BEEP = NCT6775_REG_BEEP;
3780
3781 reg_temp = NCT6775_REG_TEMP;
3782 reg_temp_mon = NCT6775_REG_TEMP_MON;
3783 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3784 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3785 reg_temp_over = NCT6775_REG_TEMP_OVER;
3786 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3787 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3788 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3789 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3790
3791 break;
3792 case nct6776:
3793 data->in_num = 9;
3794 data->pwm_num = 3;
3795 data->auto_pwm_num = 4;
3796 data->has_fan_div = false;
3797 data->temp_fixed_num = 3;
3798 data->num_temp_alarms = 3;
3799 data->num_temp_beeps = 6;
3800
3801 data->ALARM_BITS = NCT6776_ALARM_BITS;
3802 data->BEEP_BITS = NCT6776_BEEP_BITS;
3803
3804 data->fan_from_reg = fan_from_reg13;
3805 data->fan_from_reg_min = fan_from_reg13;
3806 data->target_temp_mask = 0xff;
3807 data->tolerance_mask = 0x07;
3808 data->speed_tolerance_limit = 63;
3809
3810 data->temp_label = nct6776_temp_label;
3811 data->temp_mask = NCT6776_TEMP_MASK;
3812 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3813
3814 data->REG_CONFIG = NCT6775_REG_CONFIG;
3815 data->REG_VBAT = NCT6775_REG_VBAT;
3816 data->REG_DIODE = NCT6775_REG_DIODE;
3817 data->DIODE_MASK = NCT6775_DIODE_MASK;
3818 data->REG_VIN = NCT6775_REG_IN;
3819 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3820 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3821 data->REG_TARGET = NCT6775_REG_TARGET;
3822 data->REG_FAN = NCT6775_REG_FAN;
3823 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3824 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3825 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3826 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3827 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3828 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3829 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3830 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3831 data->REG_PWM[0] = NCT6775_REG_PWM;
3832 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3833 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3834 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3835 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3836 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3837 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3838 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3839 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3840 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3841 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3842 data->REG_CRITICAL_TEMP_TOLERANCE
3843 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3844 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3845 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3846 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3847 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3848 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3849 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3850 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3851 data->REG_ALARM = NCT6775_REG_ALARM;
3852 data->REG_BEEP = NCT6776_REG_BEEP;
3853
3854 reg_temp = NCT6775_REG_TEMP;
3855 reg_temp_mon = NCT6775_REG_TEMP_MON;
3856 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3857 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3858 reg_temp_over = NCT6775_REG_TEMP_OVER;
3859 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3860 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3861 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3862 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3863
3864 break;
3865 case nct6779:
3866 data->in_num = 15;
3867 data->pwm_num = 5;
3868 data->auto_pwm_num = 4;
3869 data->has_fan_div = false;
3870 data->temp_fixed_num = 6;
3871 data->num_temp_alarms = 2;
3872 data->num_temp_beeps = 2;
3873
3874 data->ALARM_BITS = NCT6779_ALARM_BITS;
3875 data->BEEP_BITS = NCT6779_BEEP_BITS;
3876
3877 data->fan_from_reg = fan_from_reg_rpm;
3878 data->fan_from_reg_min = fan_from_reg13;
3879 data->target_temp_mask = 0xff;
3880 data->tolerance_mask = 0x07;
3881 data->speed_tolerance_limit = 63;
3882
3883 data->temp_label = nct6779_temp_label;
3884 data->temp_mask = NCT6779_TEMP_MASK;
3885 data->virt_temp_mask = NCT6779_VIRT_TEMP_MASK;
3886
3887 data->REG_CONFIG = NCT6775_REG_CONFIG;
3888 data->REG_VBAT = NCT6775_REG_VBAT;
3889 data->REG_DIODE = NCT6775_REG_DIODE;
3890 data->DIODE_MASK = NCT6775_DIODE_MASK;
3891 data->REG_VIN = NCT6779_REG_IN;
3892 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3893 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3894 data->REG_TARGET = NCT6775_REG_TARGET;
3895 data->REG_FAN = NCT6779_REG_FAN;
3896 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3897 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3898 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
3899 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3900 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3901 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3902 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3903 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3904 data->REG_PWM[0] = NCT6775_REG_PWM;
3905 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3906 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3907 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3908 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3909 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3910 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3911 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3912 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3913 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3914 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3915 data->REG_CRITICAL_TEMP_TOLERANCE
3916 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3917 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
3918 data->CRITICAL_PWM_ENABLE_MASK
3919 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
3920 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
3921 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
3922 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3923 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3924 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3925 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3926 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3927 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3928 data->REG_ALARM = NCT6779_REG_ALARM;
3929 data->REG_BEEP = NCT6776_REG_BEEP;
3930
3931 reg_temp = NCT6779_REG_TEMP;
3932 reg_temp_mon = NCT6779_REG_TEMP_MON;
3933 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
3934 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
3935 reg_temp_over = NCT6779_REG_TEMP_OVER;
3936 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
3937 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
3938 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
3939 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
3940
3941 break;
3942 case nct6791:
3943 case nct6792:
3944 case nct6793:
3945 case nct6795:
3946 case nct6796:
3947 data->in_num = 15;
3948 data->pwm_num = (data->kind == nct6796) ? 7 : 6;
3949 data->auto_pwm_num = 4;
3950 data->has_fan_div = false;
3951 data->temp_fixed_num = 6;
3952 data->num_temp_alarms = 2;
3953 data->num_temp_beeps = 2;
3954
3955 data->ALARM_BITS = NCT6791_ALARM_BITS;
3956 data->BEEP_BITS = NCT6779_BEEP_BITS;
3957
3958 data->fan_from_reg = fan_from_reg_rpm;
3959 data->fan_from_reg_min = fan_from_reg13;
3960 data->target_temp_mask = 0xff;
3961 data->tolerance_mask = 0x07;
3962 data->speed_tolerance_limit = 63;
3963
3964 switch (data->kind) {
3965 default:
3966 case nct6791:
3967 data->temp_label = nct6779_temp_label;
3968 data->temp_mask = NCT6791_TEMP_MASK;
3969 data->virt_temp_mask = NCT6791_VIRT_TEMP_MASK;
3970 break;
3971 case nct6792:
3972 data->temp_label = nct6792_temp_label;
3973 data->temp_mask = NCT6792_TEMP_MASK;
3974 data->virt_temp_mask = NCT6792_VIRT_TEMP_MASK;
3975 break;
3976 case nct6793:
3977 data->temp_label = nct6793_temp_label;
3978 data->temp_mask = NCT6793_TEMP_MASK;
3979 data->virt_temp_mask = NCT6793_VIRT_TEMP_MASK;
3980 break;
3981 case nct6795:
3982 data->temp_label = nct6795_temp_label;
3983 data->temp_mask = NCT6795_TEMP_MASK;
3984 data->virt_temp_mask = NCT6795_VIRT_TEMP_MASK;
3985 break;
3986 case nct6796:
3987 data->temp_label = nct6796_temp_label;
3988 data->temp_mask = NCT6796_TEMP_MASK;
3989 data->virt_temp_mask = NCT6796_VIRT_TEMP_MASK;
3990 break;
3991 }
3992
3993 data->REG_CONFIG = NCT6775_REG_CONFIG;
3994 data->REG_VBAT = NCT6775_REG_VBAT;
3995 data->REG_DIODE = NCT6775_REG_DIODE;
3996 data->DIODE_MASK = NCT6775_DIODE_MASK;
3997 data->REG_VIN = NCT6779_REG_IN;
3998 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3999 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
4000 data->REG_TARGET = NCT6775_REG_TARGET;
4001 data->REG_FAN = NCT6779_REG_FAN;
4002 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
4003 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
4004 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
4005 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
4006 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
4007 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
4008 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
4009 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
4010 data->REG_PWM[0] = NCT6775_REG_PWM;
4011 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
4012 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
4013 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
4014 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
4015 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4016 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4017 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4018 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4019 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4020 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4021 data->REG_CRITICAL_TEMP_TOLERANCE
4022 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4023 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4024 data->CRITICAL_PWM_ENABLE_MASK
4025 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4026 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4027 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4028 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4029 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4030 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4031 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4032 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4033 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4034 data->REG_ALARM = NCT6791_REG_ALARM;
4035 if (data->kind == nct6791)
4036 data->REG_BEEP = NCT6776_REG_BEEP;
4037 else
4038 data->REG_BEEP = NCT6792_REG_BEEP;
4039
4040 reg_temp = NCT6779_REG_TEMP;
4041 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4042 if (data->kind == nct6791) {
4043 reg_temp_mon = NCT6779_REG_TEMP_MON;
4044 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4045 } else {
4046 reg_temp_mon = NCT6792_REG_TEMP_MON;
4047 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4048 }
4049 reg_temp_over = NCT6779_REG_TEMP_OVER;
4050 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4051 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4052 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4053 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4054
4055 break;
4056 default:
4057 return -ENODEV;
4058 }
4059 data->have_in = BIT(data->in_num) - 1;
4060 data->have_temp = 0;
4061
4062 /*
4063 * On some boards, not all available temperature sources are monitored,
4064 * even though some of the monitoring registers are unused.
4065 * Get list of unused monitoring registers, then detect if any fan
4066 * controls are configured to use unmonitored temperature sources.
4067 * If so, assign the unmonitored temperature sources to available
4068 * monitoring registers.
4069 */
4070 mask = 0;
4071 available = 0;
4072 for (i = 0; i < num_reg_temp; i++) {
4073 if (reg_temp[i] == 0)
4074 continue;
4075
4076 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4077 if (!src || (mask & BIT(src)))
4078 available |= BIT(i);
4079
4080 mask |= BIT(src);
4081 }
4082
4083 /*
4084 * Now find unmonitored temperature registers and enable monitoring
4085 * if additional monitoring registers are available.
4086 */
4087 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4088 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4089
4090 mask = 0;
4091 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
4092 for (i = 0; i < num_reg_temp; i++) {
4093 if (reg_temp[i] == 0)
4094 continue;
4095
4096 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4097 if (!src || (mask & BIT(src)))
4098 continue;
4099
4100 if (!(data->temp_mask & BIT(src))) {
4101 dev_info(dev,
4102 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4103 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4104 continue;
4105 }
4106
4107 mask |= BIT(src);
4108
4109 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4110 if (src <= data->temp_fixed_num) {
4111 data->have_temp |= BIT(src - 1);
4112 data->have_temp_fixed |= BIT(src - 1);
4113 data->reg_temp[0][src - 1] = reg_temp[i];
4114 data->reg_temp[1][src - 1] = reg_temp_over[i];
4115 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4116 if (reg_temp_crit_h && reg_temp_crit_h[i])
4117 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4118 else if (reg_temp_crit[src - 1])
4119 data->reg_temp[3][src - 1]
4120 = reg_temp_crit[src - 1];
4121 if (reg_temp_crit_l && reg_temp_crit_l[i])
4122 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4123 data->reg_temp_config[src - 1] = reg_temp_config[i];
4124 data->temp_src[src - 1] = src;
4125 continue;
4126 }
4127
4128 if (s >= NUM_TEMP)
4129 continue;
4130
4131 /* Use dynamic index for other sources */
4132 data->have_temp |= BIT(s);
4133 data->reg_temp[0][s] = reg_temp[i];
4134 data->reg_temp[1][s] = reg_temp_over[i];
4135 data->reg_temp[2][s] = reg_temp_hyst[i];
4136 data->reg_temp_config[s] = reg_temp_config[i];
4137 if (reg_temp_crit_h && reg_temp_crit_h[i])
4138 data->reg_temp[3][s] = reg_temp_crit_h[i];
4139 else if (reg_temp_crit[src - 1])
4140 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4141 if (reg_temp_crit_l && reg_temp_crit_l[i])
4142 data->reg_temp[4][s] = reg_temp_crit_l[i];
4143
4144 data->temp_src[s] = src;
4145 s++;
4146 }
4147
4148 /*
4149 * Repeat with temperatures used for fan control.
4150 * This set of registers does not support limits.
4151 */
4152 for (i = 0; i < num_reg_temp_mon; i++) {
4153 if (reg_temp_mon[i] == 0)
4154 continue;
4155
4156 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4157 if (!src)
4158 continue;
4159
4160 if (!(data->temp_mask & BIT(src))) {
4161 dev_info(dev,
4162 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4163 src, i, data->REG_TEMP_SEL[i],
4164 reg_temp_mon[i]);
4165 continue;
4166 }
4167
4168 /*
4169 * For virtual temperature sources, the 'virtual' temperature
4170 * for each fan reflects a different temperature, and there
4171 * are no duplicates.
4172 */
4173 if (!(data->virt_temp_mask & BIT(src))) {
4174 if (mask & BIT(src))
4175 continue;
4176 mask |= BIT(src);
4177 }
4178
4179 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4180 if (src <= data->temp_fixed_num) {
4181 if (data->have_temp & BIT(src - 1))
4182 continue;
4183 data->have_temp |= BIT(src - 1);
4184 data->have_temp_fixed |= BIT(src - 1);
4185 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4186 data->temp_src[src - 1] = src;
4187 continue;
4188 }
4189
4190 if (s >= NUM_TEMP)
4191 continue;
4192
4193 /* Use dynamic index for other sources */
4194 data->have_temp |= BIT(s);
4195 data->reg_temp[0][s] = reg_temp_mon[i];
4196 data->temp_src[s] = src;
4197 s++;
4198 }
4199
4200 #ifdef USE_ALTERNATE
4201 /*
4202 * Go through the list of alternate temp registers and enable
4203 * if possible.
4204 * The temperature is already monitored if the respective bit in <mask>
4205 * is set.
4206 */
4207 for (i = 0; i < 31; i++) {
4208 if (!(data->temp_mask & BIT(i + 1)))
4209 continue;
4210 if (!reg_temp_alternate[i])
4211 continue;
4212 if (mask & BIT(i + 1))
4213 continue;
4214 if (i < data->temp_fixed_num) {
4215 if (data->have_temp & BIT(i))
4216 continue;
4217 data->have_temp |= BIT(i);
4218 data->have_temp_fixed |= BIT(i);
4219 data->reg_temp[0][i] = reg_temp_alternate[i];
4220 if (i < num_reg_temp) {
4221 data->reg_temp[1][i] = reg_temp_over[i];
4222 data->reg_temp[2][i] = reg_temp_hyst[i];
4223 }
4224 data->temp_src[i] = i + 1;
4225 continue;
4226 }
4227
4228 if (s >= NUM_TEMP) /* Abort if no more space */
4229 break;
4230
4231 data->have_temp |= BIT(s);
4232 data->reg_temp[0][s] = reg_temp_alternate[i];
4233 data->temp_src[s] = i + 1;
4234 s++;
4235 }
4236 #endif /* USE_ALTERNATE */
4237
4238 /* Initialize the chip */
4239 nct6775_init_device(data);
4240
4241 err = superio_enter(sio_data->sioreg);
4242 if (err)
4243 return err;
4244
4245 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4246 switch (data->kind) {
4247 case nct6775:
4248 data->have_vid = (cr2a & 0x40);
4249 break;
4250 case nct6776:
4251 data->have_vid = (cr2a & 0x60) == 0x40;
4252 break;
4253 case nct6106:
4254 case nct6779:
4255 case nct6791:
4256 case nct6792:
4257 case nct6793:
4258 case nct6795:
4259 case nct6796:
4260 break;
4261 }
4262
4263 /*
4264 * Read VID value
4265 * We can get the VID input values directly at logical device D 0xe3.
4266 */
4267 if (data->have_vid) {
4268 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4269 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4270 data->vrm = vid_which_vrm();
4271 }
4272
4273 if (fan_debounce) {
4274 u8 tmp;
4275
4276 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4277 tmp = superio_inb(sio_data->sioreg,
4278 NCT6775_REG_CR_FAN_DEBOUNCE);
4279 switch (data->kind) {
4280 case nct6106:
4281 tmp |= 0xe0;
4282 break;
4283 case nct6775:
4284 tmp |= 0x1e;
4285 break;
4286 case nct6776:
4287 case nct6779:
4288 tmp |= 0x3e;
4289 break;
4290 case nct6791:
4291 case nct6792:
4292 case nct6793:
4293 case nct6795:
4294 case nct6796:
4295 tmp |= 0x7e;
4296 break;
4297 }
4298 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4299 tmp);
4300 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4301 data->name);
4302 }
4303
4304 nct6775_check_fan_inputs(data);
4305
4306 superio_exit(sio_data->sioreg);
4307
4308 /* Read fan clock dividers immediately */
4309 nct6775_init_fan_common(dev, data);
4310
4311 /* Register sysfs hooks */
4312 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4313 data->pwm_num);
4314 if (IS_ERR(group))
4315 return PTR_ERR(group);
4316
4317 data->groups[num_attr_groups++] = group;
4318
4319 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4320 fls(data->have_in));
4321 if (IS_ERR(group))
4322 return PTR_ERR(group);
4323
4324 data->groups[num_attr_groups++] = group;
4325
4326 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4327 fls(data->has_fan));
4328 if (IS_ERR(group))
4329 return PTR_ERR(group);
4330
4331 data->groups[num_attr_groups++] = group;
4332
4333 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4334 fls(data->have_temp));
4335 if (IS_ERR(group))
4336 return PTR_ERR(group);
4337
4338 data->groups[num_attr_groups++] = group;
4339 data->groups[num_attr_groups++] = &nct6775_group_other;
4340
4341 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4342 data, data->groups);
4343 return PTR_ERR_OR_ZERO(hwmon_dev);
4344 }
4345
4346 static void nct6791_enable_io_mapping(int sioaddr)
4347 {
4348 int val;
4349
4350 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4351 if (val & 0x10) {
4352 pr_info("Enabling hardware monitor logical device mappings.\n");
4353 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4354 val & ~0x10);
4355 }
4356 }
4357
4358 static int __maybe_unused nct6775_suspend(struct device *dev)
4359 {
4360 struct nct6775_data *data = nct6775_update_device(dev);
4361
4362 mutex_lock(&data->update_lock);
4363 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4364 if (data->kind == nct6775) {
4365 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4366 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4367 }
4368 mutex_unlock(&data->update_lock);
4369
4370 return 0;
4371 }
4372
4373 static int __maybe_unused nct6775_resume(struct device *dev)
4374 {
4375 struct nct6775_data *data = dev_get_drvdata(dev);
4376 int sioreg = data->sioreg;
4377 int i, j, err = 0;
4378 u8 reg;
4379
4380 mutex_lock(&data->update_lock);
4381 data->bank = 0xff; /* Force initial bank selection */
4382
4383 err = superio_enter(sioreg);
4384 if (err)
4385 goto abort;
4386
4387 superio_select(sioreg, NCT6775_LD_HWM);
4388 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4389 if (reg != data->sio_reg_enable)
4390 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4391
4392 if (data->kind == nct6791 || data->kind == nct6792 ||
4393 data->kind == nct6793 || data->kind == nct6795 ||
4394 data->kind == nct6796)
4395 nct6791_enable_io_mapping(sioreg);
4396
4397 superio_exit(sioreg);
4398
4399 /* Restore limits */
4400 for (i = 0; i < data->in_num; i++) {
4401 if (!(data->have_in & BIT(i)))
4402 continue;
4403
4404 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4405 data->in[i][1]);
4406 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4407 data->in[i][2]);
4408 }
4409
4410 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4411 if (!(data->has_fan_min & BIT(i)))
4412 continue;
4413
4414 nct6775_write_value(data, data->REG_FAN_MIN[i],
4415 data->fan_min[i]);
4416 }
4417
4418 for (i = 0; i < NUM_TEMP; i++) {
4419 if (!(data->have_temp & BIT(i)))
4420 continue;
4421
4422 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4423 if (data->reg_temp[j][i])
4424 nct6775_write_temp(data, data->reg_temp[j][i],
4425 data->temp[j][i]);
4426 }
4427
4428 /* Restore other settings */
4429 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4430 if (data->kind == nct6775) {
4431 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4432 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4433 }
4434
4435 abort:
4436 /* Force re-reading all values */
4437 data->valid = false;
4438 mutex_unlock(&data->update_lock);
4439
4440 return err;
4441 }
4442
4443 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4444
4445 static struct platform_driver nct6775_driver = {
4446 .driver = {
4447 .name = DRVNAME,
4448 .pm = &nct6775_dev_pm_ops,
4449 },
4450 .probe = nct6775_probe,
4451 };
4452
4453 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4454 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4455 {
4456 u16 val;
4457 int err;
4458 int addr;
4459
4460 err = superio_enter(sioaddr);
4461 if (err)
4462 return err;
4463
4464 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4465 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4466 if (force_id && val != 0xffff)
4467 val = force_id;
4468
4469 switch (val & SIO_ID_MASK) {
4470 case SIO_NCT6106_ID:
4471 sio_data->kind = nct6106;
4472 break;
4473 case SIO_NCT6775_ID:
4474 sio_data->kind = nct6775;
4475 break;
4476 case SIO_NCT6776_ID:
4477 sio_data->kind = nct6776;
4478 break;
4479 case SIO_NCT6779_ID:
4480 sio_data->kind = nct6779;
4481 break;
4482 case SIO_NCT6791_ID:
4483 sio_data->kind = nct6791;
4484 break;
4485 case SIO_NCT6792_ID:
4486 sio_data->kind = nct6792;
4487 break;
4488 case SIO_NCT6793_ID:
4489 sio_data->kind = nct6793;
4490 break;
4491 case SIO_NCT6795_ID:
4492 sio_data->kind = nct6795;
4493 break;
4494 case SIO_NCT6796_ID:
4495 sio_data->kind = nct6796;
4496 break;
4497 default:
4498 if (val != 0xffff)
4499 pr_debug("unsupported chip ID: 0x%04x\n", val);
4500 superio_exit(sioaddr);
4501 return -ENODEV;
4502 }
4503
4504 /* We have a known chip, find the HWM I/O address */
4505 superio_select(sioaddr, NCT6775_LD_HWM);
4506 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4507 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4508 addr = val & IOREGION_ALIGNMENT;
4509 if (addr == 0) {
4510 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4511 superio_exit(sioaddr);
4512 return -ENODEV;
4513 }
4514
4515 /* Activate logical device if needed */
4516 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4517 if (!(val & 0x01)) {
4518 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4519 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4520 }
4521
4522 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4523 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4524 sio_data->kind == nct6796)
4525 nct6791_enable_io_mapping(sioaddr);
4526
4527 superio_exit(sioaddr);
4528 pr_info("Found %s or compatible chip at %#x:%#x\n",
4529 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4530 sio_data->sioreg = sioaddr;
4531
4532 return addr;
4533 }
4534
4535 /*
4536 * when Super-I/O functions move to a separate file, the Super-I/O
4537 * bus will manage the lifetime of the device and this module will only keep
4538 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4539 * must keep track of the device
4540 */
4541 static struct platform_device *pdev[2];
4542
4543 static int __init sensors_nct6775_init(void)
4544 {
4545 int i, err;
4546 bool found = false;
4547 int address;
4548 struct resource res;
4549 struct nct6775_sio_data sio_data;
4550 int sioaddr[2] = { 0x2e, 0x4e };
4551
4552 err = platform_driver_register(&nct6775_driver);
4553 if (err)
4554 return err;
4555
4556 /*
4557 * initialize sio_data->kind and sio_data->sioreg.
4558 *
4559 * when Super-I/O functions move to a separate file, the Super-I/O
4560 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4561 * nct6775 hardware monitor, and call probe()
4562 */
4563 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4564 address = nct6775_find(sioaddr[i], &sio_data);
4565 if (address <= 0)
4566 continue;
4567
4568 found = true;
4569
4570 pdev[i] = platform_device_alloc(DRVNAME, address);
4571 if (!pdev[i]) {
4572 err = -ENOMEM;
4573 goto exit_device_unregister;
4574 }
4575
4576 err = platform_device_add_data(pdev[i], &sio_data,
4577 sizeof(struct nct6775_sio_data));
4578 if (err)
4579 goto exit_device_put;
4580
4581 memset(&res, 0, sizeof(res));
4582 res.name = DRVNAME;
4583 res.start = address + IOREGION_OFFSET;
4584 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4585 res.flags = IORESOURCE_IO;
4586
4587 err = acpi_check_resource_conflict(&res);
4588 if (err) {
4589 platform_device_put(pdev[i]);
4590 pdev[i] = NULL;
4591 continue;
4592 }
4593
4594 err = platform_device_add_resources(pdev[i], &res, 1);
4595 if (err)
4596 goto exit_device_put;
4597
4598 /* platform_device_add calls probe() */
4599 err = platform_device_add(pdev[i]);
4600 if (err)
4601 goto exit_device_put;
4602 }
4603 if (!found) {
4604 err = -ENODEV;
4605 goto exit_unregister;
4606 }
4607
4608 return 0;
4609
4610 exit_device_put:
4611 platform_device_put(pdev[i]);
4612 exit_device_unregister:
4613 while (--i >= 0) {
4614 if (pdev[i])
4615 platform_device_unregister(pdev[i]);
4616 }
4617 exit_unregister:
4618 platform_driver_unregister(&nct6775_driver);
4619 return err;
4620 }
4621
4622 static void __exit sensors_nct6775_exit(void)
4623 {
4624 int i;
4625
4626 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4627 if (pdev[i])
4628 platform_device_unregister(pdev[i]);
4629 }
4630 platform_driver_unregister(&nct6775_driver);
4631 }
4632
4633 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4634 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4635 MODULE_LICENSE("GPL");
4636
4637 module_init(sensors_nct6775_init);
4638 module_exit(sensors_nct6775_exit);
Linux with added FPC-III support