?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-rcar.c
blob2c29f901d30908b3f0b4f9b5c29b6639ea46b398
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Renesas R-Car I2C unit
4 *
5 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2015 Renesas Electronics Corporation
7 *
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
9 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 *
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 */
14 #include <linux/bitops.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/dmaengine.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/i2c.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/reset.h>
29 #include <linux/slab.h>
30
31 /* register offsets */
32 #define ICSCR 0x00 /* slave ctrl */
33 #define ICMCR 0x04 /* master ctrl */
34 #define ICSSR 0x08 /* slave status */
35 #define ICMSR 0x0C /* master status */
36 #define ICSIER 0x10 /* slave irq enable */
37 #define ICMIER 0x14 /* master irq enable */
38 #define ICCCR 0x18 /* clock dividers */
39 #define ICSAR 0x1C /* slave address */
40 #define ICMAR 0x20 /* master address */
41 #define ICRXTX 0x24 /* data port */
42 #define ICDMAER 0x3c /* DMA enable */
43 #define ICFBSCR 0x38 /* first bit setup cycle */
44
45 /* ICSCR */
46 #define SDBS (1 << 3) /* slave data buffer select */
47 #define SIE (1 << 2) /* slave interface enable */
48 #define GCAE (1 << 1) /* general call address enable */
49 #define FNA (1 << 0) /* forced non acknowledgment */
50
51 /* ICMCR */
52 #define MDBS (1 << 7) /* non-fifo mode switch */
53 #define FSCL (1 << 6) /* override SCL pin */
54 #define FSDA (1 << 5) /* override SDA pin */
55 #define OBPC (1 << 4) /* override pins */
56 #define MIE (1 << 3) /* master if enable */
57 #define TSBE (1 << 2)
58 #define FSB (1 << 1) /* force stop bit */
59 #define ESG (1 << 0) /* enable start bit gen */
60
61 /* ICSSR (also for ICSIER) */
62 #define GCAR (1 << 6) /* general call received */
63 #define STM (1 << 5) /* slave transmit mode */
64 #define SSR (1 << 4) /* stop received */
65 #define SDE (1 << 3) /* slave data empty */
66 #define SDT (1 << 2) /* slave data transmitted */
67 #define SDR (1 << 1) /* slave data received */
68 #define SAR (1 << 0) /* slave addr received */
69
70 /* ICMSR (also for ICMIE) */
71 #define MNR (1 << 6) /* nack received */
72 #define MAL (1 << 5) /* arbitration lost */
73 #define MST (1 << 4) /* sent a stop */
74 #define MDE (1 << 3)
75 #define MDT (1 << 2)
76 #define MDR (1 << 1)
77 #define MAT (1 << 0) /* slave addr xfer done */
78
79 /* ICDMAER */
80 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */
81 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
82 #define RMDMAE (1 << 1) /* DMA Master Received Enable */
83 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
84
85 /* ICFBSCR */
86 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
87 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
88
89
90 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
91 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
92 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
93 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
94
95 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
96 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
97 #define RCAR_IRQ_STOP (MST)
98
99 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F)
100 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F)
101
102 #define ID_LAST_MSG (1 << 0)
103 #define ID_FIRST_MSG (1 << 1)
104 #define ID_DONE (1 << 2)
105 #define ID_ARBLOST (1 << 3)
106 #define ID_NACK (1 << 4)
107 /* persistent flags */
108 #define ID_P_REP_AFTER_RD BIT(29)
109 #define ID_P_NO_RXDMA BIT(30) /* HW forbids RXDMA sometimes */
110 #define ID_P_PM_BLOCKED BIT(31)
111 #define ID_P_MASK GENMASK(31, 29)
112
113 enum rcar_i2c_type {
114 I2C_RCAR_GEN1,
115 I2C_RCAR_GEN2,
116 I2C_RCAR_GEN3,
117 };
118
119 struct rcar_i2c_priv {
120 void __iomem *io;
121 struct i2c_adapter adap;
122 struct i2c_msg *msg;
123 int msgs_left;
124 struct clk *clk;
125
126 wait_queue_head_t wait;
127
128 int pos;
129 u32 icccr;
130 u32 flags;
131 u8 recovery_icmcr; /* protected by adapter lock */
132 enum rcar_i2c_type devtype;
133 struct i2c_client *slave;
134
135 struct resource *res;
136 struct dma_chan *dma_tx;
137 struct dma_chan *dma_rx;
138 struct scatterlist sg;
139 enum dma_data_direction dma_direction;
140
141 struct reset_control *rstc;
142 int irq;
143 };
144
145 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
146 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
147
148 #define LOOP_TIMEOUT 1024
149
150
151 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
152 {
153 writel(val, priv->io + reg);
154 }
155
156 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
157 {
158 return readl(priv->io + reg);
159 }
160
161 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
162 {
163 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
164
165 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
166
167 };
168
169 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
170 {
171 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
172
173 if (val)
174 priv->recovery_icmcr |= FSCL;
175 else
176 priv->recovery_icmcr &= ~FSCL;
177
178 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
179 };
180
181 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
182 {
183 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
184
185 if (val)
186 priv->recovery_icmcr |= FSDA;
187 else
188 priv->recovery_icmcr &= ~FSDA;
189
190 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
191 };
192
193 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
194 {
195 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
196
197 return !(rcar_i2c_read(priv, ICMCR) & FSDA);
198
199 };
200
201 static struct i2c_bus_recovery_info rcar_i2c_bri = {
202 .get_scl = rcar_i2c_get_scl,
203 .set_scl = rcar_i2c_set_scl,
204 .set_sda = rcar_i2c_set_sda,
205 .get_bus_free = rcar_i2c_get_bus_free,
206 .recover_bus = i2c_generic_scl_recovery,
207 };
208 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
209 {
210 /* reset master mode */
211 rcar_i2c_write(priv, ICMIER, 0);
212 rcar_i2c_write(priv, ICMCR, MDBS);
213 rcar_i2c_write(priv, ICMSR, 0);
214 /* start clock */
215 rcar_i2c_write(priv, ICCCR, priv->icccr);
216 }
217
218 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
219 {
220 int i;
221
222 for (i = 0; i < LOOP_TIMEOUT; i++) {
223 /* make sure that bus is not busy */
224 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
225 return 0;
226 udelay(1);
227 }
228
229 /* Waiting did not help, try to recover */
230 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
231 return i2c_recover_bus(&priv->adap);
232 }
233
234 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
235 {
236 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
237 unsigned long rate;
238 struct device *dev = rcar_i2c_priv_to_dev(priv);
239
240 /* Fall back to previously used values if not supplied */
241 t->bus_freq_hz = t->bus_freq_hz ?: 100000;
242 t->scl_fall_ns = t->scl_fall_ns ?: 35;
243 t->scl_rise_ns = t->scl_rise_ns ?: 200;
244 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
245
246 switch (priv->devtype) {
247 case I2C_RCAR_GEN1:
248 cdf_width = 2;
249 break;
250 case I2C_RCAR_GEN2:
251 case I2C_RCAR_GEN3:
252 cdf_width = 3;
253 break;
254 default:
255 dev_err(dev, "device type error\n");
256 return -EIO;
257 }
258
259 /*
260 * calculate SCL clock
261 * see
262 * ICCCR
263 *
264 * ick = clkp / (1 + CDF)
265 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
266 *
267 * ick : I2C internal clock < 20 MHz
268 * ticf : I2C SCL falling time
269 * tr : I2C SCL rising time
270 * intd : LSI internal delay
271 * clkp : peripheral_clk
272 * F[] : integer up-valuation
273 */
274 rate = clk_get_rate(priv->clk);
275 cdf = rate / 20000000;
276 if (cdf >= 1U << cdf_width) {
277 dev_err(dev, "Input clock %lu too high\n", rate);
278 return -EIO;
279 }
280 ick = rate / (cdf + 1);
281
282 /*
283 * it is impossible to calculate large scale
284 * number on u32. separate it
285 *
286 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
287 * = F[sum * ick / 1000000000]
288 * = F[(ick / 1000000) * sum / 1000]
289 */
290 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
291 round = (ick + 500000) / 1000000 * sum;
292 round = (round + 500) / 1000;
293
294 /*
295 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
296 *
297 * Calculation result (= SCL) should be less than
298 * bus_speed for hardware safety
299 *
300 * We could use something along the lines of
301 * div = ick / (bus_speed + 1) + 1;
302 * scgd = (div - 20 - round + 7) / 8;
303 * scl = ick / (20 + (scgd * 8) + round);
304 * (not fully verified) but that would get pretty involved
305 */
306 for (scgd = 0; scgd < 0x40; scgd++) {
307 scl = ick / (20 + (scgd * 8) + round);
308 if (scl <= t->bus_freq_hz)
309 goto scgd_find;
310 }
311 dev_err(dev, "it is impossible to calculate best SCL\n");
312 return -EIO;
313
314 scgd_find:
315 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
316 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
317
318 /* keep icccr value */
319 priv->icccr = scgd << cdf_width | cdf;
320
321 return 0;
322 }
323
324 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
325 {
326 int read = !!rcar_i2c_is_recv(priv);
327
328 priv->pos = 0;
329 if (priv->msgs_left == 1)
330 priv->flags |= ID_LAST_MSG;
331
332 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
333 /*
334 * We don't have a test case but the HW engineers say that the write order
335 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
336 * it didn't cause a drawback for me, let's rather be safe than sorry.
337 */
338 if (priv->flags & ID_FIRST_MSG) {
339 rcar_i2c_write(priv, ICMSR, 0);
340 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
341 } else {
342 if (priv->flags & ID_P_REP_AFTER_RD)
343 priv->flags &= ~ID_P_REP_AFTER_RD;
344 else
345 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
346 rcar_i2c_write(priv, ICMSR, 0);
347 }
348 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
349 }
350
351 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
352 {
353 priv->msg++;
354 priv->msgs_left--;
355 priv->flags &= ID_P_MASK;
356 rcar_i2c_prepare_msg(priv);
357 }
358
359 /*
360 * interrupt functions
361 */
362 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
363 {
364 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
365 ? priv->dma_rx : priv->dma_tx;
366
367 /* Disable DMA Master Received/Transmitted */
368 rcar_i2c_write(priv, ICDMAER, 0);
369
370 /* Reset default delay */
371 rcar_i2c_write(priv, ICFBSCR, TCYC06);
372
373 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
374 sg_dma_len(&priv->sg), priv->dma_direction);
375
376 /* Gen3 can only do one RXDMA per transfer and we just completed it */
377 if (priv->devtype == I2C_RCAR_GEN3 &&
378 priv->dma_direction == DMA_FROM_DEVICE)
379 priv->flags |= ID_P_NO_RXDMA;
380
381 priv->dma_direction = DMA_NONE;
382 }
383
384 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
385 {
386 if (priv->dma_direction == DMA_NONE)
387 return;
388 else if (priv->dma_direction == DMA_FROM_DEVICE)
389 dmaengine_terminate_all(priv->dma_rx);
390 else if (priv->dma_direction == DMA_TO_DEVICE)
391 dmaengine_terminate_all(priv->dma_tx);
392
393 rcar_i2c_dma_unmap(priv);
394 }
395
396 static void rcar_i2c_dma_callback(void *data)
397 {
398 struct rcar_i2c_priv *priv = data;
399
400 priv->pos += sg_dma_len(&priv->sg);
401
402 rcar_i2c_dma_unmap(priv);
403 }
404
405 static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
406 {
407 struct device *dev = rcar_i2c_priv_to_dev(priv);
408 struct i2c_msg *msg = priv->msg;
409 bool read = msg->flags & I2C_M_RD;
410 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
411 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
412 struct dma_async_tx_descriptor *txdesc;
413 dma_addr_t dma_addr;
414 dma_cookie_t cookie;
415 unsigned char *buf;
416 int len;
417
418 /* Do various checks to see if DMA is feasible at all */
419 if (IS_ERR(chan) || msg->len < 8 || !(msg->flags & I2C_M_DMA_SAFE) ||
420 (read && priv->flags & ID_P_NO_RXDMA))
421 return;
422
423 if (read) {
424 /*
425 * The last two bytes needs to be fetched using PIO in
426 * order for the STOP phase to work.
427 */
428 buf = priv->msg->buf;
429 len = priv->msg->len - 2;
430 } else {
431 /*
432 * First byte in message was sent using PIO.
433 */
434 buf = priv->msg->buf + 1;
435 len = priv->msg->len - 1;
436 }
437
438 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
439 if (dma_mapping_error(chan->device->dev, dma_addr)) {
440 dev_dbg(dev, "dma map failed, using PIO\n");
441 return;
442 }
443
444 sg_dma_len(&priv->sg) = len;
445 sg_dma_address(&priv->sg) = dma_addr;
446
447 priv->dma_direction = dir;
448
449 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
450 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
451 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
452 if (!txdesc) {
453 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
454 rcar_i2c_cleanup_dma(priv);
455 return;
456 }
457
458 txdesc->callback = rcar_i2c_dma_callback;
459 txdesc->callback_param = priv;
460
461 cookie = dmaengine_submit(txdesc);
462 if (dma_submit_error(cookie)) {
463 dev_dbg(dev, "submitting dma failed, using PIO\n");
464 rcar_i2c_cleanup_dma(priv);
465 return;
466 }
467
468 /* Set delay for DMA operations */
469 rcar_i2c_write(priv, ICFBSCR, TCYC17);
470
471 /* Enable DMA Master Received/Transmitted */
472 if (read)
473 rcar_i2c_write(priv, ICDMAER, RMDMAE);
474 else
475 rcar_i2c_write(priv, ICDMAER, TMDMAE);
476
477 dma_async_issue_pending(chan);
478 }
479
480 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
481 {
482 struct i2c_msg *msg = priv->msg;
483
484 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
485 if (!(msr & MDE))
486 return;
487
488 if (priv->pos < msg->len) {
489 /*
490 * Prepare next data to ICRXTX register.
491 * This data will go to _SHIFT_ register.
492 *
493 * *
494 * [ICRXTX] -> [SHIFT] -> [I2C bus]
495 */
496 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
497 priv->pos++;
498
499 /*
500 * Try to use DMA to transmit the rest of the data if
501 * address transfer phase just finished.
502 */
503 if (msr & MAT)
504 rcar_i2c_dma(priv);
505 } else {
506 /*
507 * The last data was pushed to ICRXTX on _PREV_ empty irq.
508 * It is on _SHIFT_ register, and will sent to I2C bus.
509 *
510 * *
511 * [ICRXTX] -> [SHIFT] -> [I2C bus]
512 */
513
514 if (priv->flags & ID_LAST_MSG) {
515 /*
516 * If current msg is the _LAST_ msg,
517 * prepare stop condition here.
518 * ID_DONE will be set on STOP irq.
519 */
520 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
521 } else {
522 rcar_i2c_next_msg(priv);
523 return;
524 }
525 }
526
527 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
528 }
529
530 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
531 {
532 struct i2c_msg *msg = priv->msg;
533
534 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
535 if (!(msr & MDR))
536 return;
537
538 if (msr & MAT) {
539 /*
540 * Address transfer phase finished, but no data at this point.
541 * Try to use DMA to receive data.
542 */
543 rcar_i2c_dma(priv);
544 } else if (priv->pos < msg->len) {
545 /* get received data */
546 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
547 priv->pos++;
548 }
549
550 /* If next received data is the _LAST_, go to new phase. */
551 if (priv->pos + 1 == msg->len) {
552 if (priv->flags & ID_LAST_MSG) {
553 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
554 } else {
555 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
556 priv->flags |= ID_P_REP_AFTER_RD;
557 }
558 }
559
560 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
561 rcar_i2c_next_msg(priv);
562 else
563 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
564 }
565
566 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
567 {
568 u32 ssr_raw, ssr_filtered;
569 u8 value;
570
571 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
572 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
573
574 if (!ssr_filtered)
575 return false;
576
577 /* address detected */
578 if (ssr_filtered & SAR) {
579 /* read or write request */
580 if (ssr_raw & STM) {
581 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
582 rcar_i2c_write(priv, ICRXTX, value);
583 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
584 } else {
585 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
586 rcar_i2c_read(priv, ICRXTX); /* dummy read */
587 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
588 }
589
590 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
591 }
592
593 /* master sent stop */
594 if (ssr_filtered & SSR) {
595 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
596 rcar_i2c_write(priv, ICSIER, SAR | SSR);
597 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
598 }
599
600 /* master wants to write to us */
601 if (ssr_filtered & SDR) {
602 int ret;
603
604 value = rcar_i2c_read(priv, ICRXTX);
605 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
606 /* Send NACK in case of error */
607 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
608 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
609 }
610
611 /* master wants to read from us */
612 if (ssr_filtered & SDE) {
613 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
614 rcar_i2c_write(priv, ICRXTX, value);
615 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
616 }
617
618 return true;
619 }
620
621 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
622 {
623 struct rcar_i2c_priv *priv = ptr;
624 u32 msr, val;
625
626 /* Clear START or STOP immediately, except for REPSTART after read */
627 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) {
628 val = rcar_i2c_read(priv, ICMCR);
629 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
630 }
631
632 msr = rcar_i2c_read(priv, ICMSR);
633
634 /* Only handle interrupts that are currently enabled */
635 msr &= rcar_i2c_read(priv, ICMIER);
636 if (!msr) {
637 if (rcar_i2c_slave_irq(priv))
638 return IRQ_HANDLED;
639
640 return IRQ_NONE;
641 }
642
643 /* Arbitration lost */
644 if (msr & MAL) {
645 priv->flags |= ID_DONE | ID_ARBLOST;
646 goto out;
647 }
648
649 /* Nack */
650 if (msr & MNR) {
651 /* HW automatically sends STOP after received NACK */
652 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
653 priv->flags |= ID_NACK;
654 goto out;
655 }
656
657 /* Stop */
658 if (msr & MST) {
659 priv->msgs_left--; /* The last message also made it */
660 priv->flags |= ID_DONE;
661 goto out;
662 }
663
664 if (rcar_i2c_is_recv(priv))
665 rcar_i2c_irq_recv(priv, msr);
666 else
667 rcar_i2c_irq_send(priv, msr);
668
669 out:
670 if (priv->flags & ID_DONE) {
671 rcar_i2c_write(priv, ICMIER, 0);
672 rcar_i2c_write(priv, ICMSR, 0);
673 wake_up(&priv->wait);
674 }
675
676 return IRQ_HANDLED;
677 }
678
679 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
680 enum dma_transfer_direction dir,
681 dma_addr_t port_addr)
682 {
683 struct dma_chan *chan;
684 struct dma_slave_config cfg;
685 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
686 int ret;
687
688 chan = dma_request_chan(dev, chan_name);
689 if (IS_ERR(chan)) {
690 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
691 chan_name, PTR_ERR(chan));
692 return chan;
693 }
694
695 memset(&cfg, 0, sizeof(cfg));
696 cfg.direction = dir;
697 if (dir == DMA_MEM_TO_DEV) {
698 cfg.dst_addr = port_addr;
699 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
700 } else {
701 cfg.src_addr = port_addr;
702 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
703 }
704
705 ret = dmaengine_slave_config(chan, &cfg);
706 if (ret) {
707 dev_dbg(dev, "slave_config failed for %s (%d)\n",
708 chan_name, ret);
709 dma_release_channel(chan);
710 return ERR_PTR(ret);
711 }
712
713 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
714 return chan;
715 }
716
717 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
718 struct i2c_msg *msg)
719 {
720 struct device *dev = rcar_i2c_priv_to_dev(priv);
721 bool read;
722 struct dma_chan *chan;
723 enum dma_transfer_direction dir;
724
725 read = msg->flags & I2C_M_RD;
726
727 chan = read ? priv->dma_rx : priv->dma_tx;
728 if (PTR_ERR(chan) != -EPROBE_DEFER)
729 return;
730
731 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
732 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
733
734 if (read)
735 priv->dma_rx = chan;
736 else
737 priv->dma_tx = chan;
738 }
739
740 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
741 {
742 if (!IS_ERR(priv->dma_tx)) {
743 dma_release_channel(priv->dma_tx);
744 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
745 }
746
747 if (!IS_ERR(priv->dma_rx)) {
748 dma_release_channel(priv->dma_rx);
749 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
750 }
751 }
752
753 /* I2C is a special case, we need to poll the status of a reset */
754 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
755 {
756 int i, ret;
757
758 ret = reset_control_reset(priv->rstc);
759 if (ret)
760 return ret;
761
762 for (i = 0; i < LOOP_TIMEOUT; i++) {
763 ret = reset_control_status(priv->rstc);
764 if (ret == 0)
765 return 0;
766 udelay(1);
767 }
768
769 return -ETIMEDOUT;
770 }
771
772 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
773 struct i2c_msg *msgs,
774 int num)
775 {
776 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
777 struct device *dev = rcar_i2c_priv_to_dev(priv);
778 int i, ret;
779 long time_left;
780
781 pm_runtime_get_sync(dev);
782
783 /* Check bus state before init otherwise bus busy info will be lost */
784 ret = rcar_i2c_bus_barrier(priv);
785 if (ret < 0)
786 goto out;
787
788 /* Gen3 needs a reset before allowing RXDMA once */
789 if (priv->devtype == I2C_RCAR_GEN3) {
790 priv->flags |= ID_P_NO_RXDMA;
791 if (!IS_ERR(priv->rstc)) {
792 ret = rcar_i2c_do_reset(priv);
793 if (ret == 0)
794 priv->flags &= ~ID_P_NO_RXDMA;
795 }
796 }
797
798 rcar_i2c_init(priv);
799
800 for (i = 0; i < num; i++)
801 rcar_i2c_request_dma(priv, msgs + i);
802
803 /* init first message */
804 priv->msg = msgs;
805 priv->msgs_left = num;
806 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
807 rcar_i2c_prepare_msg(priv);
808
809 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
810 num * adap->timeout);
811
812 /* cleanup DMA if it couldn't complete properly due to an error */
813 if (priv->dma_direction != DMA_NONE)
814 rcar_i2c_cleanup_dma(priv);
815
816 if (!time_left) {
817 rcar_i2c_init(priv);
818 ret = -ETIMEDOUT;
819 } else if (priv->flags & ID_NACK) {
820 ret = -ENXIO;
821 } else if (priv->flags & ID_ARBLOST) {
822 ret = -EAGAIN;
823 } else {
824 ret = num - priv->msgs_left; /* The number of transfer */
825 }
826 out:
827 pm_runtime_put(dev);
828
829 if (ret < 0 && ret != -ENXIO)
830 dev_err(dev, "error %d : %x\n", ret, priv->flags);
831
832 return ret;
833 }
834
835 static int rcar_reg_slave(struct i2c_client *slave)
836 {
837 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
838
839 if (priv->slave)
840 return -EBUSY;
841
842 if (slave->flags & I2C_CLIENT_TEN)
843 return -EAFNOSUPPORT;
844
845 /* Keep device active for slave address detection logic */
846 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
847
848 priv->slave = slave;
849 rcar_i2c_write(priv, ICSAR, slave->addr);
850 rcar_i2c_write(priv, ICSSR, 0);
851 rcar_i2c_write(priv, ICSIER, SAR | SSR);
852 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
853
854 return 0;
855 }
856
857 static int rcar_unreg_slave(struct i2c_client *slave)
858 {
859 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
860
861 WARN_ON(!priv->slave);
862
863 /* disable irqs and ensure none is running before clearing ptr */
864 rcar_i2c_write(priv, ICSIER, 0);
865 rcar_i2c_write(priv, ICSCR, 0);
866
867 synchronize_irq(priv->irq);
868 priv->slave = NULL;
869
870 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
871
872 return 0;
873 }
874
875 static u32 rcar_i2c_func(struct i2c_adapter *adap)
876 {
877 /*
878 * This HW can't do:
879 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
880 * I2C_M_NOSTART (automatically sends address after START)
881 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
882 */
883 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
884 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
885 }
886
887 static const struct i2c_algorithm rcar_i2c_algo = {
888 .master_xfer = rcar_i2c_master_xfer,
889 .functionality = rcar_i2c_func,
890 .reg_slave = rcar_reg_slave,
891 .unreg_slave = rcar_unreg_slave,
892 };
893
894 static const struct i2c_adapter_quirks rcar_i2c_quirks = {
895 .flags = I2C_AQ_NO_ZERO_LEN,
896 };
897
898 static const struct of_device_id rcar_i2c_dt_ids[] = {
899 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
900 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
901 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
902 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
903 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
904 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
905 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
906 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
907 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
908 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */
909 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
910 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
911 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
912 {},
913 };
914 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
915
916 static int rcar_i2c_probe(struct platform_device *pdev)
917 {
918 struct rcar_i2c_priv *priv;
919 struct i2c_adapter *adap;
920 struct device *dev = &pdev->dev;
921 struct i2c_timings i2c_t;
922 int ret;
923
924 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
925 if (!priv)
926 return -ENOMEM;
927
928 priv->clk = devm_clk_get(dev, NULL);
929 if (IS_ERR(priv->clk)) {
930 dev_err(dev, "cannot get clock\n");
931 return PTR_ERR(priv->clk);
932 }
933
934 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
935
936 priv->io = devm_ioremap_resource(dev, priv->res);
937 if (IS_ERR(priv->io))
938 return PTR_ERR(priv->io);
939
940 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
941 init_waitqueue_head(&priv->wait);
942
943 adap = &priv->adap;
944 adap->nr = pdev->id;
945 adap->algo = &rcar_i2c_algo;
946 adap->class = I2C_CLASS_DEPRECATED;
947 adap->retries = 3;
948 adap->dev.parent = dev;
949 adap->dev.of_node = dev->of_node;
950 adap->bus_recovery_info = &rcar_i2c_bri;
951 adap->quirks = &rcar_i2c_quirks;
952 i2c_set_adapdata(adap, priv);
953 strlcpy(adap->name, pdev->name, sizeof(adap->name));
954
955 i2c_parse_fw_timings(dev, &i2c_t, false);
956
957 /* Init DMA */
958 sg_init_table(&priv->sg, 1);
959 priv->dma_direction = DMA_NONE;
960 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
961
962 /* Activate device for clock calculation */
963 pm_runtime_enable(dev);
964 pm_runtime_get_sync(dev);
965 ret = rcar_i2c_clock_calculate(priv, &i2c_t);
966 if (ret < 0)
967 goto out_pm_put;
968
969 if (priv->devtype == I2C_RCAR_GEN3) {
970 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
971 if (!IS_ERR(priv->rstc)) {
972 ret = reset_control_status(priv->rstc);
973 if (ret < 0)
974 priv->rstc = ERR_PTR(-ENOTSUPP);
975 }
976 }
977
978 /* Stay always active when multi-master to keep arbitration working */
979 if (of_property_read_bool(dev->of_node, "multi-master"))
980 priv->flags |= ID_P_PM_BLOCKED;
981 else
982 pm_runtime_put(dev);
983
984
985 priv->irq = platform_get_irq(pdev, 0);
986 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv);
987 if (ret < 0) {
988 dev_err(dev, "cannot get irq %d\n", priv->irq);
989 goto out_pm_disable;
990 }
991
992 platform_set_drvdata(pdev, priv);
993
994 ret = i2c_add_numbered_adapter(adap);
995 if (ret < 0)
996 goto out_pm_disable;
997
998 dev_info(dev, "probed\n");
999
1000 return 0;
1001
1002 out_pm_put:
1003 pm_runtime_put(dev);
1004 out_pm_disable:
1005 pm_runtime_disable(dev);
1006 return ret;
1007 }
1008
1009 static int rcar_i2c_remove(struct platform_device *pdev)
1010 {
1011 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1012 struct device *dev = &pdev->dev;
1013
1014 i2c_del_adapter(&priv->adap);
1015 rcar_i2c_release_dma(priv);
1016 if (priv->flags & ID_P_PM_BLOCKED)
1017 pm_runtime_put(dev);
1018 pm_runtime_disable(dev);
1019
1020 return 0;
1021 }
1022
1023 static struct platform_driver rcar_i2c_driver = {
1024 .driver = {
1025 .name = "i2c-rcar",
1026 .of_match_table = rcar_i2c_dt_ids,
1027 },
1028 .probe = rcar_i2c_probe,
1029 .remove = rcar_i2c_remove,
1030 };
1031
1032 module_platform_driver(rcar_i2c_driver);
1033
1034 MODULE_LICENSE("GPL v2");
1035 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1036 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
Linux with added FPC-III support