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Linux 4.19.133
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-st.c
blob81158ae8bfe361f3416f541651cfc0f2b3287762
1 /*
2 * Copyright (C) 2013 STMicroelectronics
3 *
4 * I2C master mode controller driver, used in STMicroelectronics devices.
5 *
6 * Author: Maxime Coquelin <maxime.coquelin@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25
26 /* SSC registers */
27 #define SSC_BRG 0x000
28 #define SSC_TBUF 0x004
29 #define SSC_RBUF 0x008
30 #define SSC_CTL 0x00C
31 #define SSC_IEN 0x010
32 #define SSC_STA 0x014
33 #define SSC_I2C 0x018
34 #define SSC_SLAD 0x01C
35 #define SSC_REP_START_HOLD 0x020
36 #define SSC_START_HOLD 0x024
37 #define SSC_REP_START_SETUP 0x028
38 #define SSC_DATA_SETUP 0x02C
39 #define SSC_STOP_SETUP 0x030
40 #define SSC_BUS_FREE 0x034
41 #define SSC_TX_FSTAT 0x038
42 #define SSC_RX_FSTAT 0x03C
43 #define SSC_PRE_SCALER_BRG 0x040
44 #define SSC_CLR 0x080
45 #define SSC_NOISE_SUPP_WIDTH 0x100
46 #define SSC_PRSCALER 0x104
47 #define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108
48 #define SSC_PRSCALER_DATAOUT 0x10c
49
50 /* SSC Control */
51 #define SSC_CTL_DATA_WIDTH_9 0x8
52 #define SSC_CTL_DATA_WIDTH_MSK 0xf
53 #define SSC_CTL_BM 0xf
54 #define SSC_CTL_HB BIT(4)
55 #define SSC_CTL_PH BIT(5)
56 #define SSC_CTL_PO BIT(6)
57 #define SSC_CTL_SR BIT(7)
58 #define SSC_CTL_MS BIT(8)
59 #define SSC_CTL_EN BIT(9)
60 #define SSC_CTL_LPB BIT(10)
61 #define SSC_CTL_EN_TX_FIFO BIT(11)
62 #define SSC_CTL_EN_RX_FIFO BIT(12)
63 #define SSC_CTL_EN_CLST_RX BIT(13)
64
65 /* SSC Interrupt Enable */
66 #define SSC_IEN_RIEN BIT(0)
67 #define SSC_IEN_TIEN BIT(1)
68 #define SSC_IEN_TEEN BIT(2)
69 #define SSC_IEN_REEN BIT(3)
70 #define SSC_IEN_PEEN BIT(4)
71 #define SSC_IEN_AASEN BIT(6)
72 #define SSC_IEN_STOPEN BIT(7)
73 #define SSC_IEN_ARBLEN BIT(8)
74 #define SSC_IEN_NACKEN BIT(10)
75 #define SSC_IEN_REPSTRTEN BIT(11)
76 #define SSC_IEN_TX_FIFO_HALF BIT(12)
77 #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14)
78
79 /* SSC Status */
80 #define SSC_STA_RIR BIT(0)
81 #define SSC_STA_TIR BIT(1)
82 #define SSC_STA_TE BIT(2)
83 #define SSC_STA_RE BIT(3)
84 #define SSC_STA_PE BIT(4)
85 #define SSC_STA_CLST BIT(5)
86 #define SSC_STA_AAS BIT(6)
87 #define SSC_STA_STOP BIT(7)
88 #define SSC_STA_ARBL BIT(8)
89 #define SSC_STA_BUSY BIT(9)
90 #define SSC_STA_NACK BIT(10)
91 #define SSC_STA_REPSTRT BIT(11)
92 #define SSC_STA_TX_FIFO_HALF BIT(12)
93 #define SSC_STA_TX_FIFO_FULL BIT(13)
94 #define SSC_STA_RX_FIFO_HALF BIT(14)
95
96 /* SSC I2C Control */
97 #define SSC_I2C_I2CM BIT(0)
98 #define SSC_I2C_STRTG BIT(1)
99 #define SSC_I2C_STOPG BIT(2)
100 #define SSC_I2C_ACKG BIT(3)
101 #define SSC_I2C_AD10 BIT(4)
102 #define SSC_I2C_TXENB BIT(5)
103 #define SSC_I2C_REPSTRTG BIT(11)
104 #define SSC_I2C_SLAVE_DISABLE BIT(12)
105
106 /* SSC Tx FIFO Status */
107 #define SSC_TX_FSTAT_STATUS 0x07
108
109 /* SSC Rx FIFO Status */
110 #define SSC_RX_FSTAT_STATUS 0x07
111
112 /* SSC Clear bit operation */
113 #define SSC_CLR_SSCAAS BIT(6)
114 #define SSC_CLR_SSCSTOP BIT(7)
115 #define SSC_CLR_SSCARBL BIT(8)
116 #define SSC_CLR_NACK BIT(10)
117 #define SSC_CLR_REPSTRT BIT(11)
118
119 /* SSC Clock Prescaler */
120 #define SSC_PRSC_VALUE 0x0f
121
122
123 #define SSC_TXFIFO_SIZE 0x8
124 #define SSC_RXFIFO_SIZE 0x8
125
126 enum st_i2c_mode {
127 I2C_MODE_STANDARD,
128 I2C_MODE_FAST,
129 I2C_MODE_END,
130 };
131
132 /**
133 * struct st_i2c_timings - per-Mode tuning parameters
134 * @rate: I2C bus rate
135 * @rep_start_hold: I2C repeated start hold time requirement
136 * @rep_start_setup: I2C repeated start set up time requirement
137 * @start_hold: I2C start hold time requirement
138 * @data_setup_time: I2C data set up time requirement
139 * @stop_setup_time: I2C stop set up time requirement
140 * @bus_free_time: I2C bus free time requirement
141 * @sda_pulse_min_limit: I2C SDA pulse mini width limit
142 */
143 struct st_i2c_timings {
144 u32 rate;
145 u32 rep_start_hold;
146 u32 rep_start_setup;
147 u32 start_hold;
148 u32 data_setup_time;
149 u32 stop_setup_time;
150 u32 bus_free_time;
151 u32 sda_pulse_min_limit;
152 };
153
154 /**
155 * struct st_i2c_client - client specific data
156 * @addr: 8-bit slave addr, including r/w bit
157 * @count: number of bytes to be transfered
158 * @xfered: number of bytes already transferred
159 * @buf: data buffer
160 * @result: result of the transfer
161 * @stop: last I2C msg to be sent, i.e. STOP to be generated
162 */
163 struct st_i2c_client {
164 u8 addr;
165 u32 count;
166 u32 xfered;
167 u8 *buf;
168 int result;
169 bool stop;
170 };
171
172 /**
173 * struct st_i2c_dev - private data of the controller
174 * @adap: I2C adapter for this controller
175 * @dev: device for this controller
176 * @base: virtual memory area
177 * @complete: completion of I2C message
178 * @irq: interrupt line for th controller
179 * @clk: hw ssc block clock
180 * @mode: I2C mode of the controller. Standard or Fast only supported
181 * @scl_min_width_us: SCL line minimum pulse width in us
182 * @sda_min_width_us: SDA line minimum pulse width in us
183 * @client: I2C transfert information
184 * @busy: I2C transfer on-going
185 */
186 struct st_i2c_dev {
187 struct i2c_adapter adap;
188 struct device *dev;
189 void __iomem *base;
190 struct completion complete;
191 int irq;
192 struct clk *clk;
193 int mode;
194 u32 scl_min_width_us;
195 u32 sda_min_width_us;
196 struct st_i2c_client client;
197 bool busy;
198 };
199
200 static inline void st_i2c_set_bits(void __iomem *reg, u32 mask)
201 {
202 writel_relaxed(readl_relaxed(reg) | mask, reg);
203 }
204
205 static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask)
206 {
207 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
208 }
209
210 /*
211 * From I2C Specifications v0.5.
212 *
213 * All the values below have +10% margin added to be
214 * compatible with some out-of-spec devices,
215 * like HDMI link of the Toshiba 19AV600 TV.
216 */
217 static struct st_i2c_timings i2c_timings[] = {
218 [I2C_MODE_STANDARD] = {
219 .rate = 100000,
220 .rep_start_hold = 4400,
221 .rep_start_setup = 5170,
222 .start_hold = 4400,
223 .data_setup_time = 275,
224 .stop_setup_time = 4400,
225 .bus_free_time = 5170,
226 },
227 [I2C_MODE_FAST] = {
228 .rate = 400000,
229 .rep_start_hold = 660,
230 .rep_start_setup = 660,
231 .start_hold = 660,
232 .data_setup_time = 110,
233 .stop_setup_time = 660,
234 .bus_free_time = 1430,
235 },
236 };
237
238 static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
239 {
240 int count, i;
241
242 /*
243 * Counter only counts up to 7 but fifo size is 8...
244 * When fifo is full, counter is 0 and RIR bit of status register is
245 * set
246 */
247 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
248 count = SSC_RXFIFO_SIZE;
249 else
250 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
251 SSC_RX_FSTAT_STATUS;
252
253 for (i = 0; i < count; i++)
254 readl_relaxed(i2c_dev->base + SSC_RBUF);
255 }
256
257 static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
258 {
259 /*
260 * FIFO needs to be emptied before reseting the IP,
261 * else the controller raises a BUSY error.
262 */
263 st_i2c_flush_rx_fifo(i2c_dev);
264
265 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
266 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
267 }
268
269 /**
270 * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
271 * @i2c_dev: Controller's private data
272 */
273 static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
274 {
275 unsigned long rate;
276 u32 val, ns_per_clk;
277 struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
278
279 st_i2c_soft_reset(i2c_dev);
280
281 val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL |
282 SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP;
283 writel_relaxed(val, i2c_dev->base + SSC_CLR);
284
285 /* SSC Control register setup */
286 val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9;
287 writel_relaxed(val, i2c_dev->base + SSC_CTL);
288
289 rate = clk_get_rate(i2c_dev->clk);
290 ns_per_clk = 1000000000 / rate;
291
292 /* Baudrate */
293 val = rate / (2 * t->rate);
294 writel_relaxed(val, i2c_dev->base + SSC_BRG);
295
296 /* Pre-scaler baudrate */
297 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
298
299 /* Enable I2C mode */
300 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
301
302 /* Repeated start hold time */
303 val = t->rep_start_hold / ns_per_clk;
304 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
305
306 /* Repeated start set up time */
307 val = t->rep_start_setup / ns_per_clk;
308 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
309
310 /* Start hold time */
311 val = t->start_hold / ns_per_clk;
312 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
313
314 /* Data set up time */
315 val = t->data_setup_time / ns_per_clk;
316 writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
317
318 /* Stop set up time */
319 val = t->stop_setup_time / ns_per_clk;
320 writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
321
322 /* Bus free time */
323 val = t->bus_free_time / ns_per_clk;
324 writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
325
326 /* Prescalers set up */
327 val = rate / 10000000;
328 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
329 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
330
331 /* Noise suppression witdh */
332 val = i2c_dev->scl_min_width_us * rate / 100000000;
333 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
334
335 /* Noise suppression max output data delay width */
336 val = i2c_dev->sda_min_width_us * rate / 100000000;
337 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
338 }
339
340 static int st_i2c_recover_bus(struct i2c_adapter *i2c_adap)
341 {
342 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
343 u32 ctl;
344
345 dev_dbg(i2c_dev->dev, "Trying to recover bus\n");
346
347 /*
348 * SSP IP is dual role SPI/I2C to generate 9 clock pulses
349 * we switch to SPI node, 9 bit words and write a 0. This
350 * has been validate with a oscilloscope and is easier
351 * than switching to GPIO mode.
352 */
353
354 /* Disable interrupts */
355 writel_relaxed(0, i2c_dev->base + SSC_IEN);
356
357 st_i2c_hw_config(i2c_dev);
358
359 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
360 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
361
362 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
363 usleep_range(8000, 10000);
364
365 writel_relaxed(0, i2c_dev->base + SSC_TBUF);
366 usleep_range(2000, 4000);
367 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
368
369 return 0;
370 }
371
372 static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev)
373 {
374 u32 sta;
375 int i, ret;
376
377 for (i = 0; i < 10; i++) {
378 sta = readl_relaxed(i2c_dev->base + SSC_STA);
379 if (!(sta & SSC_STA_BUSY))
380 return 0;
381
382 usleep_range(2000, 4000);
383 }
384
385 dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta);
386
387 ret = i2c_recover_bus(&i2c_dev->adap);
388 if (ret) {
389 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
390 return ret;
391 }
392
393 return -EBUSY;
394 }
395
396 /**
397 * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO
398 * @i2c_dev: Controller's private data
399 * @byte: Data to write in the Tx FIFO
400 */
401 static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte)
402 {
403 u16 tbuf = byte << 1;
404
405 writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
406 }
407
408 /**
409 * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode
410 * @i2c_dev: Controller's private data
411 *
412 * This functions fills the Tx FIFO with I2C transfert buffer when
413 * in write mode.
414 */
415 static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev)
416 {
417 struct st_i2c_client *c = &i2c_dev->client;
418 u32 tx_fstat, sta;
419 int i;
420
421 sta = readl_relaxed(i2c_dev->base + SSC_STA);
422 if (sta & SSC_STA_TX_FIFO_FULL)
423 return;
424
425 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
426 tx_fstat &= SSC_TX_FSTAT_STATUS;
427
428 if (c->count < (SSC_TXFIFO_SIZE - tx_fstat))
429 i = c->count;
430 else
431 i = SSC_TXFIFO_SIZE - tx_fstat;
432
433 for (; i > 0; i--, c->count--, c->buf++)
434 st_i2c_write_tx_fifo(i2c_dev, *c->buf);
435 }
436
437 /**
438 * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode
439 * @i2c_dev: Controller's private data
440 * @max: Maximum amount of data to fill into the Tx FIFO
441 *
442 * This functions fills the Tx FIFO with fixed pattern when
443 * in read mode to trigger clock.
444 */
445 static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, int max)
446 {
447 struct st_i2c_client *c = &i2c_dev->client;
448 u32 tx_fstat, sta;
449 int i;
450
451 sta = readl_relaxed(i2c_dev->base + SSC_STA);
452 if (sta & SSC_STA_TX_FIFO_FULL)
453 return;
454
455 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
456 tx_fstat &= SSC_TX_FSTAT_STATUS;
457
458 if (max < (SSC_TXFIFO_SIZE - tx_fstat))
459 i = max;
460 else
461 i = SSC_TXFIFO_SIZE - tx_fstat;
462
463 for (; i > 0; i--, c->xfered++)
464 st_i2c_write_tx_fifo(i2c_dev, 0xff);
465 }
466
467 static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev)
468 {
469 struct st_i2c_client *c = &i2c_dev->client;
470 u32 i, sta;
471 u16 rbuf;
472
473 sta = readl_relaxed(i2c_dev->base + SSC_STA);
474 if (sta & SSC_STA_RIR) {
475 i = SSC_RXFIFO_SIZE;
476 } else {
477 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT);
478 i &= SSC_RX_FSTAT_STATUS;
479 }
480
481 for (; (i > 0) && (c->count > 0); i--, c->count--) {
482 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1;
483 *c->buf++ = (u8)rbuf & 0xff;
484 }
485
486 if (i) {
487 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i);
488 st_i2c_flush_rx_fifo(i2c_dev);
489 }
490 }
491
492 /**
493 * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition
494 * @i2c_dev: Controller's private data
495 */
496 static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev)
497 {
498 struct st_i2c_client *c = &i2c_dev->client;
499
500 st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN);
501 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
502
503 if (c->stop) {
504 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN);
505 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
506 } else {
507 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN);
508 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG);
509 }
510 }
511
512 /**
513 * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write
514 * @i2c_dev: Controller's private data
515 */
516 static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev)
517 {
518 struct st_i2c_client *c = &i2c_dev->client;
519
520 st_i2c_flush_rx_fifo(i2c_dev);
521
522 if (!c->count)
523 /* End of xfer, send stop or repstart */
524 st_i2c_terminate_xfer(i2c_dev);
525 else
526 st_i2c_wr_fill_tx_fifo(i2c_dev);
527 }
528
529 /**
530 * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read
531 * @i2c_dev: Controller's private data
532 */
533 static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
534 {
535 struct st_i2c_client *c = &i2c_dev->client;
536 u32 ien;
537
538 /* Trash the address read back */
539 if (!c->xfered) {
540 readl_relaxed(i2c_dev->base + SSC_RBUF);
541 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB);
542 } else {
543 st_i2c_read_rx_fifo(i2c_dev);
544 }
545
546 if (!c->count) {
547 /* End of xfer, send stop or repstart */
548 st_i2c_terminate_xfer(i2c_dev);
549 } else if (c->count == 1) {
550 /* Penultimate byte to xfer, disable ACK gen. */
551 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG);
552
553 /* Last received byte is to be handled by NACK interrupt */
554 ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN;
555 writel_relaxed(ien, i2c_dev->base + SSC_IEN);
556
557 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count);
558 } else {
559 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1);
560 }
561 }
562
563 /**
564 * st_i2c_isr() - Interrupt routine
565 * @irq: interrupt number
566 * @data: Controller's private data
567 */
568 static irqreturn_t st_i2c_isr_thread(int irq, void *data)
569 {
570 struct st_i2c_dev *i2c_dev = data;
571 struct st_i2c_client *c = &i2c_dev->client;
572 u32 sta, ien;
573 int it;
574
575 ien = readl_relaxed(i2c_dev->base + SSC_IEN);
576 sta = readl_relaxed(i2c_dev->base + SSC_STA);
577
578 /* Use __fls() to check error bits first */
579 it = __fls(sta & ien);
580 if (it < 0) {
581 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n",
582 sta, ien);
583 return IRQ_NONE;
584 }
585
586 switch (1 << it) {
587 case SSC_STA_TE:
588 if (c->addr & I2C_M_RD)
589 st_i2c_handle_read(i2c_dev);
590 else
591 st_i2c_handle_write(i2c_dev);
592 break;
593
594 case SSC_STA_STOP:
595 case SSC_STA_REPSTRT:
596 writel_relaxed(0, i2c_dev->base + SSC_IEN);
597 complete(&i2c_dev->complete);
598 break;
599
600 case SSC_STA_NACK:
601 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
602
603 /* Last received byte handled by NACK interrupt */
604 if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) {
605 st_i2c_handle_read(i2c_dev);
606 break;
607 }
608
609 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
610 writel_relaxed(it, i2c_dev->base + SSC_IEN);
611
612 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
613 c->result = -EIO;
614 break;
615
616 case SSC_STA_ARBL:
617 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
618
619 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
620 writel_relaxed(it, i2c_dev->base + SSC_IEN);
621
622 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
623 c->result = -EAGAIN;
624 break;
625
626 default:
627 dev_err(i2c_dev->dev,
628 "it %d unhandled (sta=0x%04x)\n", it, sta);
629 }
630
631 /*
632 * Read IEN register to ensure interrupt mask write is effective
633 * before re-enabling interrupt at GIC level, and thus avoid spurious
634 * interrupts.
635 */
636 readl(i2c_dev->base + SSC_IEN);
637
638 return IRQ_HANDLED;
639 }
640
641 /**
642 * st_i2c_xfer_msg() - Transfer a single I2C message
643 * @i2c_dev: Controller's private data
644 * @msg: I2C message to transfer
645 * @is_first: first message of the sequence
646 * @is_last: last message of the sequence
647 */
648 static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg,
649 bool is_first, bool is_last)
650 {
651 struct st_i2c_client *c = &i2c_dev->client;
652 u32 ctl, i2c, it;
653 unsigned long timeout;
654 int ret;
655
656 c->addr = i2c_8bit_addr_from_msg(msg);
657 c->buf = msg->buf;
658 c->count = msg->len;
659 c->xfered = 0;
660 c->result = 0;
661 c->stop = is_last;
662
663 reinit_completion(&i2c_dev->complete);
664
665 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
666 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
667
668 i2c = SSC_I2C_TXENB;
669 if (c->addr & I2C_M_RD)
670 i2c |= SSC_I2C_ACKG;
671 st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c);
672
673 /* Write slave address */
674 st_i2c_write_tx_fifo(i2c_dev, c->addr);
675
676 /* Pre-fill Tx fifo with data in case of write */
677 if (!(c->addr & I2C_M_RD))
678 st_i2c_wr_fill_tx_fifo(i2c_dev);
679
680 it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN;
681 writel_relaxed(it, i2c_dev->base + SSC_IEN);
682
683 if (is_first) {
684 ret = st_i2c_wait_free_bus(i2c_dev);
685 if (ret)
686 return ret;
687
688 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
689 }
690
691 timeout = wait_for_completion_timeout(&i2c_dev->complete,
692 i2c_dev->adap.timeout);
693 ret = c->result;
694
695 if (!timeout) {
696 dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n",
697 c->addr);
698 ret = -ETIMEDOUT;
699 }
700
701 i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG;
702 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c);
703
704 writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT,
705 i2c_dev->base + SSC_CLR);
706
707 return ret;
708 }
709
710 /**
711 * st_i2c_xfer() - Transfer a single I2C message
712 * @i2c_adap: Adapter pointer to the controller
713 * @msgs: Pointer to data to be written.
714 * @num: Number of messages to be executed
715 */
716 static int st_i2c_xfer(struct i2c_adapter *i2c_adap,
717 struct i2c_msg msgs[], int num)
718 {
719 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
720 int ret, i;
721
722 i2c_dev->busy = true;
723
724 ret = clk_prepare_enable(i2c_dev->clk);
725 if (ret) {
726 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
727 return ret;
728 }
729
730 pinctrl_pm_select_default_state(i2c_dev->dev);
731
732 st_i2c_hw_config(i2c_dev);
733
734 for (i = 0; (i < num) && !ret; i++)
735 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1);
736
737 pinctrl_pm_select_idle_state(i2c_dev->dev);
738
739 clk_disable_unprepare(i2c_dev->clk);
740
741 i2c_dev->busy = false;
742
743 return (ret < 0) ? ret : i;
744 }
745
746 #ifdef CONFIG_PM_SLEEP
747 static int st_i2c_suspend(struct device *dev)
748 {
749 struct st_i2c_dev *i2c_dev = dev_get_drvdata(dev);
750
751 if (i2c_dev->busy)
752 return -EBUSY;
753
754 pinctrl_pm_select_sleep_state(dev);
755
756 return 0;
757 }
758
759 static int st_i2c_resume(struct device *dev)
760 {
761 pinctrl_pm_select_default_state(dev);
762 /* Go in idle state if available */
763 pinctrl_pm_select_idle_state(dev);
764
765 return 0;
766 }
767
768 static SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume);
769 #define ST_I2C_PM (&st_i2c_pm)
770 #else
771 #define ST_I2C_PM NULL
772 #endif
773
774 static u32 st_i2c_func(struct i2c_adapter *adap)
775 {
776 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
777 }
778
779 static const struct i2c_algorithm st_i2c_algo = {
780 .master_xfer = st_i2c_xfer,
781 .functionality = st_i2c_func,
782 };
783
784 static struct i2c_bus_recovery_info st_i2c_recovery_info = {
785 .recover_bus = st_i2c_recover_bus,
786 };
787
788 static int st_i2c_of_get_deglitch(struct device_node *np,
789 struct st_i2c_dev *i2c_dev)
790 {
791 int ret;
792
793 ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us",
794 &i2c_dev->scl_min_width_us);
795 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
796 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n");
797 return ret;
798 }
799
800 ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us",
801 &i2c_dev->sda_min_width_us);
802 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
803 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n");
804 return ret;
805 }
806
807 return 0;
808 }
809
810 static int st_i2c_probe(struct platform_device *pdev)
811 {
812 struct device_node *np = pdev->dev.of_node;
813 struct st_i2c_dev *i2c_dev;
814 struct resource *res;
815 u32 clk_rate;
816 struct i2c_adapter *adap;
817 int ret;
818
819 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
820 if (!i2c_dev)
821 return -ENOMEM;
822
823 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
824 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
825 if (IS_ERR(i2c_dev->base))
826 return PTR_ERR(i2c_dev->base);
827
828 i2c_dev->irq = irq_of_parse_and_map(np, 0);
829 if (!i2c_dev->irq) {
830 dev_err(&pdev->dev, "IRQ missing or invalid\n");
831 return -EINVAL;
832 }
833
834 i2c_dev->clk = of_clk_get_by_name(np, "ssc");
835 if (IS_ERR(i2c_dev->clk)) {
836 dev_err(&pdev->dev, "Unable to request clock\n");
837 return PTR_ERR(i2c_dev->clk);
838 }
839
840 i2c_dev->mode = I2C_MODE_STANDARD;
841 ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
842 if ((!ret) && (clk_rate == 400000))
843 i2c_dev->mode = I2C_MODE_FAST;
844
845 i2c_dev->dev = &pdev->dev;
846
847 ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq,
848 NULL, st_i2c_isr_thread,
849 IRQF_ONESHOT, pdev->name, i2c_dev);
850 if (ret) {
851 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
852 return ret;
853 }
854
855 pinctrl_pm_select_default_state(i2c_dev->dev);
856 /* In case idle state available, select it */
857 pinctrl_pm_select_idle_state(i2c_dev->dev);
858
859 ret = st_i2c_of_get_deglitch(np, i2c_dev);
860 if (ret)
861 return ret;
862
863 adap = &i2c_dev->adap;
864 i2c_set_adapdata(adap, i2c_dev);
865 snprintf(adap->name, sizeof(adap->name), "ST I2C(%pa)", &res->start);
866 adap->owner = THIS_MODULE;
867 adap->timeout = 2 * HZ;
868 adap->retries = 0;
869 adap->algo = &st_i2c_algo;
870 adap->bus_recovery_info = &st_i2c_recovery_info;
871 adap->dev.parent = &pdev->dev;
872 adap->dev.of_node = pdev->dev.of_node;
873
874 init_completion(&i2c_dev->complete);
875
876 ret = i2c_add_adapter(adap);
877 if (ret)
878 return ret;
879
880 platform_set_drvdata(pdev, i2c_dev);
881
882 dev_info(i2c_dev->dev, "%s initialized\n", adap->name);
883
884 return 0;
885 }
886
887 static int st_i2c_remove(struct platform_device *pdev)
888 {
889 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
890
891 i2c_del_adapter(&i2c_dev->adap);
892
893 return 0;
894 }
895
896 static const struct of_device_id st_i2c_match[] = {
897 { .compatible = "st,comms-ssc-i2c", },
898 { .compatible = "st,comms-ssc4-i2c", },
899 {},
900 };
901 MODULE_DEVICE_TABLE(of, st_i2c_match);
902
903 static struct platform_driver st_i2c_driver = {
904 .driver = {
905 .name = "st-i2c",
906 .of_match_table = st_i2c_match,
907 .pm = ST_I2C_PM,
908 },
909 .probe = st_i2c_probe,
910 .remove = st_i2c_remove,
911 };
912
913 module_platform_driver(st_i2c_driver);
914
915 MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>");
916 MODULE_DESCRIPTION("STMicroelectronics I2C driver");
917 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support