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Linux 4.19.133
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-tegra.c
blobaf06198851f1b185c50c584a177426e736f0d3a5
1 /*
2 * drivers/i2c/busses/i2c-tegra.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
24 #include <linux/io.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/module.h>
30 #include <linux/reset.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/iopoll.h>
34
35 #include <asm/unaligned.h>
36
37 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
38 #define BYTES_PER_FIFO_WORD 4
39
40 #define I2C_CNFG 0x000
41 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
42 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
43 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
44 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
45 #define I2C_STATUS 0x01C
46 #define I2C_SL_CNFG 0x020
47 #define I2C_SL_CNFG_NACK BIT(1)
48 #define I2C_SL_CNFG_NEWSL BIT(2)
49 #define I2C_SL_ADDR1 0x02c
50 #define I2C_SL_ADDR2 0x030
51 #define I2C_TX_FIFO 0x050
52 #define I2C_RX_FIFO 0x054
53 #define I2C_PACKET_TRANSFER_STATUS 0x058
54 #define I2C_FIFO_CONTROL 0x05c
55 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
56 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
57 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
58 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
59 #define I2C_FIFO_STATUS 0x060
60 #define I2C_FIFO_STATUS_TX_MASK 0xF0
61 #define I2C_FIFO_STATUS_TX_SHIFT 4
62 #define I2C_FIFO_STATUS_RX_MASK 0x0F
63 #define I2C_FIFO_STATUS_RX_SHIFT 0
64 #define I2C_INT_MASK 0x064
65 #define I2C_INT_STATUS 0x068
66 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
67 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE BIT(6)
68 #define I2C_INT_TX_FIFO_OVERFLOW BIT(5)
69 #define I2C_INT_RX_FIFO_UNDERFLOW BIT(4)
70 #define I2C_INT_NO_ACK BIT(3)
71 #define I2C_INT_ARBITRATION_LOST BIT(2)
72 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
73 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
74 #define I2C_CLK_DIVISOR 0x06c
75 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
76 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
77
78 #define DVC_CTRL_REG1 0x000
79 #define DVC_CTRL_REG1_INTR_EN BIT(10)
80 #define DVC_CTRL_REG2 0x004
81 #define DVC_CTRL_REG3 0x008
82 #define DVC_CTRL_REG3_SW_PROG BIT(26)
83 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
84 #define DVC_STATUS 0x00c
85 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
86
87 #define I2C_ERR_NONE 0x00
88 #define I2C_ERR_NO_ACK 0x01
89 #define I2C_ERR_ARBITRATION_LOST 0x02
90 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
91
92 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
93 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
94 #define PACKET_HEADER0_CONT_ID_SHIFT 12
95 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4)
96
97 #define I2C_HEADER_HIGHSPEED_MODE BIT(22)
98 #define I2C_HEADER_CONT_ON_NAK BIT(21)
99 #define I2C_HEADER_SEND_START_BYTE BIT(20)
100 #define I2C_HEADER_READ BIT(19)
101 #define I2C_HEADER_10BIT_ADDR BIT(18)
102 #define I2C_HEADER_IE_ENABLE BIT(17)
103 #define I2C_HEADER_REPEAT_START BIT(16)
104 #define I2C_HEADER_CONTINUE_XFER BIT(15)
105 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
106 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
107
108 #define I2C_CONFIG_LOAD 0x08C
109 #define I2C_MSTR_CONFIG_LOAD BIT(0)
110 #define I2C_SLV_CONFIG_LOAD BIT(1)
111 #define I2C_TIMEOUT_CONFIG_LOAD BIT(2)
112
113 #define I2C_CLKEN_OVERRIDE 0x090
114 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
115
116 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
117
118 #define I2C_MST_FIFO_CONTROL 0x0b4
119 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
120 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
121 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
122 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
123
124 #define I2C_MST_FIFO_STATUS 0x0b8
125 #define I2C_MST_FIFO_STATUS_RX_MASK 0xff
126 #define I2C_MST_FIFO_STATUS_RX_SHIFT 0
127 #define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000
128 #define I2C_MST_FIFO_STATUS_TX_SHIFT 16
129
130 /*
131 * msg_end_type: The bus control which need to be send at end of transfer.
132 * @MSG_END_STOP: Send stop pulse at end of transfer.
133 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
134 * @MSG_END_CONTINUE: The following on message is coming and so do not send
135 * stop or repeat start.
136 */
137 enum msg_end_type {
138 MSG_END_STOP,
139 MSG_END_REPEAT_START,
140 MSG_END_CONTINUE,
141 };
142
143 /**
144 * struct tegra_i2c_hw_feature : Different HW support on Tegra
145 * @has_continue_xfer_support: Continue transfer supports.
146 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
147 * complete interrupt per packet basis.
148 * @has_single_clk_source: The I2C controller has single clock source. Tegra30
149 * and earlier SoCs have two clock sources i.e. div-clk and
150 * fast-clk.
151 * @has_config_load_reg: Has the config load register to load the new
152 * configuration.
153 * @clk_divisor_hs_mode: Clock divisor in HS mode.
154 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
155 * applicable if there is no fast clock source i.e. single clock
156 * source.
157 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
158 * applicable if there is no fast clock source (i.e. single
159 * clock source).
160 * @has_multi_master_mode: The I2C controller supports running in single-master
161 * or multi-master mode.
162 * @has_slcg_override_reg: The I2C controller supports a register that
163 * overrides the second level clock gating.
164 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
165 * provides additional features and allows for longer messages to
166 * be transferred in one go.
167 * @quirks: i2c adapter quirks for limiting write/read transfer size and not
168 * allowing 0 length transfers.
169 */
170 struct tegra_i2c_hw_feature {
171 bool has_continue_xfer_support;
172 bool has_per_pkt_xfer_complete_irq;
173 bool has_single_clk_source;
174 bool has_config_load_reg;
175 int clk_divisor_hs_mode;
176 int clk_divisor_std_fast_mode;
177 u16 clk_divisor_fast_plus_mode;
178 bool has_multi_master_mode;
179 bool has_slcg_override_reg;
180 bool has_mst_fifo;
181 const struct i2c_adapter_quirks *quirks;
182 };
183
184 /**
185 * struct tegra_i2c_dev - per device I2C context
186 * @dev: device reference for power management
187 * @hw: Tegra I2C HW feature
188 * @adapter: core I2C layer adapter information
189 * @div_clk: clock reference for div clock of I2C controller
190 * @fast_clk: clock reference for fast clock of I2C controller
191 * @rst: reset control for the I2C controller
192 * @base: ioremapped registers cookie
193 * @cont_id: I2C controller ID, used for packet header
194 * @irq: IRQ number of transfer complete interrupt
195 * @irq_disabled: used to track whether or not the interrupt is enabled
196 * @is_dvc: identifies the DVC I2C controller, has a different register layout
197 * @msg_complete: transfer completion notifier
198 * @msg_err: error code for completed message
199 * @msg_buf: pointer to current message data
200 * @msg_buf_remaining: size of unsent data in the message buffer
201 * @msg_read: identifies read transfers
202 * @bus_clk_rate: current I2C bus clock rate
203 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
204 * @is_multimaster_mode: track if I2C controller is in multi-master mode
205 * @xfer_lock: lock to serialize transfer submission and processing
206 */
207 struct tegra_i2c_dev {
208 struct device *dev;
209 const struct tegra_i2c_hw_feature *hw;
210 struct i2c_adapter adapter;
211 struct clk *div_clk;
212 struct clk *fast_clk;
213 struct reset_control *rst;
214 void __iomem *base;
215 int cont_id;
216 int irq;
217 bool irq_disabled;
218 int is_dvc;
219 struct completion msg_complete;
220 int msg_err;
221 u8 *msg_buf;
222 size_t msg_buf_remaining;
223 int msg_read;
224 u32 bus_clk_rate;
225 u16 clk_divisor_non_hs_mode;
226 bool is_multimaster_mode;
227 spinlock_t xfer_lock;
228 };
229
230 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
231 unsigned long reg)
232 {
233 writel(val, i2c_dev->base + reg);
234 }
235
236 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
237 {
238 return readl(i2c_dev->base + reg);
239 }
240
241 /*
242 * i2c_writel and i2c_readl will offset the register if necessary to talk
243 * to the I2C block inside the DVC block
244 */
245 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
246 unsigned long reg)
247 {
248 if (i2c_dev->is_dvc)
249 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
250 return reg;
251 }
252
253 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
254 unsigned long reg)
255 {
256 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
257
258 /* Read back register to make sure that register writes completed */
259 if (reg != I2C_TX_FIFO)
260 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
261 }
262
263 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
264 {
265 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
266 }
267
268 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
269 unsigned long reg, int len)
270 {
271 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
272 }
273
274 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
275 unsigned long reg, int len)
276 {
277 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
278 }
279
280 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
281 {
282 u32 int_mask;
283
284 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
285 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
286 }
287
288 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
289 {
290 u32 int_mask;
291
292 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
293 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
294 }
295
296 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
297 {
298 unsigned long timeout = jiffies + HZ;
299 unsigned int offset;
300 u32 mask, val;
301
302 if (i2c_dev->hw->has_mst_fifo) {
303 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
304 I2C_MST_FIFO_CONTROL_RX_FLUSH;
305 offset = I2C_MST_FIFO_CONTROL;
306 } else {
307 mask = I2C_FIFO_CONTROL_TX_FLUSH |
308 I2C_FIFO_CONTROL_RX_FLUSH;
309 offset = I2C_FIFO_CONTROL;
310 }
311
312 val = i2c_readl(i2c_dev, offset);
313 val |= mask;
314 i2c_writel(i2c_dev, val, offset);
315
316 while (i2c_readl(i2c_dev, offset) & mask) {
317 if (time_after(jiffies, timeout)) {
318 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
319 return -ETIMEDOUT;
320 }
321 msleep(1);
322 }
323 return 0;
324 }
325
326 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
327 {
328 u32 val;
329 int rx_fifo_avail;
330 u8 *buf = i2c_dev->msg_buf;
331 size_t buf_remaining = i2c_dev->msg_buf_remaining;
332 int words_to_transfer;
333
334 if (i2c_dev->hw->has_mst_fifo) {
335 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
336 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >>
337 I2C_MST_FIFO_STATUS_RX_SHIFT;
338 } else {
339 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
340 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
341 I2C_FIFO_STATUS_RX_SHIFT;
342 }
343
344 /* Rounds down to not include partial word at the end of buf */
345 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
346 if (words_to_transfer > rx_fifo_avail)
347 words_to_transfer = rx_fifo_avail;
348
349 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
350
351 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
352 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
353 rx_fifo_avail -= words_to_transfer;
354
355 /*
356 * If there is a partial word at the end of buf, handle it manually to
357 * prevent overwriting past the end of buf
358 */
359 if (rx_fifo_avail > 0 && buf_remaining > 0) {
360 BUG_ON(buf_remaining > 3);
361 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
362 val = cpu_to_le32(val);
363 memcpy(buf, &val, buf_remaining);
364 buf_remaining = 0;
365 rx_fifo_avail--;
366 }
367
368 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
369 i2c_dev->msg_buf_remaining = buf_remaining;
370 i2c_dev->msg_buf = buf;
371
372 return 0;
373 }
374
375 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
376 {
377 u32 val;
378 int tx_fifo_avail;
379 u8 *buf = i2c_dev->msg_buf;
380 size_t buf_remaining = i2c_dev->msg_buf_remaining;
381 int words_to_transfer;
382
383 if (i2c_dev->hw->has_mst_fifo) {
384 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
385 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >>
386 I2C_MST_FIFO_STATUS_TX_SHIFT;
387 } else {
388 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
389 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
390 I2C_FIFO_STATUS_TX_SHIFT;
391 }
392
393 /* Rounds down to not include partial word at the end of buf */
394 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
395
396 /* It's very common to have < 4 bytes, so optimize that case. */
397 if (words_to_transfer) {
398 if (words_to_transfer > tx_fifo_avail)
399 words_to_transfer = tx_fifo_avail;
400
401 /*
402 * Update state before writing to FIFO. If this casues us
403 * to finish writing all bytes (AKA buf_remaining goes to 0) we
404 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
405 * not maskable). We need to make sure that the isr sees
406 * buf_remaining as 0 and doesn't call us back re-entrantly.
407 */
408 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
409 tx_fifo_avail -= words_to_transfer;
410 i2c_dev->msg_buf_remaining = buf_remaining;
411 i2c_dev->msg_buf = buf +
412 words_to_transfer * BYTES_PER_FIFO_WORD;
413 barrier();
414
415 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
416
417 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
418 }
419
420 /*
421 * If there is a partial word at the end of buf, handle it manually to
422 * prevent reading past the end of buf, which could cross a page
423 * boundary and fault.
424 */
425 if (tx_fifo_avail > 0 && buf_remaining > 0) {
426 BUG_ON(buf_remaining > 3);
427 memcpy(&val, buf, buf_remaining);
428 val = le32_to_cpu(val);
429
430 /* Again update before writing to FIFO to make sure isr sees. */
431 i2c_dev->msg_buf_remaining = 0;
432 i2c_dev->msg_buf = NULL;
433 barrier();
434
435 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
436 }
437
438 return 0;
439 }
440
441 /*
442 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
443 * block. This block is identical to the rest of the I2C blocks, except that
444 * it only supports master mode, it has registers moved around, and it needs
445 * some extra init to get it into I2C mode. The register moves are handled
446 * by i2c_readl and i2c_writel
447 */
448 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
449 {
450 u32 val;
451
452 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
453 val |= DVC_CTRL_REG3_SW_PROG;
454 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
455 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
456
457 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
458 val |= DVC_CTRL_REG1_INTR_EN;
459 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
460 }
461
462 static int tegra_i2c_runtime_resume(struct device *dev)
463 {
464 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
465 int ret;
466
467 ret = pinctrl_pm_select_default_state(i2c_dev->dev);
468 if (ret)
469 return ret;
470
471 if (!i2c_dev->hw->has_single_clk_source) {
472 ret = clk_enable(i2c_dev->fast_clk);
473 if (ret < 0) {
474 dev_err(i2c_dev->dev,
475 "Enabling fast clk failed, err %d\n", ret);
476 return ret;
477 }
478 }
479
480 ret = clk_enable(i2c_dev->div_clk);
481 if (ret < 0) {
482 dev_err(i2c_dev->dev,
483 "Enabling div clk failed, err %d\n", ret);
484 clk_disable(i2c_dev->fast_clk);
485 return ret;
486 }
487
488 return 0;
489 }
490
491 static int tegra_i2c_runtime_suspend(struct device *dev)
492 {
493 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
494
495 clk_disable(i2c_dev->div_clk);
496 if (!i2c_dev->hw->has_single_clk_source)
497 clk_disable(i2c_dev->fast_clk);
498
499 return pinctrl_pm_select_idle_state(i2c_dev->dev);
500 }
501
502 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
503 {
504 unsigned long reg_offset;
505 void __iomem *addr;
506 u32 val;
507 int err;
508
509 if (i2c_dev->hw->has_config_load_reg) {
510 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
511 addr = i2c_dev->base + reg_offset;
512 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
513 if (in_interrupt())
514 err = readl_poll_timeout_atomic(addr, val, val == 0,
515 1000, I2C_CONFIG_LOAD_TIMEOUT);
516 else
517 err = readl_poll_timeout(addr, val, val == 0,
518 1000, I2C_CONFIG_LOAD_TIMEOUT);
519
520 if (err) {
521 dev_warn(i2c_dev->dev,
522 "timeout waiting for config load\n");
523 return err;
524 }
525 }
526
527 return 0;
528 }
529
530 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
531 {
532 u32 val;
533 int err;
534 u32 clk_divisor;
535
536 err = pm_runtime_get_sync(i2c_dev->dev);
537 if (err < 0) {
538 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err);
539 return err;
540 }
541
542 reset_control_assert(i2c_dev->rst);
543 udelay(2);
544 reset_control_deassert(i2c_dev->rst);
545
546 if (i2c_dev->is_dvc)
547 tegra_dvc_init(i2c_dev);
548
549 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
550 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
551
552 if (i2c_dev->hw->has_multi_master_mode)
553 val |= I2C_CNFG_MULTI_MASTER_MODE;
554
555 i2c_writel(i2c_dev, val, I2C_CNFG);
556 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
557
558 /* Make sure clock divisor programmed correctly */
559 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
560 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode <<
561 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
562 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
563
564 if (!i2c_dev->is_dvc) {
565 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
566
567 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
568 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
569 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
570 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
571 }
572
573 if (i2c_dev->hw->has_mst_fifo) {
574 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
575 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
576 i2c_writel(i2c_dev, val, I2C_MST_FIFO_CONTROL);
577 } else {
578 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
579 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
580 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
581 }
582
583 err = tegra_i2c_flush_fifos(i2c_dev);
584 if (err)
585 goto err;
586
587 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
588 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
589
590 err = tegra_i2c_wait_for_config_load(i2c_dev);
591 if (err)
592 goto err;
593
594 if (i2c_dev->irq_disabled) {
595 i2c_dev->irq_disabled = false;
596 enable_irq(i2c_dev->irq);
597 }
598
599 err:
600 pm_runtime_put(i2c_dev->dev);
601 return err;
602 }
603
604 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
605 {
606 u32 cnfg;
607
608 /*
609 * NACK interrupt is generated before the I2C controller generates
610 * the STOP condition on the bus. So wait for 2 clock periods
611 * before disabling the controller so that the STOP condition has
612 * been delivered properly.
613 */
614 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
615
616 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
617 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
618 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
619
620 return tegra_i2c_wait_for_config_load(i2c_dev);
621 }
622
623 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
624 {
625 u32 status;
626 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
627 struct tegra_i2c_dev *i2c_dev = dev_id;
628 unsigned long flags;
629
630 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
631
632 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
633 if (status == 0) {
634 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
635 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
636 i2c_readl(i2c_dev, I2C_STATUS),
637 i2c_readl(i2c_dev, I2C_CNFG));
638 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
639
640 if (!i2c_dev->irq_disabled) {
641 disable_irq_nosync(i2c_dev->irq);
642 i2c_dev->irq_disabled = true;
643 }
644 goto err;
645 }
646
647 if (unlikely(status & status_err)) {
648 tegra_i2c_disable_packet_mode(i2c_dev);
649 if (status & I2C_INT_NO_ACK)
650 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
651 if (status & I2C_INT_ARBITRATION_LOST)
652 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
653 goto err;
654 }
655
656 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
657 if (i2c_dev->msg_buf_remaining)
658 tegra_i2c_empty_rx_fifo(i2c_dev);
659 else
660 BUG();
661 }
662
663 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
664 if (i2c_dev->msg_buf_remaining)
665 tegra_i2c_fill_tx_fifo(i2c_dev);
666 else
667 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
668 }
669
670 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
671 if (i2c_dev->is_dvc)
672 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
673
674 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
675 BUG_ON(i2c_dev->msg_buf_remaining);
676 complete(&i2c_dev->msg_complete);
677 }
678 goto done;
679 err:
680 /* An error occurred, mask all interrupts */
681 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
682 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
683 I2C_INT_RX_FIFO_DATA_REQ);
684 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
685 if (i2c_dev->is_dvc)
686 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
687
688 complete(&i2c_dev->msg_complete);
689 done:
690 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
691 return IRQ_HANDLED;
692 }
693
694 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
695 struct i2c_msg *msg, enum msg_end_type end_state)
696 {
697 u32 packet_header;
698 u32 int_mask;
699 unsigned long time_left;
700 unsigned long flags;
701
702 tegra_i2c_flush_fifos(i2c_dev);
703
704 i2c_dev->msg_buf = msg->buf;
705 i2c_dev->msg_buf_remaining = msg->len;
706 i2c_dev->msg_err = I2C_ERR_NONE;
707 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
708 reinit_completion(&i2c_dev->msg_complete);
709
710 spin_lock_irqsave(&i2c_dev->xfer_lock, flags);
711
712 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
713 tegra_i2c_unmask_irq(i2c_dev, int_mask);
714
715 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
716 PACKET_HEADER0_PROTOCOL_I2C |
717 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
718 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
719 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
720
721 packet_header = msg->len - 1;
722 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
723
724 packet_header = I2C_HEADER_IE_ENABLE;
725 if (end_state == MSG_END_CONTINUE)
726 packet_header |= I2C_HEADER_CONTINUE_XFER;
727 else if (end_state == MSG_END_REPEAT_START)
728 packet_header |= I2C_HEADER_REPEAT_START;
729 if (msg->flags & I2C_M_TEN) {
730 packet_header |= msg->addr;
731 packet_header |= I2C_HEADER_10BIT_ADDR;
732 } else {
733 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
734 }
735 if (msg->flags & I2C_M_IGNORE_NAK)
736 packet_header |= I2C_HEADER_CONT_ON_NAK;
737 if (msg->flags & I2C_M_RD)
738 packet_header |= I2C_HEADER_READ;
739 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
740
741 if (!(msg->flags & I2C_M_RD))
742 tegra_i2c_fill_tx_fifo(i2c_dev);
743
744 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
745 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
746 if (msg->flags & I2C_M_RD)
747 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
748 else if (i2c_dev->msg_buf_remaining)
749 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
750
751 tegra_i2c_unmask_irq(i2c_dev, int_mask);
752 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags);
753 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
754 i2c_readl(i2c_dev, I2C_INT_MASK));
755
756 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
757 TEGRA_I2C_TIMEOUT);
758 tegra_i2c_mask_irq(i2c_dev, int_mask);
759
760 if (time_left == 0) {
761 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
762
763 tegra_i2c_init(i2c_dev);
764 return -ETIMEDOUT;
765 }
766
767 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
768 time_left, completion_done(&i2c_dev->msg_complete),
769 i2c_dev->msg_err);
770
771 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
772 return 0;
773
774 tegra_i2c_init(i2c_dev);
775 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
776 if (msg->flags & I2C_M_IGNORE_NAK)
777 return 0;
778 return -EREMOTEIO;
779 }
780
781 return -EIO;
782 }
783
784 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
785 int num)
786 {
787 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
788 int i;
789 int ret = 0;
790
791 ret = pm_runtime_get_sync(i2c_dev->dev);
792 if (ret < 0) {
793 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
794 return ret;
795 }
796
797 for (i = 0; i < num; i++) {
798 enum msg_end_type end_type = MSG_END_STOP;
799
800 if (i < (num - 1)) {
801 if (msgs[i + 1].flags & I2C_M_NOSTART)
802 end_type = MSG_END_CONTINUE;
803 else
804 end_type = MSG_END_REPEAT_START;
805 }
806 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
807 if (ret)
808 break;
809 }
810
811 pm_runtime_put(i2c_dev->dev);
812
813 return ret ?: i;
814 }
815
816 static u32 tegra_i2c_func(struct i2c_adapter *adap)
817 {
818 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
819 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
820 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
821
822 if (i2c_dev->hw->has_continue_xfer_support)
823 ret |= I2C_FUNC_NOSTART;
824 return ret;
825 }
826
827 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
828 {
829 struct device_node *np = i2c_dev->dev->of_node;
830 int ret;
831
832 ret = of_property_read_u32(np, "clock-frequency",
833 &i2c_dev->bus_clk_rate);
834 if (ret)
835 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
836
837 i2c_dev->is_multimaster_mode = of_property_read_bool(np,
838 "multi-master");
839 }
840
841 static const struct i2c_algorithm tegra_i2c_algo = {
842 .master_xfer = tegra_i2c_xfer,
843 .functionality = tegra_i2c_func,
844 };
845
846 /* payload size is only 12 bit */
847 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
848 .flags = I2C_AQ_NO_ZERO_LEN,
849 .max_read_len = 4096,
850 .max_write_len = 4096 - 12,
851 };
852
853 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
854 .flags = I2C_AQ_NO_ZERO_LEN,
855 };
856
857 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
858 .has_continue_xfer_support = false,
859 .has_per_pkt_xfer_complete_irq = false,
860 .has_single_clk_source = false,
861 .clk_divisor_hs_mode = 3,
862 .clk_divisor_std_fast_mode = 0,
863 .clk_divisor_fast_plus_mode = 0,
864 .has_config_load_reg = false,
865 .has_multi_master_mode = false,
866 .has_slcg_override_reg = false,
867 .has_mst_fifo = false,
868 .quirks = &tegra_i2c_quirks,
869 };
870
871 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
872 .has_continue_xfer_support = true,
873 .has_per_pkt_xfer_complete_irq = false,
874 .has_single_clk_source = false,
875 .clk_divisor_hs_mode = 3,
876 .clk_divisor_std_fast_mode = 0,
877 .clk_divisor_fast_plus_mode = 0,
878 .has_config_load_reg = false,
879 .has_multi_master_mode = false,
880 .has_slcg_override_reg = false,
881 .has_mst_fifo = false,
882 .quirks = &tegra_i2c_quirks,
883 };
884
885 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
886 .has_continue_xfer_support = true,
887 .has_per_pkt_xfer_complete_irq = true,
888 .has_single_clk_source = true,
889 .clk_divisor_hs_mode = 1,
890 .clk_divisor_std_fast_mode = 0x19,
891 .clk_divisor_fast_plus_mode = 0x10,
892 .has_config_load_reg = false,
893 .has_multi_master_mode = false,
894 .has_slcg_override_reg = false,
895 .has_mst_fifo = false,
896 .quirks = &tegra_i2c_quirks,
897 };
898
899 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
900 .has_continue_xfer_support = true,
901 .has_per_pkt_xfer_complete_irq = true,
902 .has_single_clk_source = true,
903 .clk_divisor_hs_mode = 1,
904 .clk_divisor_std_fast_mode = 0x19,
905 .clk_divisor_fast_plus_mode = 0x10,
906 .has_config_load_reg = true,
907 .has_multi_master_mode = false,
908 .has_slcg_override_reg = true,
909 .has_mst_fifo = false,
910 .quirks = &tegra_i2c_quirks,
911 };
912
913 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
914 .has_continue_xfer_support = true,
915 .has_per_pkt_xfer_complete_irq = true,
916 .has_single_clk_source = true,
917 .clk_divisor_hs_mode = 1,
918 .clk_divisor_std_fast_mode = 0x19,
919 .clk_divisor_fast_plus_mode = 0x10,
920 .has_config_load_reg = true,
921 .has_multi_master_mode = true,
922 .has_slcg_override_reg = true,
923 .has_mst_fifo = false,
924 .quirks = &tegra_i2c_quirks,
925 };
926
927 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
928 .has_continue_xfer_support = true,
929 .has_per_pkt_xfer_complete_irq = true,
930 .has_single_clk_source = true,
931 .clk_divisor_hs_mode = 1,
932 .clk_divisor_std_fast_mode = 0x19,
933 .clk_divisor_fast_plus_mode = 0x10,
934 .has_config_load_reg = true,
935 .has_multi_master_mode = true,
936 .has_slcg_override_reg = true,
937 .has_mst_fifo = true,
938 .quirks = &tegra194_i2c_quirks,
939 };
940
941 /* Match table for of_platform binding */
942 static const struct of_device_id tegra_i2c_of_match[] = {
943 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
944 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
945 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
946 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
947 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
948 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
949 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
950 {},
951 };
952 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
953
954 static int tegra_i2c_probe(struct platform_device *pdev)
955 {
956 struct tegra_i2c_dev *i2c_dev;
957 struct resource *res;
958 struct clk *div_clk;
959 struct clk *fast_clk;
960 void __iomem *base;
961 int irq;
962 int ret = 0;
963 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
964
965 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
966 base = devm_ioremap_resource(&pdev->dev, res);
967 if (IS_ERR(base))
968 return PTR_ERR(base);
969
970 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
971 if (!res) {
972 dev_err(&pdev->dev, "no irq resource\n");
973 return -EINVAL;
974 }
975 irq = res->start;
976
977 div_clk = devm_clk_get(&pdev->dev, "div-clk");
978 if (IS_ERR(div_clk)) {
979 dev_err(&pdev->dev, "missing controller clock\n");
980 return PTR_ERR(div_clk);
981 }
982
983 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
984 if (!i2c_dev)
985 return -ENOMEM;
986
987 i2c_dev->base = base;
988 i2c_dev->div_clk = div_clk;
989 i2c_dev->adapter.algo = &tegra_i2c_algo;
990 i2c_dev->irq = irq;
991 i2c_dev->cont_id = pdev->id;
992 i2c_dev->dev = &pdev->dev;
993
994 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
995 if (IS_ERR(i2c_dev->rst)) {
996 dev_err(&pdev->dev, "missing controller reset\n");
997 return PTR_ERR(i2c_dev->rst);
998 }
999
1000 tegra_i2c_parse_dt(i2c_dev);
1001
1002 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1003 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1004 "nvidia,tegra20-i2c-dvc");
1005 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1006 init_completion(&i2c_dev->msg_complete);
1007 spin_lock_init(&i2c_dev->xfer_lock);
1008
1009 if (!i2c_dev->hw->has_single_clk_source) {
1010 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1011 if (IS_ERR(fast_clk)) {
1012 dev_err(&pdev->dev, "missing fast clock\n");
1013 return PTR_ERR(fast_clk);
1014 }
1015 i2c_dev->fast_clk = fast_clk;
1016 }
1017
1018 platform_set_drvdata(pdev, i2c_dev);
1019
1020 if (!i2c_dev->hw->has_single_clk_source) {
1021 ret = clk_prepare(i2c_dev->fast_clk);
1022 if (ret < 0) {
1023 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1024 return ret;
1025 }
1026 }
1027
1028 i2c_dev->clk_divisor_non_hs_mode =
1029 i2c_dev->hw->clk_divisor_std_fast_mode;
1030 if (i2c_dev->hw->clk_divisor_fast_plus_mode &&
1031 (i2c_dev->bus_clk_rate == 1000000))
1032 i2c_dev->clk_divisor_non_hs_mode =
1033 i2c_dev->hw->clk_divisor_fast_plus_mode;
1034
1035 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
1036 ret = clk_set_rate(i2c_dev->div_clk,
1037 i2c_dev->bus_clk_rate * clk_multiplier);
1038 if (ret) {
1039 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret);
1040 goto unprepare_fast_clk;
1041 }
1042
1043 ret = clk_prepare(i2c_dev->div_clk);
1044 if (ret < 0) {
1045 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1046 goto unprepare_fast_clk;
1047 }
1048
1049 pm_runtime_enable(&pdev->dev);
1050 if (!pm_runtime_enabled(&pdev->dev)) {
1051 ret = tegra_i2c_runtime_resume(&pdev->dev);
1052 if (ret < 0) {
1053 dev_err(&pdev->dev, "runtime resume failed\n");
1054 goto unprepare_div_clk;
1055 }
1056 }
1057
1058 if (i2c_dev->is_multimaster_mode) {
1059 ret = clk_enable(i2c_dev->div_clk);
1060 if (ret < 0) {
1061 dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1062 ret);
1063 goto disable_rpm;
1064 }
1065 }
1066
1067 ret = tegra_i2c_init(i2c_dev);
1068 if (ret) {
1069 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1070 goto disable_div_clk;
1071 }
1072
1073 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
1074 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
1075 if (ret) {
1076 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1077 goto disable_div_clk;
1078 }
1079
1080 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1081 i2c_dev->adapter.owner = THIS_MODULE;
1082 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1083 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1084 sizeof(i2c_dev->adapter.name));
1085 i2c_dev->adapter.dev.parent = &pdev->dev;
1086 i2c_dev->adapter.nr = pdev->id;
1087 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1088
1089 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1090 if (ret)
1091 goto disable_div_clk;
1092
1093 return 0;
1094
1095 disable_div_clk:
1096 if (i2c_dev->is_multimaster_mode)
1097 clk_disable(i2c_dev->div_clk);
1098
1099 disable_rpm:
1100 pm_runtime_disable(&pdev->dev);
1101 if (!pm_runtime_status_suspended(&pdev->dev))
1102 tegra_i2c_runtime_suspend(&pdev->dev);
1103
1104 unprepare_div_clk:
1105 clk_unprepare(i2c_dev->div_clk);
1106
1107 unprepare_fast_clk:
1108 if (!i2c_dev->hw->has_single_clk_source)
1109 clk_unprepare(i2c_dev->fast_clk);
1110
1111 return ret;
1112 }
1113
1114 static int tegra_i2c_remove(struct platform_device *pdev)
1115 {
1116 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1117
1118 i2c_del_adapter(&i2c_dev->adapter);
1119
1120 if (i2c_dev->is_multimaster_mode)
1121 clk_disable(i2c_dev->div_clk);
1122
1123 pm_runtime_disable(&pdev->dev);
1124 if (!pm_runtime_status_suspended(&pdev->dev))
1125 tegra_i2c_runtime_suspend(&pdev->dev);
1126
1127 clk_unprepare(i2c_dev->div_clk);
1128 if (!i2c_dev->hw->has_single_clk_source)
1129 clk_unprepare(i2c_dev->fast_clk);
1130
1131 return 0;
1132 }
1133
1134 #ifdef CONFIG_PM_SLEEP
1135 static const struct dev_pm_ops tegra_i2c_pm = {
1136 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1137 NULL)
1138 };
1139 #define TEGRA_I2C_PM (&tegra_i2c_pm)
1140 #else
1141 #define TEGRA_I2C_PM NULL
1142 #endif
1143
1144 static struct platform_driver tegra_i2c_driver = {
1145 .probe = tegra_i2c_probe,
1146 .remove = tegra_i2c_remove,
1147 .driver = {
1148 .name = "tegra-i2c",
1149 .of_match_table = tegra_i2c_of_match,
1150 .pm = TEGRA_I2C_PM,
1151 },
1152 };
1153
1154 static int __init tegra_i2c_init_driver(void)
1155 {
1156 return platform_driver_register(&tegra_i2c_driver);
1157 }
1158
1159 static void __exit tegra_i2c_exit_driver(void)
1160 {
1161 platform_driver_unregister(&tegra_i2c_driver);
1162 }
1163
1164 subsys_initcall(tegra_i2c_init_driver);
1165 module_exit(tegra_i2c_exit_driver);
1166
1167 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1168 MODULE_AUTHOR("Colin Cross");
1169 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support