?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-uniphier-f.c
blobdd0687e36a47ba4d37313ac749614eca305b429a
1 /*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/i2c.h>
17 #include <linux/iopoll.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22
23 #define UNIPHIER_FI2C_CR 0x00 /* control register */
24 #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
25 #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
26 #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
27 #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
28 #define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
29 #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
30 #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
31 #define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
32 #define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
33 #define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
34 #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
35 #define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
36 #define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */
37 #define UNIPHIER_FI2C_INT 0x20 /* interrupt status */
38 #define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */
39 #define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */
40 #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */
41 #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */
42 #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */
43 #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */
44 #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */
45 #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */
46 #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */
47 #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */
48 #define UNIPHIER_FI2C_SR 0x2c /* status register */
49 #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */
50 #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */
51 #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */
52 #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */
53 #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */
54 #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */
55 #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */
56 #define UNIPHIER_FI2C_RST 0x34 /* reset control */
57 #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */
58 #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */
59 #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */
60 #define UNIPHIER_FI2C_BM 0x38 /* bus monitor */
61 #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */
62 #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */
63 #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */
64 #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */
65 #define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */
66 #define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */
67 #define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */
68 #define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */
69 #define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */
70 #define UNIPHIER_FI2C_BRST 0x50 /* bus reset */
71 #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */
72 #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */
73
74 #define UNIPHIER_FI2C_INT_FAULTS \
75 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
76 #define UNIPHIER_FI2C_INT_STOP \
77 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
78
79 #define UNIPHIER_FI2C_RD BIT(0)
80 #define UNIPHIER_FI2C_STOP BIT(1)
81 #define UNIPHIER_FI2C_MANUAL_NACK BIT(2)
82 #define UNIPHIER_FI2C_BYTE_WISE BIT(3)
83 #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4)
84
85 #define UNIPHIER_FI2C_DEFAULT_SPEED 100000
86 #define UNIPHIER_FI2C_MAX_SPEED 400000
87 #define UNIPHIER_FI2C_FIFO_SIZE 8
88
89 struct uniphier_fi2c_priv {
90 struct completion comp;
91 struct i2c_adapter adap;
92 void __iomem *membase;
93 struct clk *clk;
94 unsigned int len;
95 u8 *buf;
96 u32 enabled_irqs;
97 int error;
98 unsigned int flags;
99 unsigned int busy_cnt;
100 unsigned int clk_cycle;
101 spinlock_t lock; /* IRQ synchronization */
102 };
103
104 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
105 bool first)
106 {
107 int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
108
109 /*
110 * TX-FIFO stores slave address in it for the first access.
111 * Decrement the counter.
112 */
113 if (first)
114 fifo_space--;
115
116 while (priv->len) {
117 if (fifo_space-- <= 0)
118 break;
119
120 dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf);
121 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
122 priv->len--;
123 }
124 }
125
126 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
127 {
128 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
129 1 : UNIPHIER_FI2C_FIFO_SIZE;
130
131 while (priv->len) {
132 if (fifo_left-- <= 0)
133 break;
134
135 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
136 dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]);
137 priv->len--;
138 }
139 }
140
141 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
142 {
143 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
144 }
145
146 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv,
147 u32 mask)
148 {
149 writel(mask, priv->membase + UNIPHIER_FI2C_IC);
150 }
151
152 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
153 {
154 dev_dbg(&priv->adap.dev, "stop condition\n");
155
156 priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
157 uniphier_fi2c_set_irqs(priv);
158 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
159 priv->membase + UNIPHIER_FI2C_CR);
160 }
161
162 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
163 {
164 struct uniphier_fi2c_priv *priv = dev_id;
165 u32 irq_status;
166
167 spin_lock(&priv->lock);
168
169 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
170 irq_status &= priv->enabled_irqs;
171
172 dev_dbg(&priv->adap.dev,
173 "interrupt: enabled_irqs=%04x, irq_status=%04x\n",
174 priv->enabled_irqs, irq_status);
175
176 if (irq_status & UNIPHIER_FI2C_INT_STOP)
177 goto complete;
178
179 if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
180 dev_dbg(&priv->adap.dev, "arbitration lost\n");
181 priv->error = -EAGAIN;
182 goto complete;
183 }
184
185 if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
186 dev_dbg(&priv->adap.dev, "could not get ACK\n");
187 priv->error = -ENXIO;
188 if (priv->flags & UNIPHIER_FI2C_RD) {
189 /*
190 * work around a hardware bug:
191 * The receive-completed interrupt is never set even if
192 * STOP condition is detected after the address phase
193 * of read transaction fails to get ACK.
194 * To avoid time-out error, we issue STOP here,
195 * but do not wait for its completion.
196 * It should be checked after exiting this handler.
197 */
198 uniphier_fi2c_stop(priv);
199 priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
200 goto complete;
201 }
202 goto stop;
203 }
204
205 if (irq_status & UNIPHIER_FI2C_INT_TE) {
206 if (!priv->len)
207 goto data_done;
208
209 uniphier_fi2c_fill_txfifo(priv, false);
210 goto handled;
211 }
212
213 if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
214 uniphier_fi2c_drain_rxfifo(priv);
215 /*
216 * If the number of bytes to read is multiple of the FIFO size
217 * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little
218 * earlier than INT_RB. We wait for INT_RB to confirm the
219 * completion of the current message.
220 */
221 if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB))
222 goto data_done;
223
224 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
225 if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
226 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
227 dev_dbg(&priv->adap.dev,
228 "enable read byte count IRQ\n");
229 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
230 uniphier_fi2c_set_irqs(priv);
231 priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
232 }
233 if (priv->len <= 1) {
234 dev_dbg(&priv->adap.dev, "set NACK\n");
235 writel(UNIPHIER_FI2C_CR_MST |
236 UNIPHIER_FI2C_CR_NACK,
237 priv->membase + UNIPHIER_FI2C_CR);
238 }
239 }
240
241 goto handled;
242 }
243
244 spin_unlock(&priv->lock);
245
246 return IRQ_NONE;
247
248 data_done:
249 if (priv->flags & UNIPHIER_FI2C_STOP) {
250 stop:
251 uniphier_fi2c_stop(priv);
252 } else {
253 complete:
254 priv->enabled_irqs = 0;
255 uniphier_fi2c_set_irqs(priv);
256 complete(&priv->comp);
257 }
258
259 handled:
260 /*
261 * This controller makes a pause while any bit of the IRQ status is
262 * asserted. Clear the asserted bit to kick the controller just before
263 * exiting the handler.
264 */
265 uniphier_fi2c_clear_irqs(priv, irq_status);
266
267 spin_unlock(&priv->lock);
268
269 return IRQ_HANDLED;
270 }
271
272 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr)
273 {
274 priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
275 uniphier_fi2c_set_irqs(priv);
276
277 /* do not use TX byte counter */
278 writel(0, priv->membase + UNIPHIER_FI2C_TBC);
279 /* set slave address */
280 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
281 priv->membase + UNIPHIER_FI2C_DTTX);
282 /* first chunk of data */
283 uniphier_fi2c_fill_txfifo(priv, true);
284 }
285
286 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
287 {
288 priv->flags |= UNIPHIER_FI2C_RD;
289
290 if (likely(priv->len < 256)) {
291 /*
292 * If possible, use RX byte counter.
293 * It can automatically handle NACK for the last byte.
294 */
295 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
296 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
297 UNIPHIER_FI2C_INT_RB;
298 } else {
299 /*
300 * The byte counter can not count over 256. In this case,
301 * do not use it at all. Drain data when FIFO gets full,
302 * but treat the last portion as a special case.
303 */
304 writel(0, priv->membase + UNIPHIER_FI2C_RBC);
305 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
306 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
307 }
308
309 uniphier_fi2c_set_irqs(priv);
310
311 /* set slave address with RD bit */
312 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
313 priv->membase + UNIPHIER_FI2C_DTTX);
314 }
315
316 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
317 {
318 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
319 }
320
321 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
322 {
323 writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
324 priv->membase + UNIPHIER_FI2C_BRST);
325 }
326
327 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
328 {
329 uniphier_fi2c_reset(priv);
330 i2c_recover_bus(&priv->adap);
331 }
332
333 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
334 struct i2c_msg *msg, bool repeat,
335 bool stop)
336 {
337 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
338 bool is_read = msg->flags & I2C_M_RD;
339 unsigned long time_left, flags;
340
341 dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, repeat=%d, stop=%d\n",
342 is_read ? "receive" : "transmit", msg->addr, msg->len,
343 repeat, stop);
344
345 priv->len = msg->len;
346 priv->buf = msg->buf;
347 priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
348 priv->error = 0;
349 priv->flags = 0;
350
351 if (stop)
352 priv->flags |= UNIPHIER_FI2C_STOP;
353
354 reinit_completion(&priv->comp);
355 uniphier_fi2c_clear_irqs(priv, U32_MAX);
356 writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
357 priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */
358
359 spin_lock_irqsave(&priv->lock, flags);
360
361 if (is_read)
362 uniphier_fi2c_rx_init(priv, msg->addr);
363 else
364 uniphier_fi2c_tx_init(priv, msg->addr);
365
366 dev_dbg(&adap->dev, "start condition\n");
367 /*
368 * For a repeated START condition, writing a slave address to the FIFO
369 * kicks the controller. So, the UNIPHIER_FI2C_CR register should be
370 * written only for a non-repeated START condition.
371 */
372 if (!repeat)
373 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
374 priv->membase + UNIPHIER_FI2C_CR);
375
376 spin_unlock_irqrestore(&priv->lock, flags);
377
378 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
379
380 spin_lock_irqsave(&priv->lock, flags);
381 priv->enabled_irqs = 0;
382 uniphier_fi2c_set_irqs(priv);
383 spin_unlock_irqrestore(&priv->lock, flags);
384
385 if (!time_left) {
386 dev_err(&adap->dev, "transaction timeout.\n");
387 uniphier_fi2c_recover(priv);
388 return -ETIMEDOUT;
389 }
390 dev_dbg(&adap->dev, "complete\n");
391
392 if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
393 u32 status;
394 int ret;
395
396 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,
397 status,
398 (status & UNIPHIER_FI2C_SR_STS) &&
399 !(status & UNIPHIER_FI2C_SR_BB),
400 1, 20);
401 if (ret) {
402 dev_err(&adap->dev,
403 "stop condition was not completed.\n");
404 uniphier_fi2c_recover(priv);
405 return ret;
406 }
407 }
408
409 return priv->error;
410 }
411
412 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
413 {
414 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
415
416 if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
417 if (priv->busy_cnt++ > 3) {
418 /*
419 * If bus busy continues too long, it is probably
420 * in a wrong state. Try bus recovery.
421 */
422 uniphier_fi2c_recover(priv);
423 priv->busy_cnt = 0;
424 }
425
426 return -EAGAIN;
427 }
428
429 priv->busy_cnt = 0;
430 return 0;
431 }
432
433 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
434 struct i2c_msg *msgs, int num)
435 {
436 struct i2c_msg *msg, *emsg = msgs + num;
437 bool repeat = false;
438 int ret;
439
440 ret = uniphier_fi2c_check_bus_busy(adap);
441 if (ret)
442 return ret;
443
444 for (msg = msgs; msg < emsg; msg++) {
445 /* Emit STOP if it is the last message or I2C_M_STOP is set. */
446 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
447
448 ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
449 if (ret)
450 return ret;
451
452 repeat = !stop;
453 }
454
455 return num;
456 }
457
458 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
459 {
460 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
461 }
462
463 static const struct i2c_algorithm uniphier_fi2c_algo = {
464 .master_xfer = uniphier_fi2c_master_xfer,
465 .functionality = uniphier_fi2c_functionality,
466 };
467
468 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
469 {
470 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
471
472 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
473 UNIPHIER_FI2C_BM_SCLS);
474 }
475
476 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
477 {
478 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
479
480 writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
481 priv->membase + UNIPHIER_FI2C_BRST);
482 }
483
484 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
485 {
486 struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
487
488 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
489 UNIPHIER_FI2C_BM_SDAS);
490 }
491
492 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
493 {
494 uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
495 }
496
497 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
498 .recover_bus = i2c_generic_scl_recovery,
499 .get_scl = uniphier_fi2c_get_scl,
500 .set_scl = uniphier_fi2c_set_scl,
501 .get_sda = uniphier_fi2c_get_sda,
502 .unprepare_recovery = uniphier_fi2c_unprepare_recovery,
503 };
504
505 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)
506 {
507 unsigned int cyc = priv->clk_cycle;
508 u32 tmp;
509
510 tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
511 tmp |= UNIPHIER_FI2C_CR_MST;
512 writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
513
514 uniphier_fi2c_reset(priv);
515
516 /*
517 * Standard-mode: tLOW + tHIGH = 10 us
518 * Fast-mode: tLOW + tHIGH = 2.5 us
519 */
520 writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
521 /*
522 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us
523 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us
524 * "tLow/tHIGH = 5/4" meets both.
525 */
526 writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);
527 /*
528 * Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us
529 * Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us
530 */
531 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
532 /*
533 * Standard-mode: tSU;DAT = 250 ns
534 * Fast-mode: tSU;DAT = 100 ns
535 */
536 writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
537
538 uniphier_fi2c_prepare_operation(priv);
539 }
540
541 static int uniphier_fi2c_probe(struct platform_device *pdev)
542 {
543 struct device *dev = &pdev->dev;
544 struct uniphier_fi2c_priv *priv;
545 struct resource *regs;
546 u32 bus_speed;
547 unsigned long clk_rate;
548 int irq, ret;
549
550 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
551 if (!priv)
552 return -ENOMEM;
553
554 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
555 priv->membase = devm_ioremap_resource(dev, regs);
556 if (IS_ERR(priv->membase))
557 return PTR_ERR(priv->membase);
558
559 irq = platform_get_irq(pdev, 0);
560 if (irq < 0) {
561 dev_err(dev, "failed to get IRQ number\n");
562 return irq;
563 }
564
565 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
566 bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED;
567
568 if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) {
569 dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
570 return -EINVAL;
571 }
572
573 priv->clk = devm_clk_get(dev, NULL);
574 if (IS_ERR(priv->clk)) {
575 dev_err(dev, "failed to get clock\n");
576 return PTR_ERR(priv->clk);
577 }
578
579 ret = clk_prepare_enable(priv->clk);
580 if (ret)
581 return ret;
582
583 clk_rate = clk_get_rate(priv->clk);
584 if (!clk_rate) {
585 dev_err(dev, "input clock rate should not be zero\n");
586 ret = -EINVAL;
587 goto disable_clk;
588 }
589
590 priv->clk_cycle = clk_rate / bus_speed;
591 init_completion(&priv->comp);
592 spin_lock_init(&priv->lock);
593 priv->adap.owner = THIS_MODULE;
594 priv->adap.algo = &uniphier_fi2c_algo;
595 priv->adap.dev.parent = dev;
596 priv->adap.dev.of_node = dev->of_node;
597 strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
598 priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
599 i2c_set_adapdata(&priv->adap, priv);
600 platform_set_drvdata(pdev, priv);
601
602 uniphier_fi2c_hw_init(priv);
603
604 ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
605 pdev->name, priv);
606 if (ret) {
607 dev_err(dev, "failed to request irq %d\n", irq);
608 goto disable_clk;
609 }
610
611 ret = i2c_add_adapter(&priv->adap);
612 disable_clk:
613 if (ret)
614 clk_disable_unprepare(priv->clk);
615
616 return ret;
617 }
618
619 static int uniphier_fi2c_remove(struct platform_device *pdev)
620 {
621 struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
622
623 i2c_del_adapter(&priv->adap);
624 clk_disable_unprepare(priv->clk);
625
626 return 0;
627 }
628
629 static int __maybe_unused uniphier_fi2c_suspend(struct device *dev)
630 {
631 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
632
633 clk_disable_unprepare(priv->clk);
634
635 return 0;
636 }
637
638 static int __maybe_unused uniphier_fi2c_resume(struct device *dev)
639 {
640 struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
641 int ret;
642
643 ret = clk_prepare_enable(priv->clk);
644 if (ret)
645 return ret;
646
647 uniphier_fi2c_hw_init(priv);
648
649 return 0;
650 }
651
652 static const struct dev_pm_ops uniphier_fi2c_pm_ops = {
653 SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)
654 };
655
656 static const struct of_device_id uniphier_fi2c_match[] = {
657 { .compatible = "socionext,uniphier-fi2c" },
658 { /* sentinel */ }
659 };
660 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
661
662 static struct platform_driver uniphier_fi2c_drv = {
663 .probe = uniphier_fi2c_probe,
664 .remove = uniphier_fi2c_remove,
665 .driver = {
666 .name = "uniphier-fi2c",
667 .of_match_table = uniphier_fi2c_match,
668 .pm = &uniphier_fi2c_pm_ops,
669 },
670 };
671 module_platform_driver(uniphier_fi2c_drv);
672
673 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
674 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
675 MODULE_LICENSE("GPL");
Linux with added FPC-III support