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Linux 4.19.133
[linux/fpc-iii.git] / drivers / iio / adc / at91-sama5d2_adc.c
blobc485ff6f408bf11db0ba023ec120246d58f04323
1 /*
2 * Atmel ADC driver for SAMA5D2 devices and compatible.
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/bitops.h>
18 #include <linux/clk.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dmaengine.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/sched.h>
27 #include <linux/wait.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/buffer.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/trigger_consumer.h>
33 #include <linux/iio/triggered_buffer.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/regulator/consumer.h>
36
37 /* Control Register */
38 #define AT91_SAMA5D2_CR 0x00
39 /* Software Reset */
40 #define AT91_SAMA5D2_CR_SWRST BIT(0)
41 /* Start Conversion */
42 #define AT91_SAMA5D2_CR_START BIT(1)
43 /* Touchscreen Calibration */
44 #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
45 /* Comparison Restart */
46 #define AT91_SAMA5D2_CR_CMPRST BIT(4)
47
48 /* Mode Register */
49 #define AT91_SAMA5D2_MR 0x04
50 /* Trigger Selection */
51 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
52 /* ADTRG */
53 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
54 /* TIOA0 */
55 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
56 /* TIOA1 */
57 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
58 /* TIOA2 */
59 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
60 /* PWM event line 0 */
61 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
62 /* PWM event line 1 */
63 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
64 /* TIOA3 */
65 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
66 /* RTCOUT0 */
67 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
68 /* Sleep Mode */
69 #define AT91_SAMA5D2_MR_SLEEP BIT(5)
70 /* Fast Wake Up */
71 #define AT91_SAMA5D2_MR_FWUP BIT(6)
72 /* Prescaler Rate Selection */
73 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
74 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
75 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
76 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
77 /* Startup Time */
78 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
79 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
80 /* Analog Change */
81 #define AT91_SAMA5D2_MR_ANACH BIT(23)
82 /* Tracking Time */
83 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
84 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
85 /* Transfer Time */
86 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
87 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
88 /* Use Sequence Enable */
89 #define AT91_SAMA5D2_MR_USEQ BIT(31)
90
91 /* Channel Sequence Register 1 */
92 #define AT91_SAMA5D2_SEQR1 0x08
93 /* Channel Sequence Register 2 */
94 #define AT91_SAMA5D2_SEQR2 0x0c
95 /* Channel Enable Register */
96 #define AT91_SAMA5D2_CHER 0x10
97 /* Channel Disable Register */
98 #define AT91_SAMA5D2_CHDR 0x14
99 /* Channel Status Register */
100 #define AT91_SAMA5D2_CHSR 0x18
101 /* Last Converted Data Register */
102 #define AT91_SAMA5D2_LCDR 0x20
103 /* Interrupt Enable Register */
104 #define AT91_SAMA5D2_IER 0x24
105 /* Interrupt Enable Register - TS X measurement ready */
106 #define AT91_SAMA5D2_IER_XRDY BIT(20)
107 /* Interrupt Enable Register - TS Y measurement ready */
108 #define AT91_SAMA5D2_IER_YRDY BIT(21)
109 /* Interrupt Enable Register - TS pressure measurement ready */
110 #define AT91_SAMA5D2_IER_PRDY BIT(22)
111 /* Interrupt Enable Register - general overrun error */
112 #define AT91_SAMA5D2_IER_GOVRE BIT(25)
113 /* Interrupt Enable Register - Pen detect */
114 #define AT91_SAMA5D2_IER_PEN BIT(29)
115 /* Interrupt Enable Register - No pen detect */
116 #define AT91_SAMA5D2_IER_NOPEN BIT(30)
117 /* Interrupt Disable Register */
118 #define AT91_SAMA5D2_IDR 0x28
119 /* Interrupt Mask Register */
120 #define AT91_SAMA5D2_IMR 0x2c
121 /* Interrupt Status Register */
122 #define AT91_SAMA5D2_ISR 0x30
123 /* Interrupt Status Register - Pen touching sense status */
124 #define AT91_SAMA5D2_ISR_PENS BIT(31)
125 /* Last Channel Trigger Mode Register */
126 #define AT91_SAMA5D2_LCTMR 0x34
127 /* Last Channel Compare Window Register */
128 #define AT91_SAMA5D2_LCCWR 0x38
129 /* Overrun Status Register */
130 #define AT91_SAMA5D2_OVER 0x3c
131 /* Extended Mode Register */
132 #define AT91_SAMA5D2_EMR 0x40
133 /* Extended Mode Register - Oversampling rate */
134 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16)
135 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16)
136 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
137 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
138 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
139
140 /* Extended Mode Register - Averaging on single trigger event */
141 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
142 /* Compare Window Register */
143 #define AT91_SAMA5D2_CWR 0x44
144 /* Channel Gain Register */
145 #define AT91_SAMA5D2_CGR 0x48
146
147 /* Channel Offset Register */
148 #define AT91_SAMA5D2_COR 0x4c
149 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16
150
151 /* Channel Data Register 0 */
152 #define AT91_SAMA5D2_CDR0 0x50
153 /* Analog Control Register */
154 #define AT91_SAMA5D2_ACR 0x94
155 /* Analog Control Register - Pen detect sensitivity mask */
156 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
157
158 /* Touchscreen Mode Register */
159 #define AT91_SAMA5D2_TSMR 0xb0
160 /* Touchscreen Mode Register - No touch mode */
161 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
162 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
163 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
164 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
165 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
166 /* Touchscreen Mode Register - 5 wire screen */
167 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
168 /* Touchscreen Mode Register - Average samples mask */
169 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
170 /* Touchscreen Mode Register - Average samples */
171 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
172 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
173 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
174 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
175 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
176 /* Touchscreen Mode Register - Pen Debounce Time mask */
177 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
178 /* Touchscreen Mode Register - Pen Debounce Time */
179 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
180 /* Touchscreen Mode Register - No DMA for touch measurements */
181 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
182 /* Touchscreen Mode Register - Disable pen detection */
183 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
184 /* Touchscreen Mode Register - Enable pen detection */
185 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
186
187 /* Touchscreen X Position Register */
188 #define AT91_SAMA5D2_XPOSR 0xb4
189 /* Touchscreen Y Position Register */
190 #define AT91_SAMA5D2_YPOSR 0xb8
191 /* Touchscreen Pressure Register */
192 #define AT91_SAMA5D2_PRESSR 0xbc
193 /* Trigger Register */
194 #define AT91_SAMA5D2_TRGR 0xc0
195 /* Mask for TRGMOD field of TRGR register */
196 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
197 /* No trigger, only software trigger can start conversions */
198 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
199 /* Trigger Mode external trigger rising edge */
200 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
201 /* Trigger Mode external trigger falling edge */
202 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
203 /* Trigger Mode external trigger any edge */
204 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
205 /* Trigger Mode internal periodic */
206 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
207 /* Trigger Mode - trigger period mask */
208 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
209 /* Trigger Mode - trigger period */
210 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
211
212 /* Correction Select Register */
213 #define AT91_SAMA5D2_COSR 0xd0
214 /* Correction Value Register */
215 #define AT91_SAMA5D2_CVR 0xd4
216 /* Channel Error Correction Register */
217 #define AT91_SAMA5D2_CECR 0xd8
218 /* Write Protection Mode Register */
219 #define AT91_SAMA5D2_WPMR 0xe4
220 /* Write Protection Status Register */
221 #define AT91_SAMA5D2_WPSR 0xe8
222 /* Version Register */
223 #define AT91_SAMA5D2_VERSION 0xfc
224
225 #define AT91_SAMA5D2_HW_TRIG_CNT 3
226 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
227 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
228
229 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
230 AT91_SAMA5D2_DIFF_CHAN_CNT + 1)
231
232 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
233 AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
234 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
235 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
236 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
237
238 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
239 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
240
241 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
242
243 #define AT91_SAMA5D2_MAX_POS_BITS 12
244
245 /*
246 * Maximum number of bytes to hold conversion from all channels
247 * without the timestamp.
248 */
249 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
250 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2)
251
252 /* This total must also include the timestamp */
253 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8)
254
255 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
256
257 #define AT91_HWFIFO_MAX_SIZE_STR "128"
258 #define AT91_HWFIFO_MAX_SIZE 128
259
260 /* Possible values for oversampling ratio */
261 #define AT91_OSR_1SAMPLES 1
262 #define AT91_OSR_4SAMPLES 4
263 #define AT91_OSR_16SAMPLES 16
264
265 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
266 { \
267 .type = IIO_VOLTAGE, \
268 .channel = num, \
269 .address = addr, \
270 .scan_index = num, \
271 .scan_type = { \
272 .sign = 'u', \
273 .realbits = 14, \
274 .storagebits = 16, \
275 }, \
276 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
277 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
278 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
279 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
280 .datasheet_name = "CH"#num, \
281 .indexed = 1, \
282 }
283
284 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
285 { \
286 .type = IIO_VOLTAGE, \
287 .differential = 1, \
288 .channel = num, \
289 .channel2 = num2, \
290 .address = addr, \
291 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
292 .scan_type = { \
293 .sign = 's', \
294 .realbits = 14, \
295 .storagebits = 16, \
296 }, \
297 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
298 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
299 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
300 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
301 .datasheet_name = "CH"#num"-CH"#num2, \
302 .indexed = 1, \
303 }
304
305 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
306 { \
307 .type = IIO_POSITIONRELATIVE, \
308 .modified = 1, \
309 .channel = num, \
310 .channel2 = mod, \
311 .scan_index = num, \
312 .scan_type = { \
313 .sign = 'u', \
314 .realbits = 12, \
315 .storagebits = 16, \
316 }, \
317 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
318 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
319 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
320 .datasheet_name = name, \
321 }
322 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
323 { \
324 .type = IIO_PRESSURE, \
325 .channel = num, \
326 .scan_index = num, \
327 .scan_type = { \
328 .sign = 'u', \
329 .realbits = 12, \
330 .storagebits = 16, \
331 }, \
332 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
333 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
334 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
335 .datasheet_name = name, \
336 }
337
338 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
339 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
340
341 struct at91_adc_soc_info {
342 unsigned startup_time;
343 unsigned min_sample_rate;
344 unsigned max_sample_rate;
345 };
346
347 struct at91_adc_trigger {
348 char *name;
349 unsigned int trgmod_value;
350 unsigned int edge_type;
351 bool hw_trig;
352 };
353
354 /**
355 * at91_adc_dma - at91-sama5d2 dma information struct
356 * @dma_chan: the dma channel acquired
357 * @rx_buf: dma coherent allocated area
358 * @rx_dma_buf: dma handler for the buffer
359 * @phys_addr: physical address of the ADC base register
360 * @buf_idx: index inside the dma buffer where reading was last done
361 * @rx_buf_sz: size of buffer used by DMA operation
362 * @watermark: number of conversions to copy before DMA triggers irq
363 * @dma_ts: hold the start timestamp of dma operation
364 */
365 struct at91_adc_dma {
366 struct dma_chan *dma_chan;
367 u8 *rx_buf;
368 dma_addr_t rx_dma_buf;
369 phys_addr_t phys_addr;
370 int buf_idx;
371 int rx_buf_sz;
372 int watermark;
373 s64 dma_ts;
374 };
375
376 /**
377 * at91_adc_touch - at91-sama5d2 touchscreen information struct
378 * @sample_period_val: the value for periodic trigger interval
379 * @touching: is the pen touching the screen or not
380 * @x_pos: temporary placeholder for pressure computation
381 * @channels_bitmask: bitmask with the touchscreen channels enabled
382 * @workq: workqueue for buffer data pushing
383 */
384 struct at91_adc_touch {
385 u16 sample_period_val;
386 bool touching;
387 u16 x_pos;
388 unsigned long channels_bitmask;
389 struct work_struct workq;
390 };
391
392 struct at91_adc_state {
393 void __iomem *base;
394 int irq;
395 struct clk *per_clk;
396 struct regulator *reg;
397 struct regulator *vref;
398 int vref_uv;
399 unsigned int current_sample_rate;
400 struct iio_trigger *trig;
401 const struct at91_adc_trigger *selected_trig;
402 const struct iio_chan_spec *chan;
403 bool conversion_done;
404 u32 conversion_value;
405 unsigned int oversampling_ratio;
406 struct at91_adc_soc_info soc_info;
407 wait_queue_head_t wq_data_available;
408 struct at91_adc_dma dma_st;
409 struct at91_adc_touch touch_st;
410 u16 buffer[AT91_BUFFER_MAX_HWORDS];
411 /*
412 * lock to prevent concurrent 'single conversion' requests through
413 * sysfs.
414 */
415 struct mutex lock;
416 };
417
418 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
419 {
420 .name = "external_rising",
421 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
422 .edge_type = IRQ_TYPE_EDGE_RISING,
423 .hw_trig = true,
424 },
425 {
426 .name = "external_falling",
427 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
428 .edge_type = IRQ_TYPE_EDGE_FALLING,
429 .hw_trig = true,
430 },
431 {
432 .name = "external_any",
433 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
434 .edge_type = IRQ_TYPE_EDGE_BOTH,
435 .hw_trig = true,
436 },
437 {
438 .name = "software",
439 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
440 .edge_type = IRQ_TYPE_NONE,
441 .hw_trig = false,
442 },
443 };
444
445 static const struct iio_chan_spec at91_adc_channels[] = {
446 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
447 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
448 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
449 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
450 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
451 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
452 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
453 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
454 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
455 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
456 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
457 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
458 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
459 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
460 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
461 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
462 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
463 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
464 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX),
465 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X),
466 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y),
467 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"),
468 };
469
470 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
471 {
472 int i;
473
474 for (i = 0; i < indio_dev->num_channels; i++) {
475 if (indio_dev->channels[i].scan_index == chan)
476 return i;
477 }
478 return -EINVAL;
479 }
480
481 static inline struct iio_chan_spec const *
482 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
483 {
484 int index = at91_adc_chan_xlate(indio_dev, chan);
485
486 if (index < 0)
487 return NULL;
488 return indio_dev->channels + index;
489 }
490
491 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
492 const struct of_phandle_args *iiospec)
493 {
494 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
495 }
496
497 static void at91_adc_config_emr(struct at91_adc_state *st)
498 {
499 /* configure the extended mode register */
500 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR);
501
502 /* select oversampling per single trigger event */
503 emr |= AT91_SAMA5D2_EMR_ASTE(1);
504
505 /* delete leftover content if it's the case */
506 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
507
508 /* select oversampling ratio from configuration */
509 switch (st->oversampling_ratio) {
510 case AT91_OSR_1SAMPLES:
511 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
512 AT91_SAMA5D2_EMR_OSR_MASK;
513 break;
514 case AT91_OSR_4SAMPLES:
515 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
516 AT91_SAMA5D2_EMR_OSR_MASK;
517 break;
518 case AT91_OSR_16SAMPLES:
519 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
520 AT91_SAMA5D2_EMR_OSR_MASK;
521 break;
522 }
523
524 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);
525 }
526
527 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
528 {
529 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
530 /*
531 * in this case we only have 12 bits of real data, but channel
532 * is registered as 14 bits, so shift left two bits
533 */
534 *val <<= 2;
535 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
536 /*
537 * in this case we have 13 bits of real data, but channel
538 * is registered as 14 bits, so left shift one bit
539 */
540 *val <<= 1;
541 }
542
543 return IIO_VAL_INT;
544 }
545
546 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
547 int len)
548 {
549 int i = 0, val;
550 u16 *buf_u16 = (u16 *) buf;
551
552 /*
553 * We are converting each two bytes (each sample).
554 * First convert the byte based array to u16, and convert each sample
555 * separately.
556 * Each value is two bytes in an array of chars, so to not shift
557 * more than we need, save the value separately.
558 * len is in bytes, so divide by two to get number of samples.
559 */
560 while (i < len / 2) {
561 val = buf_u16[i];
562 at91_adc_adjust_val_osr(st, &val);
563 buf_u16[i] = val;
564 i++;
565 }
566 }
567
568 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
569 {
570 u32 clk_khz = st->current_sample_rate / 1000;
571 int i = 0;
572 u16 pendbc;
573 u32 tsmr, acr;
574
575 if (!state) {
576 /* disabling touch IRQs and setting mode to no touch enabled */
577 at91_adc_writel(st, AT91_SAMA5D2_IDR,
578 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
579 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);
580 return 0;
581 }
582 /*
583 * debounce time is in microseconds, we need it in milliseconds to
584 * multiply with kilohertz, so, divide by 1000, but after the multiply.
585 * round up to make sure pendbc is at least 1
586 */
587 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
588 clk_khz / 1000, 1);
589
590 /* get the required exponent */
591 while (pendbc >> i++)
592 ;
593
594 pendbc = i;
595
596 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
597
598 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
599 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
600 AT91_SAMA5D2_TSMR_PENDBC_MASK;
601 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
602 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
603 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
604
605 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);
606
607 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR);
608 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
609 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
610 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);
611
612 /* Sample Period Time = (TRGPER + 1) / ADCClock */
613 st->touch_st.sample_period_val =
614 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
615 clk_khz / 1000) - 1, 1);
616 /* enable pen detect IRQ */
617 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
618
619 return 0;
620 }
621
622 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
623 {
624 u32 val;
625 u32 scale, result, pos;
626
627 /*
628 * to obtain the actual position we must divide by scale
629 * and multiply with max, where
630 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
631 */
632 /* first half of register is the x or y, second half is the scale */
633 val = at91_adc_readl(st, reg);
634 if (!val)
635 dev_dbg(&iio_priv_to_dev(st)->dev, "pos is 0\n");
636
637 pos = val & AT91_SAMA5D2_XYZ_MASK;
638 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
639 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
640 if (scale == 0) {
641 dev_err(&iio_priv_to_dev(st)->dev, "scale is 0\n");
642 return 0;
643 }
644 result /= scale;
645
646 return result;
647 }
648
649 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
650 {
651 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR);
652 return st->touch_st.x_pos;
653 }
654
655 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
656 {
657 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR);
658 }
659
660 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
661 {
662 u32 val;
663 u32 z1, z2;
664 u32 pres;
665 u32 rxp = 1;
666 u32 factor = 1000;
667
668 /* calculate the pressure */
669 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
670 z1 = val & AT91_SAMA5D2_XYZ_MASK;
671 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
672
673 if (z1 != 0)
674 pres = rxp * (st->touch_st.x_pos * factor / 1024) *
675 (z2 * factor / z1 - factor) /
676 factor;
677 else
678 pres = 0xFFFF; /* no pen contact */
679
680 /*
681 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
682 * We compute it this way, but let's return it in the expected way,
683 * growing from 0 to 0xFFFF.
684 */
685 return 0xFFFF - pres;
686 }
687
688 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
689 {
690 *val = 0;
691 if (!st->touch_st.touching)
692 return -ENODATA;
693 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX)
694 *val = at91_adc_touch_x_pos(st);
695 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX)
696 *val = at91_adc_touch_y_pos(st);
697 else
698 return -ENODATA;
699
700 return IIO_VAL_INT;
701 }
702
703 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
704 {
705 *val = 0;
706 if (!st->touch_st.touching)
707 return -ENODATA;
708 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX)
709 *val = at91_adc_touch_pressure(st);
710 else
711 return -ENODATA;
712
713 return IIO_VAL_INT;
714 }
715
716 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
717 {
718 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
719 struct at91_adc_state *st = iio_priv(indio);
720 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
721 u8 bit;
722
723 /* clear TRGMOD */
724 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
725
726 if (state)
727 status |= st->selected_trig->trgmod_value;
728
729 /* set/unset hw trigger */
730 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
731
732 for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
733 struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);
734 u32 cor;
735
736 if (!chan)
737 continue;
738 /* these channel types cannot be handled by this trigger */
739 if (chan->type == IIO_POSITIONRELATIVE ||
740 chan->type == IIO_PRESSURE)
741 continue;
742
743 if (state) {
744 cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
745
746 if (chan->differential)
747 cor |= (BIT(chan->channel) |
748 BIT(chan->channel2)) <<
749 AT91_SAMA5D2_COR_DIFF_OFFSET;
750 else
751 cor &= ~(BIT(chan->channel) <<
752 AT91_SAMA5D2_COR_DIFF_OFFSET);
753
754 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
755 }
756
757 if (state) {
758 at91_adc_writel(st, AT91_SAMA5D2_CHER,
759 BIT(chan->channel));
760 /* enable irq only if not using DMA */
761 if (!st->dma_st.dma_chan) {
762 at91_adc_writel(st, AT91_SAMA5D2_IER,
763 BIT(chan->channel));
764 }
765 } else {
766 /* disable irq only if not using DMA */
767 if (!st->dma_st.dma_chan) {
768 at91_adc_writel(st, AT91_SAMA5D2_IDR,
769 BIT(chan->channel));
770 }
771 at91_adc_writel(st, AT91_SAMA5D2_CHDR,
772 BIT(chan->channel));
773 }
774 }
775
776 return 0;
777 }
778
779 static int at91_adc_reenable_trigger(struct iio_trigger *trig)
780 {
781 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
782 struct at91_adc_state *st = iio_priv(indio);
783
784 /* if we are using DMA, we must not reenable irq after each trigger */
785 if (st->dma_st.dma_chan)
786 return 0;
787
788 enable_irq(st->irq);
789
790 /* Needed to ACK the DRDY interruption */
791 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
792 return 0;
793 }
794
795 static const struct iio_trigger_ops at91_adc_trigger_ops = {
796 .set_trigger_state = &at91_adc_configure_trigger,
797 .try_reenable = &at91_adc_reenable_trigger,
798 .validate_device = iio_trigger_validate_own_device,
799 };
800
801 static int at91_adc_dma_size_done(struct at91_adc_state *st)
802 {
803 struct dma_tx_state state;
804 enum dma_status status;
805 int i, size;
806
807 status = dmaengine_tx_status(st->dma_st.dma_chan,
808 st->dma_st.dma_chan->cookie,
809 &state);
810 if (status != DMA_IN_PROGRESS)
811 return 0;
812
813 /* Transferred length is size in bytes from end of buffer */
814 i = st->dma_st.rx_buf_sz - state.residue;
815
816 /* Return available bytes */
817 if (i >= st->dma_st.buf_idx)
818 size = i - st->dma_st.buf_idx;
819 else
820 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
821 return size;
822 }
823
824 static void at91_dma_buffer_done(void *data)
825 {
826 struct iio_dev *indio_dev = data;
827
828 iio_trigger_poll_chained(indio_dev->trig);
829 }
830
831 static int at91_adc_dma_start(struct iio_dev *indio_dev)
832 {
833 struct at91_adc_state *st = iio_priv(indio_dev);
834 struct dma_async_tx_descriptor *desc;
835 dma_cookie_t cookie;
836 int ret;
837 u8 bit;
838
839 if (!st->dma_st.dma_chan)
840 return 0;
841
842 /* we start a new DMA, so set buffer index to start */
843 st->dma_st.buf_idx = 0;
844
845 /*
846 * compute buffer size w.r.t. watermark and enabled channels.
847 * scan_bytes is aligned so we need an exact size for DMA
848 */
849 st->dma_st.rx_buf_sz = 0;
850
851 for_each_set_bit(bit, indio_dev->active_scan_mask,
852 indio_dev->num_channels) {
853 struct iio_chan_spec const *chan =
854 at91_adc_chan_get(indio_dev, bit);
855
856 if (!chan)
857 continue;
858
859 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
860 }
861 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
862
863 /* Prepare a DMA cyclic transaction */
864 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
865 st->dma_st.rx_dma_buf,
866 st->dma_st.rx_buf_sz,
867 st->dma_st.rx_buf_sz / 2,
868 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
869
870 if (!desc) {
871 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
872 return -EBUSY;
873 }
874
875 desc->callback = at91_dma_buffer_done;
876 desc->callback_param = indio_dev;
877
878 cookie = dmaengine_submit(desc);
879 ret = dma_submit_error(cookie);
880 if (ret) {
881 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
882 dmaengine_terminate_async(st->dma_st.dma_chan);
883 return ret;
884 }
885
886 /* enable general overrun error signaling */
887 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);
888 /* Issue pending DMA requests */
889 dma_async_issue_pending(st->dma_st.dma_chan);
890
891 /* consider current time as DMA start time for timestamps */
892 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
893
894 dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
895
896 return 0;
897 }
898
899 static int at91_adc_buffer_postenable(struct iio_dev *indio_dev)
900 {
901 int ret;
902 struct at91_adc_state *st = iio_priv(indio_dev);
903
904 /* check if we are enabling triggered buffer or the touchscreen */
905 if (bitmap_subset(indio_dev->active_scan_mask,
906 &st->touch_st.channels_bitmask,
907 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
908 /* touchscreen enabling */
909 return at91_adc_configure_touch(st, true);
910 }
911 /* if we are not in triggered mode, we cannot enable the buffer. */
912 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
913 return -EINVAL;
914
915 /* we continue with the triggered buffer */
916 ret = at91_adc_dma_start(indio_dev);
917 if (ret) {
918 dev_err(&indio_dev->dev, "buffer postenable failed\n");
919 return ret;
920 }
921
922 return iio_triggered_buffer_postenable(indio_dev);
923 }
924
925 static int at91_adc_buffer_predisable(struct iio_dev *indio_dev)
926 {
927 struct at91_adc_state *st = iio_priv(indio_dev);
928 int ret;
929 u8 bit;
930
931 /* check if we are disabling triggered buffer or the touchscreen */
932 if (bitmap_subset(indio_dev->active_scan_mask,
933 &st->touch_st.channels_bitmask,
934 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
935 /* touchscreen disable */
936 return at91_adc_configure_touch(st, false);
937 }
938 /* if we are not in triggered mode, nothing to do here */
939 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
940 return -EINVAL;
941
942 /* continue with the triggered buffer */
943 ret = iio_triggered_buffer_predisable(indio_dev);
944 if (ret < 0)
945 dev_err(&indio_dev->dev, "buffer predisable failed\n");
946
947 if (!st->dma_st.dma_chan)
948 return ret;
949
950 /* if we are using DMA we must clear registers and end DMA */
951 dmaengine_terminate_sync(st->dma_st.dma_chan);
952
953 /*
954 * For each enabled channel we must read the last converted value
955 * to clear EOC status and not get a possible interrupt later.
956 * This value is being read by DMA from LCDR anyway
957 */
958 for_each_set_bit(bit, indio_dev->active_scan_mask,
959 indio_dev->num_channels) {
960 struct iio_chan_spec const *chan =
961 at91_adc_chan_get(indio_dev, bit);
962
963 if (!chan)
964 continue;
965 /* these channel types are virtual, no need to do anything */
966 if (chan->type == IIO_POSITIONRELATIVE ||
967 chan->type == IIO_PRESSURE)
968 continue;
969 if (st->dma_st.dma_chan)
970 at91_adc_readl(st, chan->address);
971 }
972
973 /* read overflow register to clear possible overflow status */
974 at91_adc_readl(st, AT91_SAMA5D2_OVER);
975 return ret;
976 }
977
978 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
979 .postenable = &at91_adc_buffer_postenable,
980 .predisable = &at91_adc_buffer_predisable,
981 };
982
983 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
984 char *trigger_name)
985 {
986 struct iio_trigger *trig;
987 int ret;
988
989 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
990 indio->id, trigger_name);
991 if (!trig)
992 return NULL;
993
994 trig->dev.parent = indio->dev.parent;
995 iio_trigger_set_drvdata(trig, indio);
996 trig->ops = &at91_adc_trigger_ops;
997
998 ret = devm_iio_trigger_register(&indio->dev, trig);
999 if (ret)
1000 return ERR_PTR(ret);
1001
1002 return trig;
1003 }
1004
1005 static int at91_adc_trigger_init(struct iio_dev *indio)
1006 {
1007 struct at91_adc_state *st = iio_priv(indio);
1008
1009 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
1010 if (IS_ERR(st->trig)) {
1011 dev_err(&indio->dev,
1012 "could not allocate trigger\n");
1013 return PTR_ERR(st->trig);
1014 }
1015
1016 return 0;
1017 }
1018
1019 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
1020 struct iio_poll_func *pf)
1021 {
1022 struct at91_adc_state *st = iio_priv(indio_dev);
1023 int i = 0;
1024 int val;
1025 u8 bit;
1026
1027 for_each_set_bit(bit, indio_dev->active_scan_mask,
1028 indio_dev->num_channels) {
1029 struct iio_chan_spec const *chan =
1030 at91_adc_chan_get(indio_dev, bit);
1031
1032 if (!chan)
1033 continue;
1034 /*
1035 * Our external trigger only supports the voltage channels.
1036 * In case someone requested a different type of channel
1037 * just put zeroes to buffer.
1038 * This should not happen because we check the scan mode
1039 * and scan mask when we enable the buffer, and we don't allow
1040 * the buffer to start with a mixed mask (voltage and something
1041 * else).
1042 * Thus, emit a warning.
1043 */
1044 if (chan->type == IIO_VOLTAGE) {
1045 val = at91_adc_readl(st, chan->address);
1046 at91_adc_adjust_val_osr(st, &val);
1047 st->buffer[i] = val;
1048 } else {
1049 st->buffer[i] = 0;
1050 WARN(true, "This trigger cannot handle this type of channel");
1051 }
1052 i++;
1053 }
1054 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1055 pf->timestamp);
1056 }
1057
1058 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
1059 {
1060 struct at91_adc_state *st = iio_priv(indio_dev);
1061 int transferred_len = at91_adc_dma_size_done(st);
1062 s64 ns = iio_get_time_ns(indio_dev);
1063 s64 interval;
1064 int sample_index = 0, sample_count, sample_size;
1065
1066 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1067 /* if we reached this point, we cannot sample faster */
1068 if (status & AT91_SAMA5D2_IER_GOVRE)
1069 pr_info_ratelimited("%s: conversion overrun detected\n",
1070 indio_dev->name);
1071
1072 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1073
1074 sample_count = div_s64(transferred_len, sample_size);
1075
1076 /*
1077 * interval between samples is total time since last transfer handling
1078 * divided by the number of samples (total size divided by sample size)
1079 */
1080 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1081
1082 while (transferred_len >= sample_size) {
1083 /*
1084 * for all the values in the current sample,
1085 * adjust the values inside the buffer for oversampling
1086 */
1087 at91_adc_adjust_val_osr_array(st,
1088 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1089 sample_size);
1090
1091 iio_push_to_buffers_with_timestamp(indio_dev,
1092 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1093 (st->dma_st.dma_ts + interval * sample_index));
1094 /* adjust remaining length */
1095 transferred_len -= sample_size;
1096 /* adjust buffer index */
1097 st->dma_st.buf_idx += sample_size;
1098 /* in case of reaching end of buffer, reset index */
1099 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1100 st->dma_st.buf_idx = 0;
1101 sample_index++;
1102 }
1103 /* adjust saved time for next transfer handling */
1104 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1105 }
1106
1107 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
1108 {
1109 struct iio_poll_func *pf = p;
1110 struct iio_dev *indio_dev = pf->indio_dev;
1111 struct at91_adc_state *st = iio_priv(indio_dev);
1112
1113 if (st->dma_st.dma_chan)
1114 at91_adc_trigger_handler_dma(indio_dev);
1115 else
1116 at91_adc_trigger_handler_nodma(indio_dev, pf);
1117
1118 iio_trigger_notify_done(indio_dev->trig);
1119
1120 return IRQ_HANDLED;
1121 }
1122
1123 static int at91_adc_buffer_init(struct iio_dev *indio)
1124 {
1125 struct at91_adc_state *st = iio_priv(indio);
1126
1127 if (st->selected_trig->hw_trig) {
1128 return devm_iio_triggered_buffer_setup(&indio->dev, indio,
1129 &iio_pollfunc_store_time,
1130 &at91_adc_trigger_handler, &at91_buffer_setup_ops);
1131 }
1132 /*
1133 * we need to prepare the buffer ops in case we will get
1134 * another buffer attached (like a callback buffer for the touchscreen)
1135 */
1136 indio->setup_ops = &at91_buffer_setup_ops;
1137
1138 return 0;
1139 }
1140
1141 static unsigned at91_adc_startup_time(unsigned startup_time_min,
1142 unsigned adc_clk_khz)
1143 {
1144 static const unsigned int startup_lookup[] = {
1145 0, 8, 16, 24,
1146 64, 80, 96, 112,
1147 512, 576, 640, 704,
1148 768, 832, 896, 960
1149 };
1150 unsigned ticks_min, i;
1151
1152 /*
1153 * Since the adc frequency is checked before, there is no reason
1154 * to not meet the startup time constraint.
1155 */
1156
1157 ticks_min = startup_time_min * adc_clk_khz / 1000;
1158 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
1159 if (startup_lookup[i] > ticks_min)
1160 break;
1161
1162 return i;
1163 }
1164
1165 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
1166 {
1167 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1168 unsigned f_per, prescal, startup, mr;
1169
1170 f_per = clk_get_rate(st->per_clk);
1171 prescal = (f_per / (2 * freq)) - 1;
1172
1173 startup = at91_adc_startup_time(st->soc_info.startup_time,
1174 freq / 1000);
1175
1176 mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
1177 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
1178 mr |= AT91_SAMA5D2_MR_STARTUP(startup);
1179 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
1180 at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
1181
1182 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
1183 freq, startup, prescal);
1184 st->current_sample_rate = freq;
1185 }
1186
1187 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1188 {
1189 return st->current_sample_rate;
1190 }
1191
1192 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
1193 {
1194 struct at91_adc_state *st = iio_priv(indio_dev);
1195 u8 bit;
1196 u16 val;
1197 int i = 0;
1198
1199 for_each_set_bit(bit, indio_dev->active_scan_mask,
1200 AT91_SAMA5D2_MAX_CHAN_IDX + 1) {
1201 struct iio_chan_spec const *chan =
1202 at91_adc_chan_get(indio_dev, bit);
1203
1204 if (chan->type == IIO_POSITIONRELATIVE)
1205 at91_adc_read_position(st, chan->channel, &val);
1206 else if (chan->type == IIO_PRESSURE)
1207 at91_adc_read_pressure(st, chan->channel, &val);
1208 else
1209 continue;
1210 st->buffer[i] = val;
1211 i++;
1212 }
1213 /*
1214 * Schedule work to push to buffers.
1215 * This is intended to push to the callback buffer that another driver
1216 * registered. We are still in a handler from our IRQ. If we push
1217 * directly, it means the other driver has it's callback called
1218 * from our IRQ context. Which is something we better avoid.
1219 * Let's schedule it after our IRQ is completed.
1220 */
1221 schedule_work(&st->touch_st.workq);
1222 }
1223
1224 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1225 {
1226 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);
1227 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |
1228 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1229 AT91_SAMA5D2_IER_PRDY);
1230 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1231 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1232 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1233 st->touch_st.touching = true;
1234 }
1235
1236 static void at91_adc_no_pen_detect_interrupt(struct at91_adc_state *st)
1237 {
1238 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1239
1240 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1241 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1242 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |
1243 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1244 AT91_SAMA5D2_IER_PRDY);
1245 st->touch_st.touching = false;
1246
1247 at91_adc_touch_data_handler(indio_dev);
1248
1249 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
1250 }
1251
1252 static void at91_adc_workq_handler(struct work_struct *workq)
1253 {
1254 struct at91_adc_touch *touch_st = container_of(workq,
1255 struct at91_adc_touch, workq);
1256 struct at91_adc_state *st = container_of(touch_st,
1257 struct at91_adc_state, touch_st);
1258 struct iio_dev *indio_dev = iio_priv_to_dev(st);
1259
1260 iio_push_to_buffers(indio_dev, st->buffer);
1261 }
1262
1263 static irqreturn_t at91_adc_interrupt(int irq, void *private)
1264 {
1265 struct iio_dev *indio = private;
1266 struct at91_adc_state *st = iio_priv(indio);
1267 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1268 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
1269 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1270 AT91_SAMA5D2_IER_PRDY;
1271
1272 if (!(status & imr))
1273 return IRQ_NONE;
1274 if (status & AT91_SAMA5D2_IER_PEN) {
1275 /* pen detected IRQ */
1276 at91_adc_pen_detect_interrupt(st);
1277 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
1278 /* nopen detected IRQ */
1279 at91_adc_no_pen_detect_interrupt(st);
1280 } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
1281 ((status & rdy_mask) == rdy_mask)) {
1282 /* periodic trigger IRQ - during pen sense */
1283 at91_adc_touch_data_handler(indio);
1284 } else if (status & AT91_SAMA5D2_ISR_PENS) {
1285 /*
1286 * touching, but the measurements are not ready yet.
1287 * read and ignore.
1288 */
1289 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
1290 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
1291 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
1292 } else if (iio_buffer_enabled(indio) && !st->dma_st.dma_chan) {
1293 /* triggered buffer without DMA */
1294 disable_irq_nosync(irq);
1295 iio_trigger_poll(indio->trig);
1296 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1297 /* triggered buffer with DMA - should not happen */
1298 disable_irq_nosync(irq);
1299 WARN(true, "Unexpected irq occurred\n");
1300 } else if (!iio_buffer_enabled(indio)) {
1301 /* software requested conversion */
1302 st->conversion_value = at91_adc_readl(st, st->chan->address);
1303 st->conversion_done = true;
1304 wake_up_interruptible(&st->wq_data_available);
1305 }
1306 return IRQ_HANDLED;
1307 }
1308
1309 static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
1310 struct iio_chan_spec const *chan, int *val)
1311 {
1312 struct at91_adc_state *st = iio_priv(indio_dev);
1313 u32 cor = 0;
1314 u16 tmp_val;
1315 int ret;
1316
1317 /*
1318 * Keep in mind that we cannot use software trigger or touchscreen
1319 * if external trigger is enabled
1320 */
1321 if (chan->type == IIO_POSITIONRELATIVE) {
1322 ret = iio_device_claim_direct_mode(indio_dev);
1323 if (ret)
1324 return ret;
1325 mutex_lock(&st->lock);
1326
1327 ret = at91_adc_read_position(st, chan->channel,
1328 &tmp_val);
1329 *val = tmp_val;
1330 mutex_unlock(&st->lock);
1331 iio_device_release_direct_mode(indio_dev);
1332
1333 return at91_adc_adjust_val_osr(st, val);
1334 }
1335 if (chan->type == IIO_PRESSURE) {
1336 ret = iio_device_claim_direct_mode(indio_dev);
1337 if (ret)
1338 return ret;
1339 mutex_lock(&st->lock);
1340
1341 ret = at91_adc_read_pressure(st, chan->channel,
1342 &tmp_val);
1343 *val = tmp_val;
1344 mutex_unlock(&st->lock);
1345 iio_device_release_direct_mode(indio_dev);
1346
1347 return at91_adc_adjust_val_osr(st, val);
1348 }
1349
1350 /* in this case we have a voltage channel */
1351
1352 ret = iio_device_claim_direct_mode(indio_dev);
1353 if (ret)
1354 return ret;
1355 mutex_lock(&st->lock);
1356
1357 st->chan = chan;
1358
1359 if (chan->differential)
1360 cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
1361 AT91_SAMA5D2_COR_DIFF_OFFSET;
1362
1363 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
1364 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
1365 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
1366 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1367
1368 ret = wait_event_interruptible_timeout(st->wq_data_available,
1369 st->conversion_done,
1370 msecs_to_jiffies(1000));
1371 if (ret == 0)
1372 ret = -ETIMEDOUT;
1373
1374 if (ret > 0) {
1375 *val = st->conversion_value;
1376 ret = at91_adc_adjust_val_osr(st, val);
1377 if (chan->scan_type.sign == 's')
1378 *val = sign_extend32(*val, 11);
1379 st->conversion_done = false;
1380 }
1381
1382 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
1383 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
1384
1385 /* Needed to ACK the DRDY interruption */
1386 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
1387
1388 mutex_unlock(&st->lock);
1389
1390 iio_device_release_direct_mode(indio_dev);
1391 return ret;
1392 }
1393
1394 static int at91_adc_read_raw(struct iio_dev *indio_dev,
1395 struct iio_chan_spec const *chan,
1396 int *val, int *val2, long mask)
1397 {
1398 struct at91_adc_state *st = iio_priv(indio_dev);
1399
1400 switch (mask) {
1401 case IIO_CHAN_INFO_RAW:
1402 return at91_adc_read_info_raw(indio_dev, chan, val);
1403 case IIO_CHAN_INFO_SCALE:
1404 *val = st->vref_uv / 1000;
1405 if (chan->differential)
1406 *val *= 2;
1407 *val2 = chan->scan_type.realbits;
1408 return IIO_VAL_FRACTIONAL_LOG2;
1409
1410 case IIO_CHAN_INFO_SAMP_FREQ:
1411 *val = at91_adc_get_sample_freq(st);
1412 return IIO_VAL_INT;
1413
1414 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1415 *val = st->oversampling_ratio;
1416 return IIO_VAL_INT;
1417
1418 default:
1419 return -EINVAL;
1420 }
1421 }
1422
1423 static int at91_adc_write_raw(struct iio_dev *indio_dev,
1424 struct iio_chan_spec const *chan,
1425 int val, int val2, long mask)
1426 {
1427 struct at91_adc_state *st = iio_priv(indio_dev);
1428
1429 switch (mask) {
1430 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1431 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
1432 (val != AT91_OSR_16SAMPLES))
1433 return -EINVAL;
1434 /* if no change, optimize out */
1435 if (val == st->oversampling_ratio)
1436 return 0;
1437 st->oversampling_ratio = val;
1438 /* update ratio */
1439 at91_adc_config_emr(st);
1440 return 0;
1441 case IIO_CHAN_INFO_SAMP_FREQ:
1442 if (val < st->soc_info.min_sample_rate ||
1443 val > st->soc_info.max_sample_rate)
1444 return -EINVAL;
1445
1446 at91_adc_setup_samp_freq(st, val);
1447 return 0;
1448 default:
1449 return -EINVAL;
1450 };
1451 }
1452
1453 static void at91_adc_dma_init(struct platform_device *pdev)
1454 {
1455 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1456 struct at91_adc_state *st = iio_priv(indio_dev);
1457 struct dma_slave_config config = {0};
1458 /*
1459 * We make the buffer double the size of the fifo,
1460 * such that DMA uses one half of the buffer (full fifo size)
1461 * and the software uses the other half to read/write.
1462 */
1463 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1464 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1465 PAGE_SIZE);
1466
1467 if (st->dma_st.dma_chan)
1468 return;
1469
1470 st->dma_st.dma_chan = dma_request_slave_channel(&pdev->dev, "rx");
1471
1472 if (!st->dma_st.dma_chan) {
1473 dev_info(&pdev->dev, "can't get DMA channel\n");
1474 goto dma_exit;
1475 }
1476
1477 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
1478 pages * PAGE_SIZE,
1479 &st->dma_st.rx_dma_buf,
1480 GFP_KERNEL);
1481 if (!st->dma_st.rx_buf) {
1482 dev_info(&pdev->dev, "can't allocate coherent DMA area\n");
1483 goto dma_chan_disable;
1484 }
1485
1486 /* Configure DMA channel to read data register */
1487 config.direction = DMA_DEV_TO_MEM;
1488 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
1489 + AT91_SAMA5D2_LCDR);
1490 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1491 config.src_maxburst = 1;
1492 config.dst_maxburst = 1;
1493
1494 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
1495 dev_info(&pdev->dev, "can't configure DMA slave\n");
1496 goto dma_free_area;
1497 }
1498
1499 dev_info(&pdev->dev, "using %s for rx DMA transfers\n",
1500 dma_chan_name(st->dma_st.dma_chan));
1501
1502 return;
1503
1504 dma_free_area:
1505 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1506 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1507 dma_chan_disable:
1508 dma_release_channel(st->dma_st.dma_chan);
1509 st->dma_st.dma_chan = 0;
1510 dma_exit:
1511 dev_info(&pdev->dev, "continuing without DMA support\n");
1512 }
1513
1514 static void at91_adc_dma_disable(struct platform_device *pdev)
1515 {
1516 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1517 struct at91_adc_state *st = iio_priv(indio_dev);
1518 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1519 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1520 PAGE_SIZE);
1521
1522 /* if we are not using DMA, just return */
1523 if (!st->dma_st.dma_chan)
1524 return;
1525
1526 /* wait for all transactions to be terminated first*/
1527 dmaengine_terminate_sync(st->dma_st.dma_chan);
1528
1529 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1530 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1531 dma_release_channel(st->dma_st.dma_chan);
1532 st->dma_st.dma_chan = 0;
1533
1534 dev_info(&pdev->dev, "continuing without DMA support\n");
1535 }
1536
1537 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1538 {
1539 struct at91_adc_state *st = iio_priv(indio_dev);
1540
1541 if (val > AT91_HWFIFO_MAX_SIZE)
1542 return -EINVAL;
1543
1544 if (!st->selected_trig->hw_trig) {
1545 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
1546 return 0;
1547 }
1548
1549 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
1550 st->dma_st.watermark = val;
1551
1552 /*
1553 * The logic here is: if we have watermark 1, it means we do
1554 * each conversion with it's own IRQ, thus we don't need DMA.
1555 * If the watermark is higher, we do DMA to do all the transfers in bulk
1556 */
1557
1558 if (val == 1)
1559 at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
1560 else if (val > 1)
1561 at91_adc_dma_init(to_platform_device(&indio_dev->dev));
1562
1563 return 0;
1564 }
1565
1566 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
1567 const unsigned long *scan_mask)
1568 {
1569 struct at91_adc_state *st = iio_priv(indio_dev);
1570
1571 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
1572 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1573 return 0;
1574 /*
1575 * if the new bitmap is a combination of touchscreen and regular
1576 * channels, then we are not fine
1577 */
1578 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
1579 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1580 return -EINVAL;
1581 return 0;
1582 }
1583
1584 static void at91_adc_hw_init(struct at91_adc_state *st)
1585 {
1586 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1587 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
1588 /*
1589 * Transfer field must be set to 2 according to the datasheet and
1590 * allows different analog settings for each channel.
1591 */
1592 at91_adc_writel(st, AT91_SAMA5D2_MR,
1593 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
1594
1595 at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
1596
1597 /* configure extended mode register */
1598 at91_adc_config_emr(st);
1599 }
1600
1601 static ssize_t at91_adc_get_fifo_state(struct device *dev,
1602 struct device_attribute *attr, char *buf)
1603 {
1604 struct iio_dev *indio_dev =
1605 platform_get_drvdata(to_platform_device(dev));
1606 struct at91_adc_state *st = iio_priv(indio_dev);
1607
1608 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
1609 }
1610
1611 static ssize_t at91_adc_get_watermark(struct device *dev,
1612 struct device_attribute *attr, char *buf)
1613 {
1614 struct iio_dev *indio_dev =
1615 platform_get_drvdata(to_platform_device(dev));
1616 struct at91_adc_state *st = iio_priv(indio_dev);
1617
1618 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
1619 }
1620
1621 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1622 at91_adc_get_fifo_state, NULL, 0);
1623 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1624 at91_adc_get_watermark, NULL, 0);
1625
1626 static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
1627 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
1628
1629 static IIO_CONST_ATTR(oversampling_ratio_available,
1630 __stringify(AT91_OSR_1SAMPLES) " "
1631 __stringify(AT91_OSR_4SAMPLES) " "
1632 __stringify(AT91_OSR_16SAMPLES));
1633
1634 static struct attribute *at91_adc_attributes[] = {
1635 &iio_const_attr_oversampling_ratio_available.dev_attr.attr,
1636 NULL,
1637 };
1638
1639 static const struct attribute_group at91_adc_attribute_group = {
1640 .attrs = at91_adc_attributes,
1641 };
1642
1643 static const struct attribute *at91_adc_fifo_attributes[] = {
1644 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
1645 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
1646 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
1647 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
1648 NULL,
1649 };
1650
1651 static const struct iio_info at91_adc_info = {
1652 .attrs = &at91_adc_attribute_group,
1653 .read_raw = &at91_adc_read_raw,
1654 .write_raw = &at91_adc_write_raw,
1655 .update_scan_mode = &at91_adc_update_scan_mode,
1656 .of_xlate = &at91_adc_of_xlate,
1657 .hwfifo_set_watermark = &at91_adc_set_watermark,
1658 };
1659
1660 static int at91_adc_probe(struct platform_device *pdev)
1661 {
1662 struct iio_dev *indio_dev;
1663 struct at91_adc_state *st;
1664 struct resource *res;
1665 int ret, i;
1666 u32 edge_type = IRQ_TYPE_NONE;
1667
1668 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
1669 if (!indio_dev)
1670 return -ENOMEM;
1671
1672 indio_dev->dev.parent = &pdev->dev;
1673 indio_dev->name = dev_name(&pdev->dev);
1674 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1675 indio_dev->info = &at91_adc_info;
1676 indio_dev->channels = at91_adc_channels;
1677 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
1678
1679 st = iio_priv(indio_dev);
1680
1681 bitmap_set(&st->touch_st.channels_bitmask,
1682 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1);
1683 bitmap_set(&st->touch_st.channels_bitmask,
1684 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1);
1685 bitmap_set(&st->touch_st.channels_bitmask,
1686 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1);
1687
1688 st->oversampling_ratio = AT91_OSR_1SAMPLES;
1689
1690 ret = of_property_read_u32(pdev->dev.of_node,
1691 "atmel,min-sample-rate-hz",
1692 &st->soc_info.min_sample_rate);
1693 if (ret) {
1694 dev_err(&pdev->dev,
1695 "invalid or missing value for atmel,min-sample-rate-hz\n");
1696 return ret;
1697 }
1698
1699 ret = of_property_read_u32(pdev->dev.of_node,
1700 "atmel,max-sample-rate-hz",
1701 &st->soc_info.max_sample_rate);
1702 if (ret) {
1703 dev_err(&pdev->dev,
1704 "invalid or missing value for atmel,max-sample-rate-hz\n");
1705 return ret;
1706 }
1707
1708 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
1709 &st->soc_info.startup_time);
1710 if (ret) {
1711 dev_err(&pdev->dev,
1712 "invalid or missing value for atmel,startup-time-ms\n");
1713 return ret;
1714 }
1715
1716 ret = of_property_read_u32(pdev->dev.of_node,
1717 "atmel,trigger-edge-type", &edge_type);
1718 if (ret) {
1719 dev_dbg(&pdev->dev,
1720 "atmel,trigger-edge-type not specified, only software trigger available\n");
1721 }
1722
1723 st->selected_trig = NULL;
1724
1725 /* find the right trigger, or no trigger at all */
1726 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
1727 if (at91_adc_trigger_list[i].edge_type == edge_type) {
1728 st->selected_trig = &at91_adc_trigger_list[i];
1729 break;
1730 }
1731
1732 if (!st->selected_trig) {
1733 dev_err(&pdev->dev, "invalid external trigger edge value\n");
1734 return -EINVAL;
1735 }
1736
1737 init_waitqueue_head(&st->wq_data_available);
1738 mutex_init(&st->lock);
1739 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
1740
1741 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1742 if (!res)
1743 return -EINVAL;
1744
1745 /* if we plan to use DMA, we need the physical address of the regs */
1746 st->dma_st.phys_addr = res->start;
1747
1748 st->base = devm_ioremap_resource(&pdev->dev, res);
1749 if (IS_ERR(st->base))
1750 return PTR_ERR(st->base);
1751
1752 st->irq = platform_get_irq(pdev, 0);
1753 if (st->irq <= 0) {
1754 if (!st->irq)
1755 st->irq = -ENXIO;
1756
1757 return st->irq;
1758 }
1759
1760 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
1761 if (IS_ERR(st->per_clk))
1762 return PTR_ERR(st->per_clk);
1763
1764 st->reg = devm_regulator_get(&pdev->dev, "vddana");
1765 if (IS_ERR(st->reg))
1766 return PTR_ERR(st->reg);
1767
1768 st->vref = devm_regulator_get(&pdev->dev, "vref");
1769 if (IS_ERR(st->vref))
1770 return PTR_ERR(st->vref);
1771
1772 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
1773 pdev->dev.driver->name, indio_dev);
1774 if (ret)
1775 return ret;
1776
1777 ret = regulator_enable(st->reg);
1778 if (ret)
1779 return ret;
1780
1781 ret = regulator_enable(st->vref);
1782 if (ret)
1783 goto reg_disable;
1784
1785 st->vref_uv = regulator_get_voltage(st->vref);
1786 if (st->vref_uv <= 0) {
1787 ret = -EINVAL;
1788 goto vref_disable;
1789 }
1790
1791 at91_adc_hw_init(st);
1792
1793 ret = clk_prepare_enable(st->per_clk);
1794 if (ret)
1795 goto vref_disable;
1796
1797 platform_set_drvdata(pdev, indio_dev);
1798
1799 ret = at91_adc_buffer_init(indio_dev);
1800 if (ret < 0) {
1801 dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
1802 goto per_clk_disable_unprepare;
1803 }
1804
1805 if (st->selected_trig->hw_trig) {
1806 ret = at91_adc_trigger_init(indio_dev);
1807 if (ret < 0) {
1808 dev_err(&pdev->dev, "couldn't setup the triggers.\n");
1809 goto per_clk_disable_unprepare;
1810 }
1811 /*
1812 * Initially the iio buffer has a length of 2 and
1813 * a watermark of 1
1814 */
1815 st->dma_st.watermark = 1;
1816
1817 iio_buffer_set_attrs(indio_dev->buffer,
1818 at91_adc_fifo_attributes);
1819 }
1820
1821 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
1822 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
1823
1824 ret = iio_device_register(indio_dev);
1825 if (ret < 0)
1826 goto dma_disable;
1827
1828 if (st->selected_trig->hw_trig)
1829 dev_info(&pdev->dev, "setting up trigger as %s\n",
1830 st->selected_trig->name);
1831
1832 dev_info(&pdev->dev, "version: %x\n",
1833 readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
1834
1835 return 0;
1836
1837 dma_disable:
1838 at91_adc_dma_disable(pdev);
1839 per_clk_disable_unprepare:
1840 clk_disable_unprepare(st->per_clk);
1841 vref_disable:
1842 regulator_disable(st->vref);
1843 reg_disable:
1844 regulator_disable(st->reg);
1845 return ret;
1846 }
1847
1848 static int at91_adc_remove(struct platform_device *pdev)
1849 {
1850 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1851 struct at91_adc_state *st = iio_priv(indio_dev);
1852
1853 iio_device_unregister(indio_dev);
1854
1855 at91_adc_dma_disable(pdev);
1856
1857 clk_disable_unprepare(st->per_clk);
1858
1859 regulator_disable(st->vref);
1860 regulator_disable(st->reg);
1861
1862 return 0;
1863 }
1864
1865 static __maybe_unused int at91_adc_suspend(struct device *dev)
1866 {
1867 struct iio_dev *indio_dev =
1868 platform_get_drvdata(to_platform_device(dev));
1869 struct at91_adc_state *st = iio_priv(indio_dev);
1870
1871 /*
1872 * Do a sofware reset of the ADC before we go to suspend.
1873 * this will ensure that all pins are free from being muxed by the ADC
1874 * and can be used by for other devices.
1875 * Otherwise, ADC will hog them and we can't go to suspend mode.
1876 */
1877 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1878
1879 clk_disable_unprepare(st->per_clk);
1880 regulator_disable(st->vref);
1881 regulator_disable(st->reg);
1882
1883 return pinctrl_pm_select_sleep_state(dev);
1884 }
1885
1886 static __maybe_unused int at91_adc_resume(struct device *dev)
1887 {
1888 struct iio_dev *indio_dev =
1889 platform_get_drvdata(to_platform_device(dev));
1890 struct at91_adc_state *st = iio_priv(indio_dev);
1891 int ret;
1892
1893 ret = pinctrl_pm_select_default_state(dev);
1894 if (ret)
1895 goto resume_failed;
1896
1897 ret = regulator_enable(st->reg);
1898 if (ret)
1899 goto resume_failed;
1900
1901 ret = regulator_enable(st->vref);
1902 if (ret)
1903 goto reg_disable_resume;
1904
1905 ret = clk_prepare_enable(st->per_clk);
1906 if (ret)
1907 goto vref_disable_resume;
1908
1909 at91_adc_hw_init(st);
1910
1911 /* reconfiguring trigger hardware state */
1912 if (!iio_buffer_enabled(indio_dev))
1913 return 0;
1914
1915 /* check if we are enabling triggered buffer or the touchscreen */
1916 if (bitmap_subset(indio_dev->active_scan_mask,
1917 &st->touch_st.channels_bitmask,
1918 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) {
1919 /* touchscreen enabling */
1920 return at91_adc_configure_touch(st, true);
1921 } else {
1922 return at91_adc_configure_trigger(st->trig, true);
1923 }
1924
1925 /* not needed but more explicit */
1926 return 0;
1927
1928 vref_disable_resume:
1929 regulator_disable(st->vref);
1930 reg_disable_resume:
1931 regulator_disable(st->reg);
1932 resume_failed:
1933 dev_err(&indio_dev->dev, "failed to resume\n");
1934 return ret;
1935 }
1936
1937 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1938
1939 static const struct of_device_id at91_adc_dt_match[] = {
1940 {
1941 .compatible = "atmel,sama5d2-adc",
1942 }, {
1943 /* sentinel */
1944 }
1945 };
1946 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
1947
1948 static struct platform_driver at91_adc_driver = {
1949 .probe = at91_adc_probe,
1950 .remove = at91_adc_remove,
1951 .driver = {
1952 .name = "at91-sama5d2_adc",
1953 .of_match_table = at91_adc_dt_match,
1954 .pm = &at91_adc_pm_ops,
1955 },
1956 };
1957 module_platform_driver(at91_adc_driver)
1958
1959 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1960 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
1961 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support