?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / iio / adc / stm32-adc.c
blob59fd8b620c50fd841391e5d363ce60c74e0e11bb
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/iio/iio.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27
28 #include "stm32-adc-core.h"
29
30 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
31 #define STM32H7_LINCALFACT_NUM 6
32
33 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
34 #define STM32H7_BOOST_CLKRATE 20000000UL
35
36 #define STM32_ADC_CH_MAX 20 /* max number of channels */
37 #define STM32_ADC_CH_SZ 10 /* max channel name size */
38 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
39 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
40 #define STM32_ADC_TIMEOUT_US 100000
41 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
42
43 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
44
45 /* External trigger enable */
46 enum stm32_adc_exten {
47 STM32_EXTEN_SWTRIG,
48 STM32_EXTEN_HWTRIG_RISING_EDGE,
49 STM32_EXTEN_HWTRIG_FALLING_EDGE,
50 STM32_EXTEN_HWTRIG_BOTH_EDGES,
51 };
52
53 /* extsel - trigger mux selection value */
54 enum stm32_adc_extsel {
55 STM32_EXT0,
56 STM32_EXT1,
57 STM32_EXT2,
58 STM32_EXT3,
59 STM32_EXT4,
60 STM32_EXT5,
61 STM32_EXT6,
62 STM32_EXT7,
63 STM32_EXT8,
64 STM32_EXT9,
65 STM32_EXT10,
66 STM32_EXT11,
67 STM32_EXT12,
68 STM32_EXT13,
69 STM32_EXT14,
70 STM32_EXT15,
71 STM32_EXT16,
72 STM32_EXT17,
73 STM32_EXT18,
74 STM32_EXT19,
75 STM32_EXT20,
76 };
77
78 /**
79 * struct stm32_adc_trig_info - ADC trigger info
80 * @name: name of the trigger, corresponding to its source
81 * @extsel: trigger selection
82 */
83 struct stm32_adc_trig_info {
84 const char *name;
85 enum stm32_adc_extsel extsel;
86 };
87
88 /**
89 * struct stm32_adc_calib - optional adc calibration data
90 * @calfact_s: Calibration offset for single ended channels
91 * @calfact_d: Calibration offset in differential
92 * @lincalfact: Linearity calibration factor
93 */
94 struct stm32_adc_calib {
95 u32 calfact_s;
96 u32 calfact_d;
97 u32 lincalfact[STM32H7_LINCALFACT_NUM];
98 };
99
100 /**
101 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
102 * @reg: register offset
103 * @mask: bitfield mask
104 * @shift: left shift
105 */
106 struct stm32_adc_regs {
107 int reg;
108 int mask;
109 int shift;
110 };
111
112 /**
113 * stm32_adc_regspec - stm32 registers definition, compatible dependent data
114 * @dr: data register offset
115 * @ier_eoc: interrupt enable register & eocie bitfield
116 * @isr_eoc: interrupt status register & eoc bitfield
117 * @sqr: reference to sequence registers array
118 * @exten: trigger control register & bitfield
119 * @extsel: trigger selection register & bitfield
120 * @res: resolution selection register & bitfield
121 * @smpr: smpr1 & smpr2 registers offset array
122 * @smp_bits: smpr1 & smpr2 index and bitfields
123 */
124 struct stm32_adc_regspec {
125 const u32 dr;
126 const struct stm32_adc_regs ier_eoc;
127 const struct stm32_adc_regs isr_eoc;
128 const struct stm32_adc_regs *sqr;
129 const struct stm32_adc_regs exten;
130 const struct stm32_adc_regs extsel;
131 const struct stm32_adc_regs res;
132 const u32 smpr[2];
133 const struct stm32_adc_regs *smp_bits;
134 };
135
136 struct stm32_adc;
137
138 /**
139 * stm32_adc_cfg - stm32 compatible configuration data
140 * @regs: registers descriptions
141 * @adc_info: per instance input channels definitions
142 * @trigs: external trigger sources
143 * @clk_required: clock is required
144 * @has_vregready: vregready status flag presence
145 * @selfcalib: optional routine for self-calibration
146 * @prepare: optional prepare routine (power-up, enable)
147 * @start_conv: routine to start conversions
148 * @stop_conv: routine to stop conversions
149 * @unprepare: optional unprepare routine (disable, power-down)
150 * @smp_cycles: programmable sampling time (ADC clock cycles)
151 */
152 struct stm32_adc_cfg {
153 const struct stm32_adc_regspec *regs;
154 const struct stm32_adc_info *adc_info;
155 struct stm32_adc_trig_info *trigs;
156 bool clk_required;
157 bool has_vregready;
158 int (*selfcalib)(struct stm32_adc *);
159 int (*prepare)(struct stm32_adc *);
160 void (*start_conv)(struct stm32_adc *, bool dma);
161 void (*stop_conv)(struct stm32_adc *);
162 void (*unprepare)(struct stm32_adc *);
163 const unsigned int *smp_cycles;
164 };
165
166 /**
167 * struct stm32_adc - private data of each ADC IIO instance
168 * @common: reference to ADC block common data
169 * @offset: ADC instance register offset in ADC block
170 * @cfg: compatible configuration data
171 * @completion: end of single conversion completion
172 * @buffer: data buffer
173 * @clk: clock for this adc instance
174 * @irq: interrupt for this adc instance
175 * @lock: spinlock
176 * @bufi: data buffer index
177 * @num_conv: expected number of scan conversions
178 * @res: data resolution (e.g. RES bitfield value)
179 * @trigger_polarity: external trigger polarity (e.g. exten)
180 * @dma_chan: dma channel
181 * @rx_buf: dma rx buffer cpu address
182 * @rx_dma_buf: dma rx buffer bus address
183 * @rx_buf_sz: dma rx buffer size
184 * @difsel bitmask to set single-ended/differential channel
185 * @pcsel bitmask to preselect channels on some devices
186 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
187 * @cal: optional calibration data on some devices
188 * @chan_name: channel name array
189 */
190 struct stm32_adc {
191 struct stm32_adc_common *common;
192 u32 offset;
193 const struct stm32_adc_cfg *cfg;
194 struct completion completion;
195 u16 buffer[STM32_ADC_MAX_SQ];
196 struct clk *clk;
197 int irq;
198 spinlock_t lock; /* interrupt lock */
199 unsigned int bufi;
200 unsigned int num_conv;
201 u32 res;
202 u32 trigger_polarity;
203 struct dma_chan *dma_chan;
204 u8 *rx_buf;
205 dma_addr_t rx_dma_buf;
206 unsigned int rx_buf_sz;
207 u32 difsel;
208 u32 pcsel;
209 u32 smpr_val[2];
210 struct stm32_adc_calib cal;
211 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ];
212 };
213
214 struct stm32_adc_diff_channel {
215 u32 vinp;
216 u32 vinn;
217 };
218
219 /**
220 * struct stm32_adc_info - stm32 ADC, per instance config data
221 * @max_channels: Number of channels
222 * @resolutions: available resolutions
223 * @num_res: number of available resolutions
224 */
225 struct stm32_adc_info {
226 int max_channels;
227 const unsigned int *resolutions;
228 const unsigned int num_res;
229 };
230
231 static const unsigned int stm32f4_adc_resolutions[] = {
232 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
233 12, 10, 8, 6,
234 };
235
236 /* stm32f4 can have up to 16 channels */
237 static const struct stm32_adc_info stm32f4_adc_info = {
238 .max_channels = 16,
239 .resolutions = stm32f4_adc_resolutions,
240 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
241 };
242
243 static const unsigned int stm32h7_adc_resolutions[] = {
244 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
245 16, 14, 12, 10, 8,
246 };
247
248 /* stm32h7 can have up to 20 channels */
249 static const struct stm32_adc_info stm32h7_adc_info = {
250 .max_channels = STM32_ADC_CH_MAX,
251 .resolutions = stm32h7_adc_resolutions,
252 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
253 };
254
255 /**
256 * stm32f4_sq - describe regular sequence registers
257 * - L: sequence len (register & bit field)
258 * - SQ1..SQ16: sequence entries (register & bit field)
259 */
260 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
261 /* L: len bit field description to be kept as first element */
262 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
263 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
264 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
265 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
266 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
267 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
268 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
269 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
270 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
271 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
272 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
273 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
274 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
275 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
276 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
277 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
278 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
279 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
280 };
281
282 /* STM32F4 external trigger sources for all instances */
283 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
284 { TIM1_CH1, STM32_EXT0 },
285 { TIM1_CH2, STM32_EXT1 },
286 { TIM1_CH3, STM32_EXT2 },
287 { TIM2_CH2, STM32_EXT3 },
288 { TIM2_CH3, STM32_EXT4 },
289 { TIM2_CH4, STM32_EXT5 },
290 { TIM2_TRGO, STM32_EXT6 },
291 { TIM3_CH1, STM32_EXT7 },
292 { TIM3_TRGO, STM32_EXT8 },
293 { TIM4_CH4, STM32_EXT9 },
294 { TIM5_CH1, STM32_EXT10 },
295 { TIM5_CH2, STM32_EXT11 },
296 { TIM5_CH3, STM32_EXT12 },
297 { TIM8_CH1, STM32_EXT13 },
298 { TIM8_TRGO, STM32_EXT14 },
299 {}, /* sentinel */
300 };
301
302 /**
303 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
304 * Sorted so it can be indexed by channel number.
305 */
306 static const struct stm32_adc_regs stm32f4_smp_bits[] = {
307 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
308 { 1, GENMASK(2, 0), 0 },
309 { 1, GENMASK(5, 3), 3 },
310 { 1, GENMASK(8, 6), 6 },
311 { 1, GENMASK(11, 9), 9 },
312 { 1, GENMASK(14, 12), 12 },
313 { 1, GENMASK(17, 15), 15 },
314 { 1, GENMASK(20, 18), 18 },
315 { 1, GENMASK(23, 21), 21 },
316 { 1, GENMASK(26, 24), 24 },
317 { 1, GENMASK(29, 27), 27 },
318 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
319 { 0, GENMASK(2, 0), 0 },
320 { 0, GENMASK(5, 3), 3 },
321 { 0, GENMASK(8, 6), 6 },
322 { 0, GENMASK(11, 9), 9 },
323 { 0, GENMASK(14, 12), 12 },
324 { 0, GENMASK(17, 15), 15 },
325 { 0, GENMASK(20, 18), 18 },
326 { 0, GENMASK(23, 21), 21 },
327 { 0, GENMASK(26, 24), 24 },
328 };
329
330 /* STM32F4 programmable sampling time (ADC clock cycles) */
331 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
332 3, 15, 28, 56, 84, 112, 144, 480,
333 };
334
335 static const struct stm32_adc_regspec stm32f4_adc_regspec = {
336 .dr = STM32F4_ADC_DR,
337 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
338 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
339 .sqr = stm32f4_sq,
340 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
341 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
342 STM32F4_EXTSEL_SHIFT },
343 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
344 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
345 .smp_bits = stm32f4_smp_bits,
346 };
347
348 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
349 /* L: len bit field description to be kept as first element */
350 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
351 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
352 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
353 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
354 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
355 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
356 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
357 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
358 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
359 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
360 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
361 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
362 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
363 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
364 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
365 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
366 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
367 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
368 };
369
370 /* STM32H7 external trigger sources for all instances */
371 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
372 { TIM1_CH1, STM32_EXT0 },
373 { TIM1_CH2, STM32_EXT1 },
374 { TIM1_CH3, STM32_EXT2 },
375 { TIM2_CH2, STM32_EXT3 },
376 { TIM3_TRGO, STM32_EXT4 },
377 { TIM4_CH4, STM32_EXT5 },
378 { TIM8_TRGO, STM32_EXT7 },
379 { TIM8_TRGO2, STM32_EXT8 },
380 { TIM1_TRGO, STM32_EXT9 },
381 { TIM1_TRGO2, STM32_EXT10 },
382 { TIM2_TRGO, STM32_EXT11 },
383 { TIM4_TRGO, STM32_EXT12 },
384 { TIM6_TRGO, STM32_EXT13 },
385 { TIM15_TRGO, STM32_EXT14 },
386 { TIM3_CH4, STM32_EXT15 },
387 { LPTIM1_OUT, STM32_EXT18 },
388 { LPTIM2_OUT, STM32_EXT19 },
389 { LPTIM3_OUT, STM32_EXT20 },
390 {},
391 };
392
393 /**
394 * stm32h7_smp_bits - describe sampling time register index & bit fields
395 * Sorted so it can be indexed by channel number.
396 */
397 static const struct stm32_adc_regs stm32h7_smp_bits[] = {
398 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
399 { 0, GENMASK(2, 0), 0 },
400 { 0, GENMASK(5, 3), 3 },
401 { 0, GENMASK(8, 6), 6 },
402 { 0, GENMASK(11, 9), 9 },
403 { 0, GENMASK(14, 12), 12 },
404 { 0, GENMASK(17, 15), 15 },
405 { 0, GENMASK(20, 18), 18 },
406 { 0, GENMASK(23, 21), 21 },
407 { 0, GENMASK(26, 24), 24 },
408 { 0, GENMASK(29, 27), 27 },
409 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
410 { 1, GENMASK(2, 0), 0 },
411 { 1, GENMASK(5, 3), 3 },
412 { 1, GENMASK(8, 6), 6 },
413 { 1, GENMASK(11, 9), 9 },
414 { 1, GENMASK(14, 12), 12 },
415 { 1, GENMASK(17, 15), 15 },
416 { 1, GENMASK(20, 18), 18 },
417 { 1, GENMASK(23, 21), 21 },
418 { 1, GENMASK(26, 24), 24 },
419 { 1, GENMASK(29, 27), 27 },
420 };
421
422 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
423 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
424 1, 2, 8, 16, 32, 64, 387, 810,
425 };
426
427 static const struct stm32_adc_regspec stm32h7_adc_regspec = {
428 .dr = STM32H7_ADC_DR,
429 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
430 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
431 .sqr = stm32h7_sq,
432 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
433 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
434 STM32H7_EXTSEL_SHIFT },
435 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
436 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
437 .smp_bits = stm32h7_smp_bits,
438 };
439
440 /**
441 * STM32 ADC registers access routines
442 * @adc: stm32 adc instance
443 * @reg: reg offset in adc instance
444 *
445 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
446 * for adc1, adc2 and adc3.
447 */
448 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
449 {
450 return readl_relaxed(adc->common->base + adc->offset + reg);
451 }
452
453 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
454
455 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
456 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
457 cond, sleep_us, timeout_us)
458
459 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
460 {
461 return readw_relaxed(adc->common->base + adc->offset + reg);
462 }
463
464 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
465 {
466 writel_relaxed(val, adc->common->base + adc->offset + reg);
467 }
468
469 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
470 {
471 unsigned long flags;
472
473 spin_lock_irqsave(&adc->lock, flags);
474 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
475 spin_unlock_irqrestore(&adc->lock, flags);
476 }
477
478 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
479 {
480 unsigned long flags;
481
482 spin_lock_irqsave(&adc->lock, flags);
483 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
484 spin_unlock_irqrestore(&adc->lock, flags);
485 }
486
487 /**
488 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
489 * @adc: stm32 adc instance
490 */
491 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
492 {
493 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
494 adc->cfg->regs->ier_eoc.mask);
495 };
496
497 /**
498 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
499 * @adc: stm32 adc instance
500 */
501 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
502 {
503 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
504 adc->cfg->regs->ier_eoc.mask);
505 }
506
507 static void stm32_adc_set_res(struct stm32_adc *adc)
508 {
509 const struct stm32_adc_regs *res = &adc->cfg->regs->res;
510 u32 val;
511
512 val = stm32_adc_readl(adc, res->reg);
513 val = (val & ~res->mask) | (adc->res << res->shift);
514 stm32_adc_writel(adc, res->reg, val);
515 }
516
517 /**
518 * stm32f4_adc_start_conv() - Start conversions for regular channels.
519 * @adc: stm32 adc instance
520 * @dma: use dma to transfer conversion result
521 *
522 * Start conversions for regular channels.
523 * Also take care of normal or DMA mode. Circular DMA may be used for regular
524 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
525 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
526 */
527 static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
528 {
529 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
530
531 if (dma)
532 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
533 STM32F4_DMA | STM32F4_DDS);
534
535 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
536
537 /* Wait for Power-up time (tSTAB from datasheet) */
538 usleep_range(2, 3);
539
540 /* Software start ? (e.g. trigger detection disabled ?) */
541 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
542 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
543 }
544
545 static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
546 {
547 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
548 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
549
550 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
551 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
552 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
553 }
554
555 static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
556 {
557 enum stm32h7_adc_dmngt dmngt;
558 unsigned long flags;
559 u32 val;
560
561 if (dma)
562 dmngt = STM32H7_DMNGT_DMA_CIRC;
563 else
564 dmngt = STM32H7_DMNGT_DR_ONLY;
565
566 spin_lock_irqsave(&adc->lock, flags);
567 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
568 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
569 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
570 spin_unlock_irqrestore(&adc->lock, flags);
571
572 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
573 }
574
575 static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
576 {
577 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
578 int ret;
579 u32 val;
580
581 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
582
583 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
584 !(val & (STM32H7_ADSTART)),
585 100, STM32_ADC_TIMEOUT_US);
586 if (ret)
587 dev_warn(&indio_dev->dev, "stop failed\n");
588
589 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
590 }
591
592 static int stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
593 {
594 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
595 int ret;
596 u32 val;
597
598 /* Exit deep power down, then enable ADC voltage regulator */
599 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
600 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
601
602 if (adc->common->rate > STM32H7_BOOST_CLKRATE)
603 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
604
605 /* Wait for startup time */
606 if (!adc->cfg->has_vregready) {
607 usleep_range(10, 20);
608 return 0;
609 }
610
611 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
612 val & STM32MP1_VREGREADY, 100,
613 STM32_ADC_TIMEOUT_US);
614 if (ret) {
615 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
616 dev_err(&indio_dev->dev, "Failed to exit power down\n");
617 }
618
619 return ret;
620 }
621
622 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
623 {
624 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
625
626 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
627 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
628 }
629
630 static int stm32h7_adc_enable(struct stm32_adc *adc)
631 {
632 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
633 int ret;
634 u32 val;
635
636 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
637
638 /* Poll for ADRDY to be set (after adc startup time) */
639 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
640 val & STM32H7_ADRDY,
641 100, STM32_ADC_TIMEOUT_US);
642 if (ret) {
643 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
644 dev_err(&indio_dev->dev, "Failed to enable ADC\n");
645 } else {
646 /* Clear ADRDY by writing one */
647 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
648 }
649
650 return ret;
651 }
652
653 static void stm32h7_adc_disable(struct stm32_adc *adc)
654 {
655 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
656 int ret;
657 u32 val;
658
659 /* Disable ADC and wait until it's effectively disabled */
660 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
661 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
662 !(val & STM32H7_ADEN), 100,
663 STM32_ADC_TIMEOUT_US);
664 if (ret)
665 dev_warn(&indio_dev->dev, "Failed to disable\n");
666 }
667
668 /**
669 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
670 * @adc: stm32 adc instance
671 */
672 static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
673 {
674 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
675 int i, ret;
676 u32 lincalrdyw_mask, val;
677
678 /* Enable adc so LINCALRDYW1..6 bits are writable */
679 ret = stm32h7_adc_enable(adc);
680 if (ret)
681 return ret;
682
683 /* Read linearity calibration */
684 lincalrdyw_mask = STM32H7_LINCALRDYW6;
685 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
686 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
687 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
688
689 /* Poll: wait calib data to be ready in CALFACT2 register */
690 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
691 !(val & lincalrdyw_mask),
692 100, STM32_ADC_TIMEOUT_US);
693 if (ret) {
694 dev_err(&indio_dev->dev, "Failed to read calfact\n");
695 goto disable;
696 }
697
698 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
699 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
700 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
701
702 lincalrdyw_mask >>= 1;
703 }
704
705 /* Read offset calibration */
706 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
707 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
708 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
709 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
710 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
711
712 disable:
713 stm32h7_adc_disable(adc);
714
715 return ret;
716 }
717
718 /**
719 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
720 * @adc: stm32 adc instance
721 * Note: ADC must be enabled, with no on-going conversions.
722 */
723 static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
724 {
725 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
726 int i, ret;
727 u32 lincalrdyw_mask, val;
728
729 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
730 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
731 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
732
733 lincalrdyw_mask = STM32H7_LINCALRDYW6;
734 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
735 /*
736 * Write saved calibration data to shadow registers:
737 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
738 * data write. Then poll to wait for complete transfer.
739 */
740 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
741 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
742 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
743 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
744 val & lincalrdyw_mask,
745 100, STM32_ADC_TIMEOUT_US);
746 if (ret) {
747 dev_err(&indio_dev->dev, "Failed to write calfact\n");
748 return ret;
749 }
750
751 /*
752 * Read back calibration data, has two effects:
753 * - It ensures bits LINCALRDYW[6..1] are kept cleared
754 * for next time calibration needs to be restored.
755 * - BTW, bit clear triggers a read, then check data has been
756 * correctly written.
757 */
758 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
759 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
760 !(val & lincalrdyw_mask),
761 100, STM32_ADC_TIMEOUT_US);
762 if (ret) {
763 dev_err(&indio_dev->dev, "Failed to read calfact\n");
764 return ret;
765 }
766 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
767 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
768 dev_err(&indio_dev->dev, "calfact not consistent\n");
769 return -EIO;
770 }
771
772 lincalrdyw_mask >>= 1;
773 }
774
775 return 0;
776 }
777
778 /**
779 * Fixed timeout value for ADC calibration.
780 * worst cases:
781 * - low clock frequency
782 * - maximum prescalers
783 * Calibration requires:
784 * - 131,072 ADC clock cycle for the linear calibration
785 * - 20 ADC clock cycle for the offset calibration
786 *
787 * Set to 100ms for now
788 */
789 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000
790
791 /**
792 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
793 * @adc: stm32 adc instance
794 * Exit from power down, calibrate ADC, then return to power down.
795 */
796 static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
797 {
798 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
799 int ret;
800 u32 val;
801
802 ret = stm32h7_adc_exit_pwr_down(adc);
803 if (ret)
804 return ret;
805
806 /*
807 * Select calibration mode:
808 * - Offset calibration for single ended inputs
809 * - No linearity calibration (do it later, before reading it)
810 */
811 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
812 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
813
814 /* Start calibration, then wait for completion */
815 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
816 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
817 !(val & STM32H7_ADCAL), 100,
818 STM32H7_ADC_CALIB_TIMEOUT_US);
819 if (ret) {
820 dev_err(&indio_dev->dev, "calibration failed\n");
821 goto pwr_dwn;
822 }
823
824 /*
825 * Select calibration mode, then start calibration:
826 * - Offset calibration for differential input
827 * - Linearity calibration (needs to be done only once for single/diff)
828 * will run simultaneously with offset calibration.
829 */
830 stm32_adc_set_bits(adc, STM32H7_ADC_CR,
831 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
832 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
833 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
834 !(val & STM32H7_ADCAL), 100,
835 STM32H7_ADC_CALIB_TIMEOUT_US);
836 if (ret) {
837 dev_err(&indio_dev->dev, "calibration failed\n");
838 goto pwr_dwn;
839 }
840
841 stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
842 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
843
844 /* Read calibration result for future reference */
845 ret = stm32h7_adc_read_selfcalib(adc);
846
847 pwr_dwn:
848 stm32h7_adc_enter_pwr_down(adc);
849
850 return ret;
851 }
852
853 /**
854 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
855 * @adc: stm32 adc instance
856 * Leave power down mode.
857 * Configure channels as single ended or differential before enabling ADC.
858 * Enable ADC.
859 * Restore calibration data.
860 * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
861 * - Only one input is selected for single ended (e.g. 'vinp')
862 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
863 */
864 static int stm32h7_adc_prepare(struct stm32_adc *adc)
865 {
866 int ret;
867
868 ret = stm32h7_adc_exit_pwr_down(adc);
869 if (ret)
870 return ret;
871
872 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
873
874 ret = stm32h7_adc_enable(adc);
875 if (ret)
876 goto pwr_dwn;
877
878 ret = stm32h7_adc_restore_selfcalib(adc);
879 if (ret)
880 goto disable;
881
882 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
883
884 return 0;
885
886 disable:
887 stm32h7_adc_disable(adc);
888 pwr_dwn:
889 stm32h7_adc_enter_pwr_down(adc);
890
891 return ret;
892 }
893
894 static void stm32h7_adc_unprepare(struct stm32_adc *adc)
895 {
896 stm32h7_adc_disable(adc);
897 stm32h7_adc_enter_pwr_down(adc);
898 }
899
900 /**
901 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
902 * @indio_dev: IIO device
903 * @scan_mask: channels to be converted
904 *
905 * Conversion sequence :
906 * Apply sampling time settings for all channels.
907 * Configure ADC scan sequence based on selected channels in scan_mask.
908 * Add channels to SQR registers, from scan_mask LSB to MSB, then
909 * program sequence len.
910 */
911 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
912 const unsigned long *scan_mask)
913 {
914 struct stm32_adc *adc = iio_priv(indio_dev);
915 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
916 const struct iio_chan_spec *chan;
917 u32 val, bit;
918 int i = 0;
919
920 /* Apply sampling time settings */
921 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
922 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
923
924 for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
925 chan = indio_dev->channels + bit;
926 /*
927 * Assign one channel per SQ entry in regular
928 * sequence, starting with SQ1.
929 */
930 i++;
931 if (i > STM32_ADC_MAX_SQ)
932 return -EINVAL;
933
934 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
935 __func__, chan->channel, i);
936
937 val = stm32_adc_readl(adc, sqr[i].reg);
938 val &= ~sqr[i].mask;
939 val |= chan->channel << sqr[i].shift;
940 stm32_adc_writel(adc, sqr[i].reg, val);
941 }
942
943 if (!i)
944 return -EINVAL;
945
946 /* Sequence len */
947 val = stm32_adc_readl(adc, sqr[0].reg);
948 val &= ~sqr[0].mask;
949 val |= ((i - 1) << sqr[0].shift);
950 stm32_adc_writel(adc, sqr[0].reg, val);
951
952 return 0;
953 }
954
955 /**
956 * stm32_adc_get_trig_extsel() - Get external trigger selection
957 * @trig: trigger
958 *
959 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
960 */
961 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
962 struct iio_trigger *trig)
963 {
964 struct stm32_adc *adc = iio_priv(indio_dev);
965 int i;
966
967 /* lookup triggers registered by stm32 timer trigger driver */
968 for (i = 0; adc->cfg->trigs[i].name; i++) {
969 /**
970 * Checking both stm32 timer trigger type and trig name
971 * should be safe against arbitrary trigger names.
972 */
973 if ((is_stm32_timer_trigger(trig) ||
974 is_stm32_lptim_trigger(trig)) &&
975 !strcmp(adc->cfg->trigs[i].name, trig->name)) {
976 return adc->cfg->trigs[i].extsel;
977 }
978 }
979
980 return -EINVAL;
981 }
982
983 /**
984 * stm32_adc_set_trig() - Set a regular trigger
985 * @indio_dev: IIO device
986 * @trig: IIO trigger
987 *
988 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
989 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
990 * - if HW trigger enabled, set source & polarity
991 */
992 static int stm32_adc_set_trig(struct iio_dev *indio_dev,
993 struct iio_trigger *trig)
994 {
995 struct stm32_adc *adc = iio_priv(indio_dev);
996 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
997 unsigned long flags;
998 int ret;
999
1000 if (trig) {
1001 ret = stm32_adc_get_trig_extsel(indio_dev, trig);
1002 if (ret < 0)
1003 return ret;
1004
1005 /* set trigger source and polarity (default to rising edge) */
1006 extsel = ret;
1007 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1008 }
1009
1010 spin_lock_irqsave(&adc->lock, flags);
1011 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1012 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1013 val |= exten << adc->cfg->regs->exten.shift;
1014 val |= extsel << adc->cfg->regs->extsel.shift;
1015 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
1016 spin_unlock_irqrestore(&adc->lock, flags);
1017
1018 return 0;
1019 }
1020
1021 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
1022 const struct iio_chan_spec *chan,
1023 unsigned int type)
1024 {
1025 struct stm32_adc *adc = iio_priv(indio_dev);
1026
1027 adc->trigger_polarity = type;
1028
1029 return 0;
1030 }
1031
1032 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
1033 const struct iio_chan_spec *chan)
1034 {
1035 struct stm32_adc *adc = iio_priv(indio_dev);
1036
1037 return adc->trigger_polarity;
1038 }
1039
1040 static const char * const stm32_trig_pol_items[] = {
1041 "rising-edge", "falling-edge", "both-edges",
1042 };
1043
1044 static const struct iio_enum stm32_adc_trig_pol = {
1045 .items = stm32_trig_pol_items,
1046 .num_items = ARRAY_SIZE(stm32_trig_pol_items),
1047 .get = stm32_adc_get_trig_pol,
1048 .set = stm32_adc_set_trig_pol,
1049 };
1050
1051 /**
1052 * stm32_adc_single_conv() - Performs a single conversion
1053 * @indio_dev: IIO device
1054 * @chan: IIO channel
1055 * @res: conversion result
1056 *
1057 * The function performs a single conversion on a given channel:
1058 * - Apply sampling time settings
1059 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1060 * - Use SW trigger
1061 * - Start conversion, then wait for interrupt completion.
1062 */
1063 static int stm32_adc_single_conv(struct iio_dev *indio_dev,
1064 const struct iio_chan_spec *chan,
1065 int *res)
1066 {
1067 struct stm32_adc *adc = iio_priv(indio_dev);
1068 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1069 long timeout;
1070 u32 val;
1071 int ret;
1072
1073 reinit_completion(&adc->completion);
1074
1075 adc->bufi = 0;
1076
1077 if (adc->cfg->prepare) {
1078 ret = adc->cfg->prepare(adc);
1079 if (ret)
1080 return ret;
1081 }
1082
1083 /* Apply sampling time settings */
1084 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1085 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1086
1087 /* Program chan number in regular sequence (SQ1) */
1088 val = stm32_adc_readl(adc, regs->sqr[1].reg);
1089 val &= ~regs->sqr[1].mask;
1090 val |= chan->channel << regs->sqr[1].shift;
1091 stm32_adc_writel(adc, regs->sqr[1].reg, val);
1092
1093 /* Set regular sequence len (0 for 1 conversion) */
1094 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1095
1096 /* Trigger detection disabled (conversion can be launched in SW) */
1097 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1098
1099 stm32_adc_conv_irq_enable(adc);
1100
1101 adc->cfg->start_conv(adc, false);
1102
1103 timeout = wait_for_completion_interruptible_timeout(
1104 &adc->completion, STM32_ADC_TIMEOUT);
1105 if (timeout == 0) {
1106 ret = -ETIMEDOUT;
1107 } else if (timeout < 0) {
1108 ret = timeout;
1109 } else {
1110 *res = adc->buffer[0];
1111 ret = IIO_VAL_INT;
1112 }
1113
1114 adc->cfg->stop_conv(adc);
1115
1116 stm32_adc_conv_irq_disable(adc);
1117
1118 if (adc->cfg->unprepare)
1119 adc->cfg->unprepare(adc);
1120
1121 return ret;
1122 }
1123
1124 static int stm32_adc_read_raw(struct iio_dev *indio_dev,
1125 struct iio_chan_spec const *chan,
1126 int *val, int *val2, long mask)
1127 {
1128 struct stm32_adc *adc = iio_priv(indio_dev);
1129 int ret;
1130
1131 switch (mask) {
1132 case IIO_CHAN_INFO_RAW:
1133 ret = iio_device_claim_direct_mode(indio_dev);
1134 if (ret)
1135 return ret;
1136 if (chan->type == IIO_VOLTAGE)
1137 ret = stm32_adc_single_conv(indio_dev, chan, val);
1138 else
1139 ret = -EINVAL;
1140 iio_device_release_direct_mode(indio_dev);
1141 return ret;
1142
1143 case IIO_CHAN_INFO_SCALE:
1144 if (chan->differential) {
1145 *val = adc->common->vref_mv * 2;
1146 *val2 = chan->scan_type.realbits;
1147 } else {
1148 *val = adc->common->vref_mv;
1149 *val2 = chan->scan_type.realbits;
1150 }
1151 return IIO_VAL_FRACTIONAL_LOG2;
1152
1153 case IIO_CHAN_INFO_OFFSET:
1154 if (chan->differential)
1155 /* ADC_full_scale / 2 */
1156 *val = -((1 << chan->scan_type.realbits) / 2);
1157 else
1158 *val = 0;
1159 return IIO_VAL_INT;
1160
1161 default:
1162 return -EINVAL;
1163 }
1164 }
1165
1166 static irqreturn_t stm32_adc_isr(int irq, void *data)
1167 {
1168 struct stm32_adc *adc = data;
1169 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1170 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1171 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1172
1173 if (status & regs->isr_eoc.mask) {
1174 /* Reading DR also clears EOC status flag */
1175 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1176 if (iio_buffer_enabled(indio_dev)) {
1177 adc->bufi++;
1178 if (adc->bufi >= adc->num_conv) {
1179 stm32_adc_conv_irq_disable(adc);
1180 iio_trigger_poll(indio_dev->trig);
1181 }
1182 } else {
1183 complete(&adc->completion);
1184 }
1185 return IRQ_HANDLED;
1186 }
1187
1188 return IRQ_NONE;
1189 }
1190
1191 /**
1192 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1193 * @indio_dev: IIO device
1194 * @trig: new trigger
1195 *
1196 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1197 * driver, -EINVAL otherwise.
1198 */
1199 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
1200 struct iio_trigger *trig)
1201 {
1202 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1203 }
1204
1205 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1206 {
1207 struct stm32_adc *adc = iio_priv(indio_dev);
1208 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
1209 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
1210
1211 /*
1212 * dma cyclic transfers are used, buffer is split into two periods.
1213 * There should be :
1214 * - always one buffer (period) dma is working on
1215 * - one buffer (period) driver can push with iio_trigger_poll().
1216 */
1217 watermark = min(watermark, val * (unsigned)(sizeof(u16)));
1218 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1219
1220 return 0;
1221 }
1222
1223 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
1224 const unsigned long *scan_mask)
1225 {
1226 struct stm32_adc *adc = iio_priv(indio_dev);
1227 int ret;
1228
1229 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1230
1231 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1232 if (ret)
1233 return ret;
1234
1235 return 0;
1236 }
1237
1238 static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
1239 const struct of_phandle_args *iiospec)
1240 {
1241 int i;
1242
1243 for (i = 0; i < indio_dev->num_channels; i++)
1244 if (indio_dev->channels[i].channel == iiospec->args[0])
1245 return i;
1246
1247 return -EINVAL;
1248 }
1249
1250 /**
1251 * stm32_adc_debugfs_reg_access - read or write register value
1252 *
1253 * To read a value from an ADC register:
1254 * echo [ADC reg offset] > direct_reg_access
1255 * cat direct_reg_access
1256 *
1257 * To write a value in a ADC register:
1258 * echo [ADC_reg_offset] [value] > direct_reg_access
1259 */
1260 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
1261 unsigned reg, unsigned writeval,
1262 unsigned *readval)
1263 {
1264 struct stm32_adc *adc = iio_priv(indio_dev);
1265
1266 if (!readval)
1267 stm32_adc_writel(adc, reg, writeval);
1268 else
1269 *readval = stm32_adc_readl(adc, reg);
1270
1271 return 0;
1272 }
1273
1274 static const struct iio_info stm32_adc_iio_info = {
1275 .read_raw = stm32_adc_read_raw,
1276 .validate_trigger = stm32_adc_validate_trigger,
1277 .hwfifo_set_watermark = stm32_adc_set_watermark,
1278 .update_scan_mode = stm32_adc_update_scan_mode,
1279 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
1280 .of_xlate = stm32_adc_of_xlate,
1281 };
1282
1283 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1284 {
1285 struct dma_tx_state state;
1286 enum dma_status status;
1287
1288 status = dmaengine_tx_status(adc->dma_chan,
1289 adc->dma_chan->cookie,
1290 &state);
1291 if (status == DMA_IN_PROGRESS) {
1292 /* Residue is size in bytes from end of buffer */
1293 unsigned int i = adc->rx_buf_sz - state.residue;
1294 unsigned int size;
1295
1296 /* Return available bytes */
1297 if (i >= adc->bufi)
1298 size = i - adc->bufi;
1299 else
1300 size = adc->rx_buf_sz + i - adc->bufi;
1301
1302 return size;
1303 }
1304
1305 return 0;
1306 }
1307
1308 static void stm32_adc_dma_buffer_done(void *data)
1309 {
1310 struct iio_dev *indio_dev = data;
1311 struct stm32_adc *adc = iio_priv(indio_dev);
1312 int residue = stm32_adc_dma_residue(adc);
1313
1314 /*
1315 * In DMA mode the trigger services of IIO are not used
1316 * (e.g. no call to iio_trigger_poll).
1317 * Calling irq handler associated to the hardware trigger is not
1318 * relevant as the conversions have already been done. Data
1319 * transfers are performed directly in DMA callback instead.
1320 * This implementation avoids to call trigger irq handler that
1321 * may sleep, in an atomic context (DMA irq handler context).
1322 */
1323 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1324
1325 while (residue >= indio_dev->scan_bytes) {
1326 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1327
1328 iio_push_to_buffers(indio_dev, buffer);
1329
1330 residue -= indio_dev->scan_bytes;
1331 adc->bufi += indio_dev->scan_bytes;
1332 if (adc->bufi >= adc->rx_buf_sz)
1333 adc->bufi = 0;
1334 }
1335 }
1336
1337 static int stm32_adc_dma_start(struct iio_dev *indio_dev)
1338 {
1339 struct stm32_adc *adc = iio_priv(indio_dev);
1340 struct dma_async_tx_descriptor *desc;
1341 dma_cookie_t cookie;
1342 int ret;
1343
1344 if (!adc->dma_chan)
1345 return 0;
1346
1347 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
1348 adc->rx_buf_sz, adc->rx_buf_sz / 2);
1349
1350 /* Prepare a DMA cyclic transaction */
1351 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1352 adc->rx_dma_buf,
1353 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1354 DMA_DEV_TO_MEM,
1355 DMA_PREP_INTERRUPT);
1356 if (!desc)
1357 return -EBUSY;
1358
1359 desc->callback = stm32_adc_dma_buffer_done;
1360 desc->callback_param = indio_dev;
1361
1362 cookie = dmaengine_submit(desc);
1363 ret = dma_submit_error(cookie);
1364 if (ret) {
1365 dmaengine_terminate_sync(adc->dma_chan);
1366 return ret;
1367 }
1368
1369 /* Issue pending DMA requests */
1370 dma_async_issue_pending(adc->dma_chan);
1371
1372 return 0;
1373 }
1374
1375 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1376 {
1377 struct stm32_adc *adc = iio_priv(indio_dev);
1378 int ret;
1379
1380 if (adc->cfg->prepare) {
1381 ret = adc->cfg->prepare(adc);
1382 if (ret)
1383 return ret;
1384 }
1385
1386 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
1387 if (ret) {
1388 dev_err(&indio_dev->dev, "Can't set trigger\n");
1389 goto err_unprepare;
1390 }
1391
1392 ret = stm32_adc_dma_start(indio_dev);
1393 if (ret) {
1394 dev_err(&indio_dev->dev, "Can't start dma\n");
1395 goto err_clr_trig;
1396 }
1397
1398 ret = iio_triggered_buffer_postenable(indio_dev);
1399 if (ret < 0)
1400 goto err_stop_dma;
1401
1402 /* Reset adc buffer index */
1403 adc->bufi = 0;
1404
1405 if (!adc->dma_chan)
1406 stm32_adc_conv_irq_enable(adc);
1407
1408 adc->cfg->start_conv(adc, !!adc->dma_chan);
1409
1410 return 0;
1411
1412 err_stop_dma:
1413 if (adc->dma_chan)
1414 dmaengine_terminate_all(adc->dma_chan);
1415 err_clr_trig:
1416 stm32_adc_set_trig(indio_dev, NULL);
1417 err_unprepare:
1418 if (adc->cfg->unprepare)
1419 adc->cfg->unprepare(adc);
1420
1421 return ret;
1422 }
1423
1424 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1425 {
1426 struct stm32_adc *adc = iio_priv(indio_dev);
1427 int ret;
1428
1429 adc->cfg->stop_conv(adc);
1430 if (!adc->dma_chan)
1431 stm32_adc_conv_irq_disable(adc);
1432
1433 ret = iio_triggered_buffer_predisable(indio_dev);
1434 if (ret < 0)
1435 dev_err(&indio_dev->dev, "predisable failed\n");
1436
1437 if (adc->dma_chan)
1438 dmaengine_terminate_sync(adc->dma_chan);
1439
1440 if (stm32_adc_set_trig(indio_dev, NULL))
1441 dev_err(&indio_dev->dev, "Can't clear trigger\n");
1442
1443 if (adc->cfg->unprepare)
1444 adc->cfg->unprepare(adc);
1445
1446 return ret;
1447 }
1448
1449 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
1450 .postenable = &stm32_adc_buffer_postenable,
1451 .predisable = &stm32_adc_buffer_predisable,
1452 };
1453
1454 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
1455 {
1456 struct iio_poll_func *pf = p;
1457 struct iio_dev *indio_dev = pf->indio_dev;
1458 struct stm32_adc *adc = iio_priv(indio_dev);
1459
1460 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1461
1462 if (!adc->dma_chan) {
1463 /* reset buffer index */
1464 adc->bufi = 0;
1465 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1466 pf->timestamp);
1467 } else {
1468 int residue = stm32_adc_dma_residue(adc);
1469
1470 while (residue >= indio_dev->scan_bytes) {
1471 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1472
1473 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1474 pf->timestamp);
1475 residue -= indio_dev->scan_bytes;
1476 adc->bufi += indio_dev->scan_bytes;
1477 if (adc->bufi >= adc->rx_buf_sz)
1478 adc->bufi = 0;
1479 }
1480 }
1481
1482 iio_trigger_notify_done(indio_dev->trig);
1483
1484 /* re-enable eoc irq */
1485 if (!adc->dma_chan)
1486 stm32_adc_conv_irq_enable(adc);
1487
1488 return IRQ_HANDLED;
1489 }
1490
1491 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
1492 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
1493 {
1494 .name = "trigger_polarity_available",
1495 .shared = IIO_SHARED_BY_ALL,
1496 .read = iio_enum_available_read,
1497 .private = (uintptr_t)&stm32_adc_trig_pol,
1498 },
1499 {},
1500 };
1501
1502 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
1503 {
1504 struct device_node *node = indio_dev->dev.of_node;
1505 struct stm32_adc *adc = iio_priv(indio_dev);
1506 unsigned int i;
1507 u32 res;
1508
1509 if (of_property_read_u32(node, "assigned-resolution-bits", &res))
1510 res = adc->cfg->adc_info->resolutions[0];
1511
1512 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1513 if (res == adc->cfg->adc_info->resolutions[i])
1514 break;
1515 if (i >= adc->cfg->adc_info->num_res) {
1516 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1517 return -EINVAL;
1518 }
1519
1520 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
1521 adc->res = i;
1522
1523 return 0;
1524 }
1525
1526 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1527 {
1528 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1529 u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1530 unsigned int smp, r = smpr->reg;
1531
1532 /* Determine sampling time (ADC clock cycles) */
1533 period_ns = NSEC_PER_SEC / adc->common->rate;
1534 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
1535 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1536 break;
1537 if (smp > STM32_ADC_MAX_SMP)
1538 smp = STM32_ADC_MAX_SMP;
1539
1540 /* pre-build sampling time registers (e.g. smpr1, smpr2) */
1541 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1542 }
1543
1544 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
1545 struct iio_chan_spec *chan, u32 vinp,
1546 u32 vinn, int scan_index, bool differential)
1547 {
1548 struct stm32_adc *adc = iio_priv(indio_dev);
1549 char *name = adc->chan_name[vinp];
1550
1551 chan->type = IIO_VOLTAGE;
1552 chan->channel = vinp;
1553 if (differential) {
1554 chan->differential = 1;
1555 chan->channel2 = vinn;
1556 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn);
1557 } else {
1558 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp);
1559 }
1560 chan->datasheet_name = name;
1561 chan->scan_index = scan_index;
1562 chan->indexed = 1;
1563 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1564 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
1565 BIT(IIO_CHAN_INFO_OFFSET);
1566 chan->scan_type.sign = 'u';
1567 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1568 chan->scan_type.storagebits = 16;
1569 chan->ext_info = stm32_adc_ext_info;
1570
1571 /* pre-build selected channels mask */
1572 adc->pcsel |= BIT(chan->channel);
1573 if (differential) {
1574 /* pre-build diff channels mask */
1575 adc->difsel |= BIT(chan->channel);
1576 /* Also add negative input to pre-selected channels */
1577 adc->pcsel |= BIT(chan->channel2);
1578 }
1579 }
1580
1581 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
1582 {
1583 struct device_node *node = indio_dev->dev.of_node;
1584 struct stm32_adc *adc = iio_priv(indio_dev);
1585 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1586 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX];
1587 struct property *prop;
1588 const __be32 *cur;
1589 struct iio_chan_spec *channels;
1590 int scan_index = 0, num_channels = 0, num_diff = 0, ret, i;
1591 u32 val, smp = 0;
1592
1593 ret = of_property_count_u32_elems(node, "st,adc-channels");
1594 if (ret > adc_info->max_channels) {
1595 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1596 return -EINVAL;
1597 } else if (ret > 0) {
1598 num_channels += ret;
1599 }
1600
1601 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels",
1602 sizeof(*diff));
1603 if (ret > adc_info->max_channels) {
1604 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
1605 return -EINVAL;
1606 } else if (ret > 0) {
1607 int size = ret * sizeof(*diff) / sizeof(u32);
1608
1609 num_diff = ret;
1610 num_channels += ret;
1611 ret = of_property_read_u32_array(node, "st,adc-diff-channels",
1612 (u32 *)diff, size);
1613 if (ret)
1614 return ret;
1615 }
1616
1617 if (!num_channels) {
1618 dev_err(&indio_dev->dev, "No channels configured\n");
1619 return -ENODATA;
1620 }
1621
1622 /* Optional sample time is provided either for each, or all channels */
1623 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
1624 if (ret > 1 && ret != num_channels) {
1625 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1626 return -EINVAL;
1627 }
1628
1629 channels = devm_kcalloc(&indio_dev->dev, num_channels,
1630 sizeof(struct iio_chan_spec), GFP_KERNEL);
1631 if (!channels)
1632 return -ENOMEM;
1633
1634 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1635 if (val >= adc_info->max_channels) {
1636 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1637 return -EINVAL;
1638 }
1639
1640 /* Channel can't be configured both as single-ended & diff */
1641 for (i = 0; i < num_diff; i++) {
1642 if (val == diff[i].vinp) {
1643 dev_err(&indio_dev->dev,
1644 "channel %d miss-configured\n", val);
1645 return -EINVAL;
1646 }
1647 }
1648 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
1649 0, scan_index, false);
1650 scan_index++;
1651 }
1652
1653 for (i = 0; i < num_diff; i++) {
1654 if (diff[i].vinp >= adc_info->max_channels ||
1655 diff[i].vinn >= adc_info->max_channels) {
1656 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
1657 diff[i].vinp, diff[i].vinn);
1658 return -EINVAL;
1659 }
1660 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1661 diff[i].vinp, diff[i].vinn, scan_index,
1662 true);
1663 scan_index++;
1664 }
1665
1666 for (i = 0; i < scan_index; i++) {
1667 /*
1668 * Using of_property_read_u32_index(), smp value will only be
1669 * modified if valid u32 value can be decoded. This allows to
1670 * get either no value, 1 shared value for all indexes, or one
1671 * value per channel.
1672 */
1673 of_property_read_u32_index(node, "st,min-sample-time-nsecs",
1674 i, &smp);
1675 /* Prepare sampling time settings */
1676 stm32_adc_smpr_init(adc, channels[i].channel, smp);
1677 }
1678
1679 indio_dev->num_channels = scan_index;
1680 indio_dev->channels = channels;
1681
1682 return 0;
1683 }
1684
1685 static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev)
1686 {
1687 struct stm32_adc *adc = iio_priv(indio_dev);
1688 struct dma_slave_config config;
1689 int ret;
1690
1691 adc->dma_chan = dma_request_chan(dev, "rx");
1692 if (IS_ERR(adc->dma_chan)) {
1693 ret = PTR_ERR(adc->dma_chan);
1694 if (ret != -ENODEV) {
1695 if (ret != -EPROBE_DEFER)
1696 dev_err(dev,
1697 "DMA channel request failed with %d\n",
1698 ret);
1699 return ret;
1700 }
1701
1702 /* DMA is optional: fall back to IRQ mode */
1703 adc->dma_chan = NULL;
1704 return 0;
1705 }
1706
1707 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1708 STM32_DMA_BUFFER_SIZE,
1709 &adc->rx_dma_buf, GFP_KERNEL);
1710 if (!adc->rx_buf) {
1711 ret = -ENOMEM;
1712 goto err_release;
1713 }
1714
1715 /* Configure DMA channel to read data register */
1716 memset(&config, 0, sizeof(config));
1717 config.src_addr = (dma_addr_t)adc->common->phys_base;
1718 config.src_addr += adc->offset + adc->cfg->regs->dr;
1719 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1720
1721 ret = dmaengine_slave_config(adc->dma_chan, &config);
1722 if (ret)
1723 goto err_free;
1724
1725 return 0;
1726
1727 err_free:
1728 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1729 adc->rx_buf, adc->rx_dma_buf);
1730 err_release:
1731 dma_release_channel(adc->dma_chan);
1732
1733 return ret;
1734 }
1735
1736 static int stm32_adc_probe(struct platform_device *pdev)
1737 {
1738 struct iio_dev *indio_dev;
1739 struct device *dev = &pdev->dev;
1740 irqreturn_t (*handler)(int irq, void *p) = NULL;
1741 struct stm32_adc *adc;
1742 int ret;
1743
1744 if (!pdev->dev.of_node)
1745 return -ENODEV;
1746
1747 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1748 if (!indio_dev)
1749 return -ENOMEM;
1750
1751 adc = iio_priv(indio_dev);
1752 adc->common = dev_get_drvdata(pdev->dev.parent);
1753 spin_lock_init(&adc->lock);
1754 init_completion(&adc->completion);
1755 adc->cfg = (const struct stm32_adc_cfg *)
1756 of_match_device(dev->driver->of_match_table, dev)->data;
1757
1758 indio_dev->name = dev_name(&pdev->dev);
1759 indio_dev->dev.parent = &pdev->dev;
1760 indio_dev->dev.of_node = pdev->dev.of_node;
1761 indio_dev->info = &stm32_adc_iio_info;
1762 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
1763
1764 platform_set_drvdata(pdev, adc);
1765
1766 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1767 if (ret != 0) {
1768 dev_err(&pdev->dev, "missing reg property\n");
1769 return -EINVAL;
1770 }
1771
1772 adc->irq = platform_get_irq(pdev, 0);
1773 if (adc->irq < 0) {
1774 dev_err(&pdev->dev, "failed to get irq\n");
1775 return adc->irq;
1776 }
1777
1778 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1779 0, pdev->name, adc);
1780 if (ret) {
1781 dev_err(&pdev->dev, "failed to request IRQ\n");
1782 return ret;
1783 }
1784
1785 adc->clk = devm_clk_get(&pdev->dev, NULL);
1786 if (IS_ERR(adc->clk)) {
1787 ret = PTR_ERR(adc->clk);
1788 if (ret == -ENOENT && !adc->cfg->clk_required) {
1789 adc->clk = NULL;
1790 } else {
1791 dev_err(&pdev->dev, "Can't get clock\n");
1792 return ret;
1793 }
1794 }
1795
1796 if (adc->clk) {
1797 ret = clk_prepare_enable(adc->clk);
1798 if (ret < 0) {
1799 dev_err(&pdev->dev, "clk enable failed\n");
1800 return ret;
1801 }
1802 }
1803
1804 ret = stm32_adc_of_get_resolution(indio_dev);
1805 if (ret < 0)
1806 goto err_clk_disable;
1807 stm32_adc_set_res(adc);
1808
1809 if (adc->cfg->selfcalib) {
1810 ret = adc->cfg->selfcalib(adc);
1811 if (ret)
1812 goto err_clk_disable;
1813 }
1814
1815 ret = stm32_adc_chan_of_init(indio_dev);
1816 if (ret < 0)
1817 goto err_clk_disable;
1818
1819 ret = stm32_adc_dma_request(dev, indio_dev);
1820 if (ret < 0)
1821 goto err_clk_disable;
1822
1823 if (!adc->dma_chan)
1824 handler = &stm32_adc_trigger_handler;
1825
1826 ret = iio_triggered_buffer_setup(indio_dev,
1827 &iio_pollfunc_store_time, handler,
1828 &stm32_adc_buffer_setup_ops);
1829 if (ret) {
1830 dev_err(&pdev->dev, "buffer setup failed\n");
1831 goto err_dma_disable;
1832 }
1833
1834 ret = iio_device_register(indio_dev);
1835 if (ret) {
1836 dev_err(&pdev->dev, "iio dev register failed\n");
1837 goto err_buffer_cleanup;
1838 }
1839
1840 return 0;
1841
1842 err_buffer_cleanup:
1843 iio_triggered_buffer_cleanup(indio_dev);
1844
1845 err_dma_disable:
1846 if (adc->dma_chan) {
1847 dma_free_coherent(adc->dma_chan->device->dev,
1848 STM32_DMA_BUFFER_SIZE,
1849 adc->rx_buf, adc->rx_dma_buf);
1850 dma_release_channel(adc->dma_chan);
1851 }
1852 err_clk_disable:
1853 if (adc->clk)
1854 clk_disable_unprepare(adc->clk);
1855
1856 return ret;
1857 }
1858
1859 static int stm32_adc_remove(struct platform_device *pdev)
1860 {
1861 struct stm32_adc *adc = platform_get_drvdata(pdev);
1862 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1863
1864 iio_device_unregister(indio_dev);
1865 iio_triggered_buffer_cleanup(indio_dev);
1866 if (adc->dma_chan) {
1867 dma_free_coherent(adc->dma_chan->device->dev,
1868 STM32_DMA_BUFFER_SIZE,
1869 adc->rx_buf, adc->rx_dma_buf);
1870 dma_release_channel(adc->dma_chan);
1871 }
1872 if (adc->clk)
1873 clk_disable_unprepare(adc->clk);
1874
1875 return 0;
1876 }
1877
1878 static const struct stm32_adc_cfg stm32f4_adc_cfg = {
1879 .regs = &stm32f4_adc_regspec,
1880 .adc_info = &stm32f4_adc_info,
1881 .trigs = stm32f4_adc_trigs,
1882 .clk_required = true,
1883 .start_conv = stm32f4_adc_start_conv,
1884 .stop_conv = stm32f4_adc_stop_conv,
1885 .smp_cycles = stm32f4_adc_smp_cycles,
1886 };
1887
1888 static const struct stm32_adc_cfg stm32h7_adc_cfg = {
1889 .regs = &stm32h7_adc_regspec,
1890 .adc_info = &stm32h7_adc_info,
1891 .trigs = stm32h7_adc_trigs,
1892 .selfcalib = stm32h7_adc_selfcalib,
1893 .start_conv = stm32h7_adc_start_conv,
1894 .stop_conv = stm32h7_adc_stop_conv,
1895 .prepare = stm32h7_adc_prepare,
1896 .unprepare = stm32h7_adc_unprepare,
1897 .smp_cycles = stm32h7_adc_smp_cycles,
1898 };
1899
1900 static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
1901 .regs = &stm32h7_adc_regspec,
1902 .adc_info = &stm32h7_adc_info,
1903 .trigs = stm32h7_adc_trigs,
1904 .has_vregready = true,
1905 .selfcalib = stm32h7_adc_selfcalib,
1906 .start_conv = stm32h7_adc_start_conv,
1907 .stop_conv = stm32h7_adc_stop_conv,
1908 .prepare = stm32h7_adc_prepare,
1909 .unprepare = stm32h7_adc_unprepare,
1910 .smp_cycles = stm32h7_adc_smp_cycles,
1911 };
1912
1913 static const struct of_device_id stm32_adc_of_match[] = {
1914 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
1915 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
1916 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
1917 {},
1918 };
1919 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
1920
1921 static struct platform_driver stm32_adc_driver = {
1922 .probe = stm32_adc_probe,
1923 .remove = stm32_adc_remove,
1924 .driver = {
1925 .name = "stm32-adc",
1926 .of_match_table = stm32_adc_of_match,
1927 },
1928 };
1929 module_platform_driver(stm32_adc_driver);
1930
1931 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
1932 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
1933 MODULE_LICENSE("GPL v2");
1934 MODULE_ALIAS("platform:stm32-adc");
Linux with added FPC-III support