drivers/iio/adc/ti-ads8688.c

   1 /*
   2  * Copyright (C) 2015 Prevas A/S
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/sysfs.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18
  19 #include <linux/iio/iio.h>
  20 #include <linux/iio/buffer.h>
  21 #include <linux/iio/trigger_consumer.h>
  22 #include <linux/iio/triggered_buffer.h>
  23 #include <linux/iio/sysfs.h>
  24
  25 #define ADS8688_CMD_REG(x)              (x << 8)
  26 #define ADS8688_CMD_REG_NOOP            0x00
  27 #define ADS8688_CMD_REG_RST             0x85
  28 #define ADS8688_CMD_REG_MAN_CH(chan)    (0xC0 | (4 * chan))
  29 #define ADS8688_CMD_DONT_CARE_BITS      16
  30
  31 #define ADS8688_PROG_REG(x)             (x << 9)
  32 #define ADS8688_PROG_REG_RANGE_CH(chan) (0x05 + chan)
  33 #define ADS8688_PROG_WR_BIT             BIT(8)
  34 #define ADS8688_PROG_DONT_CARE_BITS     8
  35
  36 #define ADS8688_REG_PLUSMINUS25VREF     0
  37 #define ADS8688_REG_PLUSMINUS125VREF    1
  38 #define ADS8688_REG_PLUSMINUS0625VREF   2
  39 #define ADS8688_REG_PLUS25VREF          5
  40 #define ADS8688_REG_PLUS125VREF         6
  41
  42 #define ADS8688_VREF_MV                 4096
  43 #define ADS8688_REALBITS                16
  44 #define ADS8688_MAX_CHANNELS            8
  45
  46 /*
  47  * enum ads8688_range - ADS8688 reference voltage range
  48  * @ADS8688_PLUSMINUS25VREF: Device is configured for input range ±2.5 * VREF
  49  * @ADS8688_PLUSMINUS125VREF: Device is configured for input range ±1.25 * VREF
  50  * @ADS8688_PLUSMINUS0625VREF: Device is configured for input range ±0.625 * VREF
  51  * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF
  52  * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF
  53  */
  54 enum ads8688_range {
  55         ADS8688_PLUSMINUS25VREF,
  56         ADS8688_PLUSMINUS125VREF,
  57         ADS8688_PLUSMINUS0625VREF,
  58         ADS8688_PLUS25VREF,
  59         ADS8688_PLUS125VREF,
  60 };
  61
  62 struct ads8688_chip_info {
  63         const struct iio_chan_spec *channels;
  64         unsigned int num_channels;
  65 };
  66
  67 struct ads8688_state {
  68         struct mutex                    lock;
  69         const struct ads8688_chip_info  *chip_info;
  70         struct spi_device               *spi;
  71         struct regulator                *reg;
  72         unsigned int                    vref_mv;
  73         enum ads8688_range              range[8];
  74         union {
  75                 __be32 d32;
  76                 u8 d8[4];
  77         } data[2] ____cacheline_aligned;
  78 };
  79
  80 enum ads8688_id {
  81         ID_ADS8684,
  82         ID_ADS8688,
  83 };
  84
  85 struct ads8688_ranges {
  86         enum ads8688_range range;
  87         unsigned int scale;
  88         int offset;
  89         u8 reg;
  90 };
  91
  92 static const struct ads8688_ranges ads8688_range_def[5] = {
  93         {
  94                 .range = ADS8688_PLUSMINUS25VREF,
  95                 .scale = 76295,
  96                 .offset = -(1 << (ADS8688_REALBITS - 1)),
  97                 .reg = ADS8688_REG_PLUSMINUS25VREF,
  98         }, {
  99                 .range = ADS8688_PLUSMINUS125VREF,
 100                 .scale = 38148,
 101                 .offset = -(1 << (ADS8688_REALBITS - 1)),
 102                 .reg = ADS8688_REG_PLUSMINUS125VREF,
 103         }, {
 104                 .range = ADS8688_PLUSMINUS0625VREF,
 105                 .scale = 19074,
 106                 .offset = -(1 << (ADS8688_REALBITS - 1)),
 107                 .reg = ADS8688_REG_PLUSMINUS0625VREF,
 108         }, {
 109                 .range = ADS8688_PLUS25VREF,
 110                 .scale = 38148,
 111                 .offset = 0,
 112                 .reg = ADS8688_REG_PLUS25VREF,
 113         }, {
 114                 .range = ADS8688_PLUS125VREF,
 115                 .scale = 19074,
 116                 .offset = 0,
 117                 .reg = ADS8688_REG_PLUS125VREF,
 118         }
 119 };
 120
 121 static ssize_t ads8688_show_scales(struct device *dev,
 122                                    struct device_attribute *attr, char *buf)
 123 {
 124         struct ads8688_state *st = iio_priv(dev_to_iio_dev(dev));
 125
 126         return sprintf(buf, "0.%09u 0.%09u 0.%09u\n",
 127                        ads8688_range_def[0].scale * st->vref_mv,
 128                        ads8688_range_def[1].scale * st->vref_mv,
 129                        ads8688_range_def[2].scale * st->vref_mv);
 130 }
 131
 132 static ssize_t ads8688_show_offsets(struct device *dev,
 133                                     struct device_attribute *attr, char *buf)
 134 {
 135         return sprintf(buf, "%d %d\n", ads8688_range_def[0].offset,
 136                        ads8688_range_def[3].offset);
 137 }
 138
 139 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
 140                        ads8688_show_scales, NULL, 0);
 141 static IIO_DEVICE_ATTR(in_voltage_offset_available, S_IRUGO,
 142                        ads8688_show_offsets, NULL, 0);
 143
 144 static struct attribute *ads8688_attributes[] = {
 145         &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
 146         &iio_dev_attr_in_voltage_offset_available.dev_attr.attr,
 147         NULL,
 148 };
 149
 150 static const struct attribute_group ads8688_attribute_group = {
 151         .attrs = ads8688_attributes,
 152 };
 153
 154 #define ADS8688_CHAN(index)                                     \
 155 {                                                               \
 156         .type = IIO_VOLTAGE,                                    \
 157         .indexed = 1,                                           \
 158         .channel = index,                                       \
 159         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)            \
 160                               | BIT(IIO_CHAN_INFO_SCALE)        \
 161                               | BIT(IIO_CHAN_INFO_OFFSET),      \
 162         .scan_index = index,                                    \
 163         .scan_type = {                                          \
 164                 .sign = 'u',                                    \
 165                 .realbits = 16,                                 \
 166                 .storagebits = 16,                              \
 167                 .endianness = IIO_BE,                           \
 168         },                                                      \
 169 }
 170
 171 static const struct iio_chan_spec ads8684_channels[] = {
 172         ADS8688_CHAN(0),
 173         ADS8688_CHAN(1),
 174         ADS8688_CHAN(2),
 175         ADS8688_CHAN(3),
 176 };
 177
 178 static const struct iio_chan_spec ads8688_channels[] = {
 179         ADS8688_CHAN(0),
 180         ADS8688_CHAN(1),
 181         ADS8688_CHAN(2),
 182         ADS8688_CHAN(3),
 183         ADS8688_CHAN(4),
 184         ADS8688_CHAN(5),
 185         ADS8688_CHAN(6),
 186         ADS8688_CHAN(7),
 187 };
 188
 189 static int ads8688_prog_write(struct iio_dev *indio_dev, unsigned int addr,
 190                               unsigned int val)
 191 {
 192         struct ads8688_state *st = iio_priv(indio_dev);
 193         u32 tmp;
 194
 195         tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val;
 196         tmp <<= ADS8688_PROG_DONT_CARE_BITS;
 197         st->data[0].d32 = cpu_to_be32(tmp);
 198
 199         return spi_write(st->spi, &st->data[0].d8[1], 3);
 200 }
 201
 202 static int ads8688_reset(struct iio_dev *indio_dev)
 203 {
 204         struct ads8688_state *st = iio_priv(indio_dev);
 205         u32 tmp;
 206
 207         tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_RST);
 208         tmp <<= ADS8688_CMD_DONT_CARE_BITS;
 209         st->data[0].d32 = cpu_to_be32(tmp);
 210
 211         return spi_write(st->spi, &st->data[0].d8[0], 4);
 212 }
 213
 214 static int ads8688_read(struct iio_dev *indio_dev, unsigned int chan)
 215 {
 216         struct ads8688_state *st = iio_priv(indio_dev);
 217         int ret;
 218         u32 tmp;
 219         struct spi_transfer t[] = {
 220                 {
 221                         .tx_buf = &st->data[0].d8[0],
 222                         .len = 4,
 223                         .cs_change = 1,
 224                 }, {
 225                         .tx_buf = &st->data[1].d8[0],
 226                         .rx_buf = &st->data[1].d8[0],
 227                         .len = 4,
 228                 },
 229         };
 230
 231         tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_MAN_CH(chan));
 232         tmp <<= ADS8688_CMD_DONT_CARE_BITS;
 233         st->data[0].d32 = cpu_to_be32(tmp);
 234
 235         tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_NOOP);
 236         tmp <<= ADS8688_CMD_DONT_CARE_BITS;
 237         st->data[1].d32 = cpu_to_be32(tmp);
 238
 239         ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
 240         if (ret < 0)
 241                 return ret;
 242
 243         return be32_to_cpu(st->data[1].d32) & 0xffff;
 244 }
 245
 246 static int ads8688_read_raw(struct iio_dev *indio_dev,
 247                             struct iio_chan_spec const *chan,
 248                             int *val, int *val2, long m)
 249 {
 250         int ret, offset;
 251         unsigned long scale_mv;
 252
 253         struct ads8688_state *st = iio_priv(indio_dev);
 254
 255         mutex_lock(&st->lock);
 256         switch (m) {
 257         case IIO_CHAN_INFO_RAW:
 258                 ret = ads8688_read(indio_dev, chan->channel);
 259                 mutex_unlock(&st->lock);
 260                 if (ret < 0)
 261                         return ret;
 262                 *val = ret;
 263                 return IIO_VAL_INT;
 264         case IIO_CHAN_INFO_SCALE:
 265                 scale_mv = st->vref_mv;
 266                 scale_mv *= ads8688_range_def[st->range[chan->channel]].scale;
 267                 *val = 0;
 268                 *val2 = scale_mv;
 269                 mutex_unlock(&st->lock);
 270                 return IIO_VAL_INT_PLUS_NANO;
 271         case IIO_CHAN_INFO_OFFSET:
 272                 offset = ads8688_range_def[st->range[chan->channel]].offset;
 273                 *val = offset;
 274                 mutex_unlock(&st->lock);
 275                 return IIO_VAL_INT;
 276         }
 277         mutex_unlock(&st->lock);
 278
 279         return -EINVAL;
 280 }
 281
 282 static int ads8688_write_reg_range(struct iio_dev *indio_dev,
 283                                    struct iio_chan_spec const *chan,
 284                                    enum ads8688_range range)
 285 {
 286         unsigned int tmp;
 287         int ret;
 288
 289         tmp = ADS8688_PROG_REG_RANGE_CH(chan->channel);
 290         ret = ads8688_prog_write(indio_dev, tmp, range);
 291
 292         return ret;
 293 }
 294
 295 static int ads8688_write_raw(struct iio_dev *indio_dev,
 296                              struct iio_chan_spec const *chan,
 297                              int val, int val2, long mask)
 298 {
 299         struct ads8688_state *st = iio_priv(indio_dev);
 300         unsigned int scale = 0;
 301         int ret = -EINVAL, i, offset = 0;
 302
 303         mutex_lock(&st->lock);
 304         switch (mask) {
 305         case IIO_CHAN_INFO_SCALE:
 306                 /* If the offset is 0 the ±2.5 * VREF mode is not available */
 307                 offset = ads8688_range_def[st->range[chan->channel]].offset;
 308                 if (offset == 0 && val2 == ads8688_range_def[0].scale * st->vref_mv) {
 309                         mutex_unlock(&st->lock);
 310                         return -EINVAL;
 311                 }
 312
 313                 /* Lookup new mode */
 314                 for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
 315                         if (val2 == ads8688_range_def[i].scale * st->vref_mv &&
 316                             offset == ads8688_range_def[i].offset) {
 317                                 ret = ads8688_write_reg_range(indio_dev, chan,
 318                                         ads8688_range_def[i].reg);
 319                                 break;
 320                         }
 321                 break;
 322         case IIO_CHAN_INFO_OFFSET:
 323                 /*
 324                  * There are only two available offsets:
 325                  * 0 and -(1 << (ADS8688_REALBITS - 1))
 326                  */
 327                 if (!(ads8688_range_def[0].offset == val ||
 328                     ads8688_range_def[3].offset == val)) {
 329                         mutex_unlock(&st->lock);
 330                         return -EINVAL;
 331                 }
 332
 333                 /*
 334                  * If the device are in ±2.5 * VREF mode, it's not allowed to
 335                  * switch to a mode where the offset is 0
 336                  */
 337                 if (val == 0 &&
 338                     st->range[chan->channel] == ADS8688_PLUSMINUS25VREF) {
 339                         mutex_unlock(&st->lock);
 340                         return -EINVAL;
 341                 }
 342
 343                 scale = ads8688_range_def[st->range[chan->channel]].scale;
 344
 345                 /* Lookup new mode */
 346                 for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
 347                         if (val == ads8688_range_def[i].offset &&
 348                             scale == ads8688_range_def[i].scale) {
 349                                 ret = ads8688_write_reg_range(indio_dev, chan,
 350                                         ads8688_range_def[i].reg);
 351                                 break;
 352                         }
 353                 break;
 354         }
 355
 356         if (!ret)
 357                 st->range[chan->channel] = ads8688_range_def[i].range;
 358
 359         mutex_unlock(&st->lock);
 360
 361         return ret;
 362 }
 363
 364 static int ads8688_write_raw_get_fmt(struct iio_dev *indio_dev,
 365                                      struct iio_chan_spec const *chan,
 366                                      long mask)
 367 {
 368         switch (mask) {
 369         case IIO_CHAN_INFO_SCALE:
 370                 return IIO_VAL_INT_PLUS_NANO;
 371         case IIO_CHAN_INFO_OFFSET:
 372                 return IIO_VAL_INT;
 373         }
 374
 375         return -EINVAL;
 376 }
 377
 378 static const struct iio_info ads8688_info = {
 379         .read_raw = &ads8688_read_raw,
 380         .write_raw = &ads8688_write_raw,
 381         .write_raw_get_fmt = &ads8688_write_raw_get_fmt,
 382         .attrs = &ads8688_attribute_group,
 383 };
 384
 385 static irqreturn_t ads8688_trigger_handler(int irq, void *p)
 386 {
 387         struct iio_poll_func *pf = p;
 388         struct iio_dev *indio_dev = pf->indio_dev;
 389         u16 buffer[ADS8688_MAX_CHANNELS + sizeof(s64)/sizeof(u16)];
 390         int i, j = 0;
 391
 392         for (i = 0; i < indio_dev->masklength; i++) {
 393                 if (!test_bit(i, indio_dev->active_scan_mask))
 394                         continue;
 395                 buffer[j] = ads8688_read(indio_dev, i);
 396                 j++;
 397         }
 398
 399         iio_push_to_buffers_with_timestamp(indio_dev, buffer,
 400                         iio_get_time_ns(indio_dev));
 401
 402         iio_trigger_notify_done(indio_dev->trig);
 403
 404         return IRQ_HANDLED;
 405 }
 406
 407 static const struct ads8688_chip_info ads8688_chip_info_tbl[] = {
 408         [ID_ADS8684] = {
 409                 .channels = ads8684_channels,
 410                 .num_channels = ARRAY_SIZE(ads8684_channels),
 411         },
 412         [ID_ADS8688] = {
 413                 .channels = ads8688_channels,
 414                 .num_channels = ARRAY_SIZE(ads8688_channels),
 415         },
 416 };
 417
 418 static int ads8688_probe(struct spi_device *spi)
 419 {
 420         struct ads8688_state *st;
 421         struct iio_dev *indio_dev;
 422         int ret;
 423
 424         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 425         if (indio_dev == NULL)
 426                 return -ENOMEM;
 427
 428         st = iio_priv(indio_dev);
 429
 430         st->reg = devm_regulator_get_optional(&spi->dev, "vref");
 431         if (!IS_ERR(st->reg)) {
 432                 ret = regulator_enable(st->reg);
 433                 if (ret)
 434                         return ret;
 435
 436                 ret = regulator_get_voltage(st->reg);
 437                 if (ret < 0)
 438                         goto err_regulator_disable;
 439
 440                 st->vref_mv = ret / 1000;
 441         } else {
 442                 /* Use internal reference */
 443                 st->vref_mv = ADS8688_VREF_MV;
 444         }
 445
 446         st->chip_info = &ads8688_chip_info_tbl[spi_get_device_id(spi)->driver_data];
 447
 448         spi->mode = SPI_MODE_1;
 449
 450         spi_set_drvdata(spi, indio_dev);
 451
 452         st->spi = spi;
 453
 454         indio_dev->name = spi_get_device_id(spi)->name;
 455         indio_dev->dev.parent = &spi->dev;
 456         indio_dev->dev.of_node = spi->dev.of_node;
 457         indio_dev->modes = INDIO_DIRECT_MODE;
 458         indio_dev->channels = st->chip_info->channels;
 459         indio_dev->num_channels = st->chip_info->num_channels;
 460         indio_dev->info = &ads8688_info;
 461
 462         ads8688_reset(indio_dev);
 463
 464         mutex_init(&st->lock);
 465
 466         ret = iio_triggered_buffer_setup(indio_dev, NULL, ads8688_trigger_handler, NULL);
 467         if (ret < 0) {
 468                 dev_err(&spi->dev, "iio triggered buffer setup failed\n");
 469                 goto err_regulator_disable;
 470         }
 471
 472         ret = iio_device_register(indio_dev);
 473         if (ret)
 474                 goto err_buffer_cleanup;
 475
 476         return 0;
 477
 478 err_buffer_cleanup:
 479         iio_triggered_buffer_cleanup(indio_dev);
 480
 481 err_regulator_disable:
 482         if (!IS_ERR(st->reg))
 483                 regulator_disable(st->reg);
 484
 485         return ret;
 486 }
 487
 488 static int ads8688_remove(struct spi_device *spi)
 489 {
 490         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 491         struct ads8688_state *st = iio_priv(indio_dev);
 492
 493         iio_device_unregister(indio_dev);
 494         iio_triggered_buffer_cleanup(indio_dev);
 495
 496         if (!IS_ERR(st->reg))
 497                 regulator_disable(st->reg);
 498
 499         return 0;
 500 }
 501
 502 static const struct spi_device_id ads8688_id[] = {
 503         {"ads8684", ID_ADS8684},
 504         {"ads8688", ID_ADS8688},
 505         {}
 506 };
 507 MODULE_DEVICE_TABLE(spi, ads8688_id);
 508
 509 static const struct of_device_id ads8688_of_match[] = {
 510         { .compatible = "ti,ads8684" },
 511         { .compatible = "ti,ads8688" },
 512         { }
 513 };
 514 MODULE_DEVICE_TABLE(of, ads8688_of_match);
 515
 516 static struct spi_driver ads8688_driver = {
 517         .driver = {
 518                 .name   = "ads8688",
 519         },
 520         .probe          = ads8688_probe,
 521         .remove         = ads8688_remove,
 522         .id_table       = ads8688_id,
 523 };
 524 module_spi_driver(ads8688_driver);
 525
 526 MODULE_AUTHOR("Sean Nyekjaer <sean.nyekjaer@prevas.dk>");
 527 MODULE_DESCRIPTION("Texas Instruments ADS8688 driver");
 528 MODULE_LICENSE("GPL v2");