drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h

   1 /*
   2 * Copyright (C) 2012 Invensense, Inc.
   3 *
   4 * This software is licensed under the terms of the GNU General Public
   5 * License version 2, as published by the Free Software Foundation, and
   6 * may be copied, distributed, and modified under those terms.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13 #include <linux/i2c.h>
  14 #include <linux/i2c-mux.h>
  15 #include <linux/mutex.h>
  16 #include <linux/iio/iio.h>
  17 #include <linux/iio/buffer.h>
  18 #include <linux/regmap.h>
  19 #include <linux/iio/sysfs.h>
  20 #include <linux/iio/kfifo_buf.h>
  21 #include <linux/iio/trigger.h>
  22 #include <linux/iio/triggered_buffer.h>
  23 #include <linux/iio/trigger_consumer.h>
  24 #include <linux/platform_data/invensense_mpu6050.h>
  25
  26 /**
  27  *  struct inv_mpu6050_reg_map - Notable registers.
  28  *  @sample_rate_div:   Divider applied to gyro output rate.
  29  *  @lpf:               Configures internal low pass filter.
  30  *  @accel_lpf:         Configures accelerometer low pass filter.
  31  *  @user_ctrl:         Enables/resets the FIFO.
  32  *  @fifo_en:           Determines which data will appear in FIFO.
  33  *  @gyro_config:       gyro config register.
  34  *  @accl_config:       accel config register
  35  *  @fifo_count_h:      Upper byte of FIFO count.
  36  *  @fifo_r_w:          FIFO register.
  37  *  @raw_gyro:          Address of first gyro register.
  38  *  @raw_accl:          Address of first accel register.
  39  *  @temperature:       temperature register
  40  *  @int_enable:        Interrupt enable register.
  41  *  @int_status:        Interrupt status register.
  42  *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  43  *  @pwr_mgmt_2:        Controls power state of individual sensors.
  44  *  @int_pin_cfg;       Controls interrupt pin configuration.
  45  *  @accl_offset:       Controls the accelerometer calibration offset.
  46  *  @gyro_offset:       Controls the gyroscope calibration offset.
  47  *  @i2c_if:            Controls the i2c interface
  48  */
  49 struct inv_mpu6050_reg_map {
  50         u8 sample_rate_div;
  51         u8 lpf;
  52         u8 accel_lpf;
  53         u8 user_ctrl;
  54         u8 fifo_en;
  55         u8 gyro_config;
  56         u8 accl_config;
  57         u8 fifo_count_h;
  58         u8 fifo_r_w;
  59         u8 raw_gyro;
  60         u8 raw_accl;
  61         u8 temperature;
  62         u8 int_enable;
  63         u8 int_status;
  64         u8 pwr_mgmt_1;
  65         u8 pwr_mgmt_2;
  66         u8 int_pin_cfg;
  67         u8 accl_offset;
  68         u8 gyro_offset;
  69         u8 i2c_if;
  70 };
  71
  72 /*device enum */
  73 enum inv_devices {
  74         INV_MPU6050,
  75         INV_MPU6500,
  76         INV_MPU6515,
  77         INV_MPU6000,
  78         INV_MPU9150,
  79         INV_MPU9250,
  80         INV_MPU9255,
  81         INV_ICM20608,
  82         INV_ICM20602,
  83         INV_NUM_PARTS
  84 };
  85
  86 /**
  87  *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  88  *  @fsr:               Full scale range.
  89  *  @lpf:               Digital low pass filter frequency.
  90  *  @accl_fs:           accel full scale range.
  91  *  @accl_fifo_enable:  enable accel data output
  92  *  @gyro_fifo_enable:  enable gyro data output
  93  *  @divider:           chip sample rate divider (sample rate divider - 1)
  94  */
  95 struct inv_mpu6050_chip_config {
  96         unsigned int fsr:2;
  97         unsigned int lpf:3;
  98         unsigned int accl_fs:2;
  99         unsigned int accl_fifo_enable:1;
 100         unsigned int gyro_fifo_enable:1;
 101         u8 divider;
 102         u8 user_ctrl;
 103 };
 104
 105 /**
 106  *  struct inv_mpu6050_hw - Other important hardware information.
 107  *  @whoami:    Self identification byte from WHO_AM_I register
 108  *  @name:      name of the chip.
 109  *  @reg:   register map of the chip.
 110  *  @config:    configuration of the chip.
 111  *  @fifo_size: size of the FIFO in bytes.
 112  *  @temp:      offset and scale to apply to raw temperature.
 113  */
 114 struct inv_mpu6050_hw {
 115         u8 whoami;
 116         u8 *name;
 117         const struct inv_mpu6050_reg_map *reg;
 118         const struct inv_mpu6050_chip_config *config;
 119         size_t fifo_size;
 120         struct {
 121                 int offset;
 122                 int scale;
 123         } temp;
 124 };
 125
 126 /*
 127  *  struct inv_mpu6050_state - Driver state variables.
 128  *  @lock:              Chip access lock.
 129  *  @trig:              IIO trigger.
 130  *  @chip_config:       Cached attribute information.
 131  *  @reg:               Map of important registers.
 132  *  @hw:                Other hardware-specific information.
 133  *  @chip_type:         chip type.
 134  *  @plat_data:         platform data (deprecated in favor of @orientation).
 135  *  @orientation:       sensor chip orientation relative to main hardware.
 136  *  @map                regmap pointer.
 137  *  @irq                interrupt number.
 138  *  @irq_mask           the int_pin_cfg mask to configure interrupt type.
 139  *  @chip_period:       chip internal period estimation (~1kHz).
 140  *  @it_timestamp:      timestamp from previous interrupt.
 141  *  @data_timestamp:    timestamp for next data sample.
 142  */
 143 struct inv_mpu6050_state {
 144         struct mutex lock;
 145         struct iio_trigger  *trig;
 146         struct inv_mpu6050_chip_config chip_config;
 147         const struct inv_mpu6050_reg_map *reg;
 148         const struct inv_mpu6050_hw *hw;
 149         enum   inv_devices chip_type;
 150         struct i2c_mux_core *muxc;
 151         struct i2c_client *mux_client;
 152         unsigned int powerup_count;
 153         struct inv_mpu6050_platform_data plat_data;
 154         struct iio_mount_matrix orientation;
 155         struct regmap *map;
 156         int irq;
 157         u8 irq_mask;
 158         unsigned skip_samples;
 159         s64 chip_period;
 160         s64 it_timestamp;
 161         s64 data_timestamp;
 162 };
 163
 164 /*register and associated bit definition*/
 165 #define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 166 #define INV_MPU6050_REG_GYRO_OFFSET         0x13
 167
 168 #define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 169 #define INV_MPU6050_REG_CONFIG              0x1A
 170 #define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 171 #define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 172
 173 #define INV_MPU6050_REG_FIFO_EN             0x23
 174 #define INV_MPU6050_BIT_ACCEL_OUT           0x08
 175 #define INV_MPU6050_BITS_GYRO_OUT           0x70
 176
 177 #define INV_MPU6050_REG_INT_ENABLE          0x38
 178 #define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 179 #define INV_MPU6050_BIT_DMP_INT_EN          0x02
 180
 181 #define INV_MPU6050_REG_RAW_ACCEL           0x3B
 182 #define INV_MPU6050_REG_TEMPERATURE         0x41
 183 #define INV_MPU6050_REG_RAW_GYRO            0x43
 184
 185 #define INV_MPU6050_REG_INT_STATUS          0x3A
 186 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
 187 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
 188
 189 #define INV_MPU6050_REG_USER_CTRL           0x6A
 190 #define INV_MPU6050_BIT_FIFO_RST            0x04
 191 #define INV_MPU6050_BIT_DMP_RST             0x08
 192 #define INV_MPU6050_BIT_I2C_MST_EN          0x20
 193 #define INV_MPU6050_BIT_FIFO_EN             0x40
 194 #define INV_MPU6050_BIT_DMP_EN              0x80
 195 #define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 196
 197 #define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 198 #define INV_MPU6050_BIT_H_RESET             0x80
 199 #define INV_MPU6050_BIT_SLEEP               0x40
 200 #define INV_MPU6050_BIT_CLK_MASK            0x7
 201
 202 #define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 203 #define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 204 #define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 205
 206 /* ICM20602 register */
 207 #define INV_ICM20602_REG_I2C_IF             0x70
 208 #define INV_ICM20602_BIT_I2C_IF_DIS         0x40
 209
 210 #define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 211 #define INV_MPU6050_REG_FIFO_R_W            0x74
 212
 213 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 214 #define INV_MPU6050_FIFO_COUNT_BYTE          2
 215
 216 /* ICM20602 FIFO samples include temperature readings */
 217 #define INV_ICM20602_BYTES_PER_TEMP_SENSOR   2
 218
 219 /* mpu6500 registers */
 220 #define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 221 #define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 222
 223 /* delay time in milliseconds */
 224 #define INV_MPU6050_POWER_UP_TIME            100
 225 #define INV_MPU6050_TEMP_UP_TIME             100
 226 #define INV_MPU6050_SENSOR_UP_TIME           30
 227
 228 /* delay time in microseconds */
 229 #define INV_MPU6050_REG_UP_TIME_MIN          5000
 230 #define INV_MPU6050_REG_UP_TIME_MAX          10000
 231
 232 #define INV_MPU6050_TEMP_OFFSET              12420
 233 #define INV_MPU6050_TEMP_SCALE               2941176
 234 #define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 235 #define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 236 #define INV_MPU6050_THREE_AXIS               3
 237 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 238 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 239
 240 #define INV_MPU6500_TEMP_OFFSET              7011
 241 #define INV_MPU6500_TEMP_SCALE               2995178
 242
 243 #define INV_ICM20608_TEMP_OFFSET             8170
 244 #define INV_ICM20608_TEMP_SCALE              3059976
 245
 246 /* 6 + 6 round up and plus 8 */
 247 #define INV_MPU6050_OUTPUT_DATA_SIZE         24
 248
 249 #define INV_MPU6050_REG_INT_PIN_CFG     0x37
 250 #define INV_MPU6050_ACTIVE_HIGH         0x00
 251 #define INV_MPU6050_ACTIVE_LOW          0x80
 252 /* enable level triggering */
 253 #define INV_MPU6050_LATCH_INT_EN        0x20
 254 #define INV_MPU6050_BIT_BYPASS_EN       0x2
 255
 256 /* Allowed timestamp period jitter in percent */
 257 #define INV_MPU6050_TS_PERIOD_JITTER    4
 258
 259 /* init parameters */
 260 #define INV_MPU6050_INIT_FIFO_RATE           50
 261 #define INV_MPU6050_MAX_FIFO_RATE            1000
 262 #define INV_MPU6050_MIN_FIFO_RATE            4
 263
 264 /* chip internal frequency: 1KHz */
 265 #define INV_MPU6050_INTERNAL_FREQ_HZ            1000
 266 /* return the frequency divider (chip sample rate divider + 1) */
 267 #define INV_MPU6050_FREQ_DIVIDER(st)                                    \
 268         ((st)->chip_config.divider + 1)
 269 /* chip sample rate divider to fifo rate */
 270 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)                     \
 271         ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
 272 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)                       \
 273         (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
 274
 275 #define INV_MPU6050_REG_WHOAMI                  117
 276
 277 #define INV_MPU6000_WHOAMI_VALUE                0x68
 278 #define INV_MPU6050_WHOAMI_VALUE                0x68
 279 #define INV_MPU6500_WHOAMI_VALUE                0x70
 280 #define INV_MPU9150_WHOAMI_VALUE                0x68
 281 #define INV_MPU9250_WHOAMI_VALUE                0x71
 282 #define INV_MPU9255_WHOAMI_VALUE                0x73
 283 #define INV_MPU6515_WHOAMI_VALUE                0x74
 284 #define INV_ICM20608_WHOAMI_VALUE               0xAF
 285 #define INV_ICM20602_WHOAMI_VALUE               0x12
 286
 287 /* scan element definition for generic MPU6xxx devices */
 288 enum inv_mpu6050_scan {
 289         INV_MPU6050_SCAN_ACCL_X,
 290         INV_MPU6050_SCAN_ACCL_Y,
 291         INV_MPU6050_SCAN_ACCL_Z,
 292         INV_MPU6050_SCAN_GYRO_X,
 293         INV_MPU6050_SCAN_GYRO_Y,
 294         INV_MPU6050_SCAN_GYRO_Z,
 295         INV_MPU6050_SCAN_TIMESTAMP,
 296 };
 297
 298 /* scan element definition for ICM20602, which includes temperature */
 299 enum inv_icm20602_scan {
 300         INV_ICM20602_SCAN_ACCL_X,
 301         INV_ICM20602_SCAN_ACCL_Y,
 302         INV_ICM20602_SCAN_ACCL_Z,
 303         INV_ICM20602_SCAN_TEMP,
 304         INV_ICM20602_SCAN_GYRO_X,
 305         INV_ICM20602_SCAN_GYRO_Y,
 306         INV_ICM20602_SCAN_GYRO_Z,
 307         INV_ICM20602_SCAN_TIMESTAMP,
 308 };
 309
 310 enum inv_mpu6050_filter_e {
 311         INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
 312         INV_MPU6050_FILTER_188HZ,
 313         INV_MPU6050_FILTER_98HZ,
 314         INV_MPU6050_FILTER_42HZ,
 315         INV_MPU6050_FILTER_20HZ,
 316         INV_MPU6050_FILTER_10HZ,
 317         INV_MPU6050_FILTER_5HZ,
 318         INV_MPU6050_FILTER_2100HZ_NOLPF,
 319         NUM_MPU6050_FILTER
 320 };
 321
 322 /* IIO attribute address */
 323 enum INV_MPU6050_IIO_ATTR_ADDR {
 324         ATTR_GYRO_MATRIX,
 325         ATTR_ACCL_MATRIX,
 326 };
 327
 328 enum inv_mpu6050_accl_fs_e {
 329         INV_MPU6050_FS_02G = 0,
 330         INV_MPU6050_FS_04G,
 331         INV_MPU6050_FS_08G,
 332         INV_MPU6050_FS_16G,
 333         NUM_ACCL_FSR
 334 };
 335
 336 enum inv_mpu6050_fsr_e {
 337         INV_MPU6050_FSR_250DPS = 0,
 338         INV_MPU6050_FSR_500DPS,
 339         INV_MPU6050_FSR_1000DPS,
 340         INV_MPU6050_FSR_2000DPS,
 341         NUM_MPU6050_FSR
 342 };
 343
 344 enum inv_mpu6050_clock_sel_e {
 345         INV_CLK_INTERNAL = 0,
 346         INV_CLK_PLL,
 347         NUM_CLK
 348 };
 349
 350 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 351 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
 352 int inv_reset_fifo(struct iio_dev *indio_dev);
 353 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
 354 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 355 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
 356 int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 357 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 358 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 359                 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 360 extern const struct dev_pm_ops inv_mpu_pmops;