?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 4.19.133
[linux/fpc-iii.git] / drivers / iommu / amd_iommu.c
blob0783f44e9afe55f0b6e03d85f2e9ebf00f5ef81f
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dma-direct.h>
32 #include <linux/iommu-helper.h>
33 #include <linux/iommu.h>
34 #include <linux/delay.h>
35 #include <linux/amd-iommu.h>
36 #include <linux/notifier.h>
37 #include <linux/export.h>
38 #include <linux/irq.h>
39 #include <linux/msi.h>
40 #include <linux/dma-contiguous.h>
41 #include <linux/irqdomain.h>
42 #include <linux/percpu.h>
43 #include <linux/iova.h>
44 #include <asm/irq_remapping.h>
45 #include <asm/io_apic.h>
46 #include <asm/apic.h>
47 #include <asm/hw_irq.h>
48 #include <asm/msidef.h>
49 #include <asm/proto.h>
50 #include <asm/iommu.h>
51 #include <asm/gart.h>
52 #include <asm/dma.h>
53
54 #include "amd_iommu_proto.h"
55 #include "amd_iommu_types.h"
56 #include "irq_remapping.h"
57
58 #define AMD_IOMMU_MAPPING_ERROR 0
59
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
62 #define LOOP_TIMEOUT 100000
63
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
85 static DEFINE_SPINLOCK(pd_bitmap_lock);
86
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * general struct to manage commands send to an IOMMU
107 */
108 struct iommu_cmd {
109 u32 data[4];
110 };
111
112 struct kmem_cache *amd_iommu_irq_cache;
113
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118
119 /*
120 * Data container for a dma_ops specific protection domain
121 */
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
128 };
129
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
132
133 /****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
141 {
142 struct acpi_device *adev = ACPI_COMPANION(dev);
143 const char *hid, *uid;
144
145 if (!adev)
146 return -ENODEV;
147
148 hid = acpi_device_hid(adev);
149 uid = acpi_device_uid(adev);
150
151 if (!hid || !(*hid))
152 return -ENODEV;
153
154 if (!uid || !(*uid))
155 return strcmp(hid, entry->hid);
156
157 if (!(*entry->uid))
158 return strcmp(hid, entry->hid);
159
160 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
161 }
162
163 static inline u16 get_pci_device_id(struct device *dev)
164 {
165 struct pci_dev *pdev = to_pci_dev(dev);
166
167 return PCI_DEVID(pdev->bus->number, pdev->devfn);
168 }
169
170 static inline int get_acpihid_device_id(struct device *dev,
171 struct acpihid_map_entry **entry)
172 {
173 struct acpihid_map_entry *p;
174
175 list_for_each_entry(p, &acpihid_map, list) {
176 if (!match_hid_uid(dev, p)) {
177 if (entry)
178 *entry = p;
179 return p->devid;
180 }
181 }
182 return -EINVAL;
183 }
184
185 static inline int get_device_id(struct device *dev)
186 {
187 int devid;
188
189 if (dev_is_pci(dev))
190 devid = get_pci_device_id(dev);
191 else
192 devid = get_acpihid_device_id(dev, NULL);
193
194 return devid;
195 }
196
197 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
198 {
199 return container_of(dom, struct protection_domain, domain);
200 }
201
202 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
203 {
204 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
205 return container_of(domain, struct dma_ops_domain, domain);
206 }
207
208 static struct iommu_dev_data *alloc_dev_data(u16 devid)
209 {
210 struct iommu_dev_data *dev_data;
211
212 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
213 if (!dev_data)
214 return NULL;
215
216 dev_data->devid = devid;
217 ratelimit_default_init(&dev_data->rs);
218
219 llist_add(&dev_data->dev_data_list, &dev_data_list);
220 return dev_data;
221 }
222
223 static struct iommu_dev_data *search_dev_data(u16 devid)
224 {
225 struct iommu_dev_data *dev_data;
226 struct llist_node *node;
227
228 if (llist_empty(&dev_data_list))
229 return NULL;
230
231 node = dev_data_list.first;
232 llist_for_each_entry(dev_data, node, dev_data_list) {
233 if (dev_data->devid == devid)
234 return dev_data;
235 }
236
237 return NULL;
238 }
239
240 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
241 {
242 *(u16 *)data = alias;
243 return 0;
244 }
245
246 static u16 get_alias(struct device *dev)
247 {
248 struct pci_dev *pdev = to_pci_dev(dev);
249 u16 devid, ivrs_alias, pci_alias;
250
251 /* The callers make sure that get_device_id() does not fail here */
252 devid = get_device_id(dev);
253
254 /* For ACPI HID devices, we simply return the devid as such */
255 if (!dev_is_pci(dev))
256 return devid;
257
258 ivrs_alias = amd_iommu_alias_table[devid];
259
260 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
261
262 if (ivrs_alias == pci_alias)
263 return ivrs_alias;
264
265 /*
266 * DMA alias showdown
267 *
268 * The IVRS is fairly reliable in telling us about aliases, but it
269 * can't know about every screwy device. If we don't have an IVRS
270 * reported alias, use the PCI reported alias. In that case we may
271 * still need to initialize the rlookup and dev_table entries if the
272 * alias is to a non-existent device.
273 */
274 if (ivrs_alias == devid) {
275 if (!amd_iommu_rlookup_table[pci_alias]) {
276 amd_iommu_rlookup_table[pci_alias] =
277 amd_iommu_rlookup_table[devid];
278 memcpy(amd_iommu_dev_table[pci_alias].data,
279 amd_iommu_dev_table[devid].data,
280 sizeof(amd_iommu_dev_table[pci_alias].data));
281 }
282
283 return pci_alias;
284 }
285
286 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
287 "for device %s[%04x:%04x], kernel reported alias "
288 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
289 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
290 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
291 PCI_FUNC(pci_alias));
292
293 /*
294 * If we don't have a PCI DMA alias and the IVRS alias is on the same
295 * bus, then the IVRS table may know about a quirk that we don't.
296 */
297 if (pci_alias == devid &&
298 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
299 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
300 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
301 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
302 dev_name(dev));
303 }
304
305 return ivrs_alias;
306 }
307
308 static struct iommu_dev_data *find_dev_data(u16 devid)
309 {
310 struct iommu_dev_data *dev_data;
311 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
312
313 dev_data = search_dev_data(devid);
314
315 if (dev_data == NULL) {
316 dev_data = alloc_dev_data(devid);
317 if (!dev_data)
318 return NULL;
319
320 if (translation_pre_enabled(iommu))
321 dev_data->defer_attach = true;
322 }
323
324 return dev_data;
325 }
326
327 struct iommu_dev_data *get_dev_data(struct device *dev)
328 {
329 return dev->archdata.iommu;
330 }
331 EXPORT_SYMBOL(get_dev_data);
332
333 /*
334 * Find or create an IOMMU group for a acpihid device.
335 */
336 static struct iommu_group *acpihid_device_group(struct device *dev)
337 {
338 struct acpihid_map_entry *p, *entry = NULL;
339 int devid;
340
341 devid = get_acpihid_device_id(dev, &entry);
342 if (devid < 0)
343 return ERR_PTR(devid);
344
345 list_for_each_entry(p, &acpihid_map, list) {
346 if ((devid == p->devid) && p->group)
347 entry->group = p->group;
348 }
349
350 if (!entry->group)
351 entry->group = generic_device_group(dev);
352 else
353 iommu_group_ref_get(entry->group);
354
355 return entry->group;
356 }
357
358 static bool pci_iommuv2_capable(struct pci_dev *pdev)
359 {
360 static const int caps[] = {
361 PCI_EXT_CAP_ID_ATS,
362 PCI_EXT_CAP_ID_PRI,
363 PCI_EXT_CAP_ID_PASID,
364 };
365 int i, pos;
366
367 if (pci_ats_disabled())
368 return false;
369
370 for (i = 0; i < 3; ++i) {
371 pos = pci_find_ext_capability(pdev, caps[i]);
372 if (pos == 0)
373 return false;
374 }
375
376 return true;
377 }
378
379 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
380 {
381 struct iommu_dev_data *dev_data;
382
383 dev_data = get_dev_data(&pdev->dev);
384
385 return dev_data->errata & (1 << erratum) ? true : false;
386 }
387
388 /*
389 * This function checks if the driver got a valid device from the caller to
390 * avoid dereferencing invalid pointers.
391 */
392 static bool check_device(struct device *dev)
393 {
394 int devid;
395
396 if (!dev || !dev->dma_mask)
397 return false;
398
399 devid = get_device_id(dev);
400 if (devid < 0)
401 return false;
402
403 /* Out of our scope? */
404 if (devid > amd_iommu_last_bdf)
405 return false;
406
407 if (amd_iommu_rlookup_table[devid] == NULL)
408 return false;
409
410 return true;
411 }
412
413 static void init_iommu_group(struct device *dev)
414 {
415 struct iommu_group *group;
416
417 group = iommu_group_get_for_dev(dev);
418 if (IS_ERR(group))
419 return;
420
421 iommu_group_put(group);
422 }
423
424 static int iommu_init_device(struct device *dev)
425 {
426 struct iommu_dev_data *dev_data;
427 struct amd_iommu *iommu;
428 int devid;
429
430 if (dev->archdata.iommu)
431 return 0;
432
433 devid = get_device_id(dev);
434 if (devid < 0)
435 return devid;
436
437 iommu = amd_iommu_rlookup_table[devid];
438
439 dev_data = find_dev_data(devid);
440 if (!dev_data)
441 return -ENOMEM;
442
443 dev_data->alias = get_alias(dev);
444
445 /*
446 * By default we use passthrough mode for IOMMUv2 capable device.
447 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
448 * invalid address), we ignore the capability for the device so
449 * it'll be forced to go into translation mode.
450 */
451 if ((iommu_pass_through || !amd_iommu_force_isolation) &&
452 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
453 struct amd_iommu *iommu;
454
455 iommu = amd_iommu_rlookup_table[dev_data->devid];
456 dev_data->iommu_v2 = iommu->is_iommu_v2;
457 }
458
459 dev->archdata.iommu = dev_data;
460
461 iommu_device_link(&iommu->iommu, dev);
462
463 return 0;
464 }
465
466 static void iommu_ignore_device(struct device *dev)
467 {
468 u16 alias;
469 int devid;
470
471 devid = get_device_id(dev);
472 if (devid < 0)
473 return;
474
475 alias = get_alias(dev);
476
477 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
478 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
479
480 amd_iommu_rlookup_table[devid] = NULL;
481 amd_iommu_rlookup_table[alias] = NULL;
482 }
483
484 static void iommu_uninit_device(struct device *dev)
485 {
486 struct iommu_dev_data *dev_data;
487 struct amd_iommu *iommu;
488 int devid;
489
490 devid = get_device_id(dev);
491 if (devid < 0)
492 return;
493
494 iommu = amd_iommu_rlookup_table[devid];
495
496 dev_data = search_dev_data(devid);
497 if (!dev_data)
498 return;
499
500 if (dev_data->domain)
501 detach_device(dev);
502
503 iommu_device_unlink(&iommu->iommu, dev);
504
505 iommu_group_remove_device(dev);
506
507 /* Remove dma-ops */
508 dev->dma_ops = NULL;
509
510 /*
511 * We keep dev_data around for unplugged devices and reuse it when the
512 * device is re-plugged - not doing so would introduce a ton of races.
513 */
514 }
515
516 /****************************************************************************
517 *
518 * Interrupt handling functions
519 *
520 ****************************************************************************/
521
522 static void dump_dte_entry(u16 devid)
523 {
524 int i;
525
526 for (i = 0; i < 4; ++i)
527 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
528 amd_iommu_dev_table[devid].data[i]);
529 }
530
531 static void dump_command(unsigned long phys_addr)
532 {
533 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
534 int i;
535
536 for (i = 0; i < 4; ++i)
537 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
538 }
539
540 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
541 u64 address, int flags)
542 {
543 struct iommu_dev_data *dev_data = NULL;
544 struct pci_dev *pdev;
545
546 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
547 devid & 0xff);
548 if (pdev)
549 dev_data = get_dev_data(&pdev->dev);
550
551 if (dev_data && __ratelimit(&dev_data->rs)) {
552 dev_err(&pdev->dev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
553 domain_id, address, flags);
554 } else if (printk_ratelimit()) {
555 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
556 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
557 domain_id, address, flags);
558 }
559
560 if (pdev)
561 pci_dev_put(pdev);
562 }
563
564 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
565 {
566 struct device *dev = iommu->iommu.dev;
567 int type, devid, pasid, flags, tag;
568 volatile u32 *event = __evt;
569 int count = 0;
570 u64 address;
571
572 retry:
573 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
574 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
575 pasid = PPR_PASID(*(u64 *)&event[0]);
576 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
577 address = (u64)(((u64)event[3]) << 32) | event[2];
578
579 if (type == 0) {
580 /* Did we hit the erratum? */
581 if (++count == LOOP_TIMEOUT) {
582 pr_err("AMD-Vi: No event written to event log\n");
583 return;
584 }
585 udelay(1);
586 goto retry;
587 }
588
589 if (type == EVENT_TYPE_IO_FAULT) {
590 amd_iommu_report_page_fault(devid, pasid, address, flags);
591 return;
592 }
593
594 switch (type) {
595 case EVENT_TYPE_ILL_DEV:
596 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 pasid, address, flags);
599 dump_dte_entry(devid);
600 break;
601 case EVENT_TYPE_DEV_TAB_ERR:
602 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
603 "address=0x%016llx flags=0x%04x]\n",
604 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
605 address, flags);
606 break;
607 case EVENT_TYPE_PAGE_TAB_ERR:
608 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
609 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
610 pasid, address, flags);
611 break;
612 case EVENT_TYPE_ILL_CMD:
613 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
614 dump_command(address);
615 break;
616 case EVENT_TYPE_CMD_HARD_ERR:
617 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
618 address, flags);
619 break;
620 case EVENT_TYPE_IOTLB_INV_TO:
621 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
622 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
623 address);
624 break;
625 case EVENT_TYPE_INV_DEV_REQ:
626 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
628 pasid, address, flags);
629 break;
630 case EVENT_TYPE_INV_PPR_REQ:
631 pasid = ((event[0] >> 16) & 0xFFFF)
632 | ((event[1] << 6) & 0xF0000);
633 tag = event[1] & 0x03FF;
634 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
635 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
636 pasid, address, flags);
637 break;
638 default:
639 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
640 event[0], event[1], event[2], event[3]);
641 }
642
643 memset(__evt, 0, 4 * sizeof(u32));
644 }
645
646 static void iommu_poll_events(struct amd_iommu *iommu)
647 {
648 u32 head, tail;
649
650 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
651 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
652
653 while (head != tail) {
654 iommu_print_event(iommu, iommu->evt_buf + head);
655 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
656 }
657
658 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
659 }
660
661 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
662 {
663 struct amd_iommu_fault fault;
664
665 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
666 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
667 return;
668 }
669
670 fault.address = raw[1];
671 fault.pasid = PPR_PASID(raw[0]);
672 fault.device_id = PPR_DEVID(raw[0]);
673 fault.tag = PPR_TAG(raw[0]);
674 fault.flags = PPR_FLAGS(raw[0]);
675
676 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
677 }
678
679 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
680 {
681 u32 head, tail;
682
683 if (iommu->ppr_log == NULL)
684 return;
685
686 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
687 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
688
689 while (head != tail) {
690 volatile u64 *raw;
691 u64 entry[2];
692 int i;
693
694 raw = (u64 *)(iommu->ppr_log + head);
695
696 /*
697 * Hardware bug: Interrupt may arrive before the entry is
698 * written to memory. If this happens we need to wait for the
699 * entry to arrive.
700 */
701 for (i = 0; i < LOOP_TIMEOUT; ++i) {
702 if (PPR_REQ_TYPE(raw[0]) != 0)
703 break;
704 udelay(1);
705 }
706
707 /* Avoid memcpy function-call overhead */
708 entry[0] = raw[0];
709 entry[1] = raw[1];
710
711 /*
712 * To detect the hardware bug we need to clear the entry
713 * back to zero.
714 */
715 raw[0] = raw[1] = 0UL;
716
717 /* Update head pointer of hardware ring-buffer */
718 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
719 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
720
721 /* Handle PPR entry */
722 iommu_handle_ppr_entry(iommu, entry);
723
724 /* Refresh ring-buffer information */
725 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
726 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
727 }
728 }
729
730 #ifdef CONFIG_IRQ_REMAP
731 static int (*iommu_ga_log_notifier)(u32);
732
733 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
734 {
735 iommu_ga_log_notifier = notifier;
736
737 return 0;
738 }
739 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
740
741 static void iommu_poll_ga_log(struct amd_iommu *iommu)
742 {
743 u32 head, tail, cnt = 0;
744
745 if (iommu->ga_log == NULL)
746 return;
747
748 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
749 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
750
751 while (head != tail) {
752 volatile u64 *raw;
753 u64 log_entry;
754
755 raw = (u64 *)(iommu->ga_log + head);
756 cnt++;
757
758 /* Avoid memcpy function-call overhead */
759 log_entry = *raw;
760
761 /* Update head pointer of hardware ring-buffer */
762 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
763 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
764
765 /* Handle GA entry */
766 switch (GA_REQ_TYPE(log_entry)) {
767 case GA_GUEST_NR:
768 if (!iommu_ga_log_notifier)
769 break;
770
771 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
772 __func__, GA_DEVID(log_entry),
773 GA_TAG(log_entry));
774
775 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
776 pr_err("AMD-Vi: GA log notifier failed.\n");
777 break;
778 default:
779 break;
780 }
781 }
782 }
783 #endif /* CONFIG_IRQ_REMAP */
784
785 #define AMD_IOMMU_INT_MASK \
786 (MMIO_STATUS_EVT_INT_MASK | \
787 MMIO_STATUS_PPR_INT_MASK | \
788 MMIO_STATUS_GALOG_INT_MASK)
789
790 irqreturn_t amd_iommu_int_thread(int irq, void *data)
791 {
792 struct amd_iommu *iommu = (struct amd_iommu *) data;
793 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
794
795 while (status & AMD_IOMMU_INT_MASK) {
796 /* Enable EVT and PPR and GA interrupts again */
797 writel(AMD_IOMMU_INT_MASK,
798 iommu->mmio_base + MMIO_STATUS_OFFSET);
799
800 if (status & MMIO_STATUS_EVT_INT_MASK) {
801 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
802 iommu_poll_events(iommu);
803 }
804
805 if (status & MMIO_STATUS_PPR_INT_MASK) {
806 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
807 iommu_poll_ppr_log(iommu);
808 }
809
810 #ifdef CONFIG_IRQ_REMAP
811 if (status & MMIO_STATUS_GALOG_INT_MASK) {
812 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
813 iommu_poll_ga_log(iommu);
814 }
815 #endif
816
817 /*
818 * Hardware bug: ERBT1312
819 * When re-enabling interrupt (by writing 1
820 * to clear the bit), the hardware might also try to set
821 * the interrupt bit in the event status register.
822 * In this scenario, the bit will be set, and disable
823 * subsequent interrupts.
824 *
825 * Workaround: The IOMMU driver should read back the
826 * status register and check if the interrupt bits are cleared.
827 * If not, driver will need to go through the interrupt handler
828 * again and re-clear the bits
829 */
830 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
831 }
832 return IRQ_HANDLED;
833 }
834
835 irqreturn_t amd_iommu_int_handler(int irq, void *data)
836 {
837 return IRQ_WAKE_THREAD;
838 }
839
840 /****************************************************************************
841 *
842 * IOMMU command queuing functions
843 *
844 ****************************************************************************/
845
846 static int wait_on_sem(volatile u64 *sem)
847 {
848 int i = 0;
849
850 while (*sem == 0 && i < LOOP_TIMEOUT) {
851 udelay(1);
852 i += 1;
853 }
854
855 if (i == LOOP_TIMEOUT) {
856 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
857 return -EIO;
858 }
859
860 return 0;
861 }
862
863 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
864 struct iommu_cmd *cmd)
865 {
866 u8 *target;
867
868 target = iommu->cmd_buf + iommu->cmd_buf_tail;
869
870 iommu->cmd_buf_tail += sizeof(*cmd);
871 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
872
873 /* Copy command to buffer */
874 memcpy(target, cmd, sizeof(*cmd));
875
876 /* Tell the IOMMU about it */
877 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
878 }
879
880 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
881 {
882 u64 paddr = iommu_virt_to_phys((void *)address);
883
884 WARN_ON(address & 0x7ULL);
885
886 memset(cmd, 0, sizeof(*cmd));
887 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
888 cmd->data[1] = upper_32_bits(paddr);
889 cmd->data[2] = 1;
890 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
891 }
892
893 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
894 {
895 memset(cmd, 0, sizeof(*cmd));
896 cmd->data[0] = devid;
897 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
898 }
899
900 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
901 size_t size, u16 domid, int pde)
902 {
903 u64 pages;
904 bool s;
905
906 pages = iommu_num_pages(address, size, PAGE_SIZE);
907 s = false;
908
909 if (pages > 1) {
910 /*
911 * If we have to flush more than one page, flush all
912 * TLB entries for this domain
913 */
914 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
915 s = true;
916 }
917
918 address &= PAGE_MASK;
919
920 memset(cmd, 0, sizeof(*cmd));
921 cmd->data[1] |= domid;
922 cmd->data[2] = lower_32_bits(address);
923 cmd->data[3] = upper_32_bits(address);
924 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
925 if (s) /* size bit - we flush more than one 4kb page */
926 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
927 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
928 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
929 }
930
931 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
932 u64 address, size_t size)
933 {
934 u64 pages;
935 bool s;
936
937 pages = iommu_num_pages(address, size, PAGE_SIZE);
938 s = false;
939
940 if (pages > 1) {
941 /*
942 * If we have to flush more than one page, flush all
943 * TLB entries for this domain
944 */
945 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
946 s = true;
947 }
948
949 address &= PAGE_MASK;
950
951 memset(cmd, 0, sizeof(*cmd));
952 cmd->data[0] = devid;
953 cmd->data[0] |= (qdep & 0xff) << 24;
954 cmd->data[1] = devid;
955 cmd->data[2] = lower_32_bits(address);
956 cmd->data[3] = upper_32_bits(address);
957 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
958 if (s)
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
960 }
961
962 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
963 u64 address, bool size)
964 {
965 memset(cmd, 0, sizeof(*cmd));
966
967 address &= ~(0xfffULL);
968
969 cmd->data[0] = pasid;
970 cmd->data[1] = domid;
971 cmd->data[2] = lower_32_bits(address);
972 cmd->data[3] = upper_32_bits(address);
973 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
975 if (size)
976 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
977 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
978 }
979
980 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
981 int qdep, u64 address, bool size)
982 {
983 memset(cmd, 0, sizeof(*cmd));
984
985 address &= ~(0xfffULL);
986
987 cmd->data[0] = devid;
988 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
989 cmd->data[0] |= (qdep & 0xff) << 24;
990 cmd->data[1] = devid;
991 cmd->data[1] |= (pasid & 0xff) << 16;
992 cmd->data[2] = lower_32_bits(address);
993 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
994 cmd->data[3] = upper_32_bits(address);
995 if (size)
996 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
997 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
998 }
999
1000 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
1001 int status, int tag, bool gn)
1002 {
1003 memset(cmd, 0, sizeof(*cmd));
1004
1005 cmd->data[0] = devid;
1006 if (gn) {
1007 cmd->data[1] = pasid;
1008 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1009 }
1010 cmd->data[3] = tag & 0x1ff;
1011 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1012
1013 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1014 }
1015
1016 static void build_inv_all(struct iommu_cmd *cmd)
1017 {
1018 memset(cmd, 0, sizeof(*cmd));
1019 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1020 }
1021
1022 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1023 {
1024 memset(cmd, 0, sizeof(*cmd));
1025 cmd->data[0] = devid;
1026 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1027 }
1028
1029 /*
1030 * Writes the command to the IOMMUs command buffer and informs the
1031 * hardware about the new command.
1032 */
1033 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1034 struct iommu_cmd *cmd,
1035 bool sync)
1036 {
1037 unsigned int count = 0;
1038 u32 left, next_tail;
1039
1040 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1041 again:
1042 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1043
1044 if (left <= 0x20) {
1045 /* Skip udelay() the first time around */
1046 if (count++) {
1047 if (count == LOOP_TIMEOUT) {
1048 pr_err("AMD-Vi: Command buffer timeout\n");
1049 return -EIO;
1050 }
1051
1052 udelay(1);
1053 }
1054
1055 /* Update head and recheck remaining space */
1056 iommu->cmd_buf_head = readl(iommu->mmio_base +
1057 MMIO_CMD_HEAD_OFFSET);
1058
1059 goto again;
1060 }
1061
1062 copy_cmd_to_buffer(iommu, cmd);
1063
1064 /* Do we need to make sure all commands are processed? */
1065 iommu->need_sync = sync;
1066
1067 return 0;
1068 }
1069
1070 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1071 struct iommu_cmd *cmd,
1072 bool sync)
1073 {
1074 unsigned long flags;
1075 int ret;
1076
1077 raw_spin_lock_irqsave(&iommu->lock, flags);
1078 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1079 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1080
1081 return ret;
1082 }
1083
1084 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1085 {
1086 return iommu_queue_command_sync(iommu, cmd, true);
1087 }
1088
1089 /*
1090 * This function queues a completion wait command into the command
1091 * buffer of an IOMMU
1092 */
1093 static int iommu_completion_wait(struct amd_iommu *iommu)
1094 {
1095 struct iommu_cmd cmd;
1096 unsigned long flags;
1097 int ret;
1098
1099 if (!iommu->need_sync)
1100 return 0;
1101
1102
1103 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1104
1105 raw_spin_lock_irqsave(&iommu->lock, flags);
1106
1107 iommu->cmd_sem = 0;
1108
1109 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1110 if (ret)
1111 goto out_unlock;
1112
1113 ret = wait_on_sem(&iommu->cmd_sem);
1114
1115 out_unlock:
1116 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1117
1118 return ret;
1119 }
1120
1121 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1122 {
1123 struct iommu_cmd cmd;
1124
1125 build_inv_dte(&cmd, devid);
1126
1127 return iommu_queue_command(iommu, &cmd);
1128 }
1129
1130 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1131 {
1132 u32 devid;
1133
1134 for (devid = 0; devid <= 0xffff; ++devid)
1135 iommu_flush_dte(iommu, devid);
1136
1137 iommu_completion_wait(iommu);
1138 }
1139
1140 /*
1141 * This function uses heavy locking and may disable irqs for some time. But
1142 * this is no issue because it is only called during resume.
1143 */
1144 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1145 {
1146 u32 dom_id;
1147
1148 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1149 struct iommu_cmd cmd;
1150 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1151 dom_id, 1);
1152 iommu_queue_command(iommu, &cmd);
1153 }
1154
1155 iommu_completion_wait(iommu);
1156 }
1157
1158 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1159 {
1160 struct iommu_cmd cmd;
1161
1162 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1163 dom_id, 1);
1164 iommu_queue_command(iommu, &cmd);
1165
1166 iommu_completion_wait(iommu);
1167 }
1168
1169 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1170 {
1171 struct iommu_cmd cmd;
1172
1173 build_inv_all(&cmd);
1174
1175 iommu_queue_command(iommu, &cmd);
1176 iommu_completion_wait(iommu);
1177 }
1178
1179 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1180 {
1181 struct iommu_cmd cmd;
1182
1183 build_inv_irt(&cmd, devid);
1184
1185 iommu_queue_command(iommu, &cmd);
1186 }
1187
1188 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1189 {
1190 u32 devid;
1191
1192 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1193 iommu_flush_irt(iommu, devid);
1194
1195 iommu_completion_wait(iommu);
1196 }
1197
1198 void iommu_flush_all_caches(struct amd_iommu *iommu)
1199 {
1200 if (iommu_feature(iommu, FEATURE_IA)) {
1201 amd_iommu_flush_all(iommu);
1202 } else {
1203 amd_iommu_flush_dte_all(iommu);
1204 amd_iommu_flush_irt_all(iommu);
1205 amd_iommu_flush_tlb_all(iommu);
1206 }
1207 }
1208
1209 /*
1210 * Command send function for flushing on-device TLB
1211 */
1212 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1213 u64 address, size_t size)
1214 {
1215 struct amd_iommu *iommu;
1216 struct iommu_cmd cmd;
1217 int qdep;
1218
1219 qdep = dev_data->ats.qdep;
1220 iommu = amd_iommu_rlookup_table[dev_data->devid];
1221
1222 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1223
1224 return iommu_queue_command(iommu, &cmd);
1225 }
1226
1227 /*
1228 * Command send function for invalidating a device table entry
1229 */
1230 static int device_flush_dte(struct iommu_dev_data *dev_data)
1231 {
1232 struct amd_iommu *iommu;
1233 u16 alias;
1234 int ret;
1235
1236 iommu = amd_iommu_rlookup_table[dev_data->devid];
1237 alias = dev_data->alias;
1238
1239 ret = iommu_flush_dte(iommu, dev_data->devid);
1240 if (!ret && alias != dev_data->devid)
1241 ret = iommu_flush_dte(iommu, alias);
1242 if (ret)
1243 return ret;
1244
1245 if (dev_data->ats.enabled)
1246 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1247
1248 return ret;
1249 }
1250
1251 /*
1252 * TLB invalidation function which is called from the mapping functions.
1253 * It invalidates a single PTE if the range to flush is within a single
1254 * page. Otherwise it flushes the whole TLB of the IOMMU.
1255 */
1256 static void __domain_flush_pages(struct protection_domain *domain,
1257 u64 address, size_t size, int pde)
1258 {
1259 struct iommu_dev_data *dev_data;
1260 struct iommu_cmd cmd;
1261 int ret = 0, i;
1262
1263 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1264
1265 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1266 if (!domain->dev_iommu[i])
1267 continue;
1268
1269 /*
1270 * Devices of this domain are behind this IOMMU
1271 * We need a TLB flush
1272 */
1273 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1274 }
1275
1276 list_for_each_entry(dev_data, &domain->dev_list, list) {
1277
1278 if (!dev_data->ats.enabled)
1279 continue;
1280
1281 ret |= device_flush_iotlb(dev_data, address, size);
1282 }
1283
1284 WARN_ON(ret);
1285 }
1286
1287 static void domain_flush_pages(struct protection_domain *domain,
1288 u64 address, size_t size)
1289 {
1290 __domain_flush_pages(domain, address, size, 0);
1291 }
1292
1293 /* Flush the whole IO/TLB for a given protection domain */
1294 static void domain_flush_tlb(struct protection_domain *domain)
1295 {
1296 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1297 }
1298
1299 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1300 static void domain_flush_tlb_pde(struct protection_domain *domain)
1301 {
1302 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1303 }
1304
1305 static void domain_flush_complete(struct protection_domain *domain)
1306 {
1307 int i;
1308
1309 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1310 if (domain && !domain->dev_iommu[i])
1311 continue;
1312
1313 /*
1314 * Devices of this domain are behind this IOMMU
1315 * We need to wait for completion of all commands.
1316 */
1317 iommu_completion_wait(amd_iommus[i]);
1318 }
1319 }
1320
1321
1322 /*
1323 * This function flushes the DTEs for all devices in domain
1324 */
1325 static void domain_flush_devices(struct protection_domain *domain)
1326 {
1327 struct iommu_dev_data *dev_data;
1328
1329 list_for_each_entry(dev_data, &domain->dev_list, list)
1330 device_flush_dte(dev_data);
1331 }
1332
1333 /****************************************************************************
1334 *
1335 * The functions below are used the create the page table mappings for
1336 * unity mapped regions.
1337 *
1338 ****************************************************************************/
1339
1340 /*
1341 * This function is used to add another level to an IO page table. Adding
1342 * another level increases the size of the address space by 9 bits to a size up
1343 * to 64 bits.
1344 */
1345 static void increase_address_space(struct protection_domain *domain,
1346 gfp_t gfp)
1347 {
1348 unsigned long flags;
1349 u64 *pte;
1350
1351 spin_lock_irqsave(&domain->lock, flags);
1352
1353 if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1354 /* address space already 64 bit large */
1355 goto out;
1356
1357 pte = (void *)get_zeroed_page(gfp);
1358 if (!pte)
1359 goto out;
1360
1361 *pte = PM_LEVEL_PDE(domain->mode,
1362 iommu_virt_to_phys(domain->pt_root));
1363 domain->pt_root = pte;
1364 domain->mode += 1;
1365 domain->updated = true;
1366
1367 out:
1368 spin_unlock_irqrestore(&domain->lock, flags);
1369
1370 return;
1371 }
1372
1373 static u64 *alloc_pte(struct protection_domain *domain,
1374 unsigned long address,
1375 unsigned long page_size,
1376 u64 **pte_page,
1377 gfp_t gfp)
1378 {
1379 int level, end_lvl;
1380 u64 *pte, *page;
1381
1382 BUG_ON(!is_power_of_2(page_size));
1383
1384 while (address > PM_LEVEL_SIZE(domain->mode))
1385 increase_address_space(domain, gfp);
1386
1387 level = domain->mode - 1;
1388 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1389 address = PAGE_SIZE_ALIGN(address, page_size);
1390 end_lvl = PAGE_SIZE_LEVEL(page_size);
1391
1392 while (level > end_lvl) {
1393 u64 __pte, __npte;
1394
1395 __pte = *pte;
1396
1397 if (!IOMMU_PTE_PRESENT(__pte)) {
1398 page = (u64 *)get_zeroed_page(gfp);
1399 if (!page)
1400 return NULL;
1401
1402 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1403
1404 /* pte could have been changed somewhere. */
1405 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1406 free_page((unsigned long)page);
1407 continue;
1408 }
1409 }
1410
1411 /* No level skipping support yet */
1412 if (PM_PTE_LEVEL(*pte) != level)
1413 return NULL;
1414
1415 level -= 1;
1416
1417 pte = IOMMU_PTE_PAGE(*pte);
1418
1419 if (pte_page && level == end_lvl)
1420 *pte_page = pte;
1421
1422 pte = &pte[PM_LEVEL_INDEX(level, address)];
1423 }
1424
1425 return pte;
1426 }
1427
1428 /*
1429 * This function checks if there is a PTE for a given dma address. If
1430 * there is one, it returns the pointer to it.
1431 */
1432 static u64 *fetch_pte(struct protection_domain *domain,
1433 unsigned long address,
1434 unsigned long *page_size)
1435 {
1436 int level;
1437 u64 *pte;
1438
1439 *page_size = 0;
1440
1441 if (address > PM_LEVEL_SIZE(domain->mode))
1442 return NULL;
1443
1444 level = domain->mode - 1;
1445 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1446 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1447
1448 while (level > 0) {
1449
1450 /* Not Present */
1451 if (!IOMMU_PTE_PRESENT(*pte))
1452 return NULL;
1453
1454 /* Large PTE */
1455 if (PM_PTE_LEVEL(*pte) == 7 ||
1456 PM_PTE_LEVEL(*pte) == 0)
1457 break;
1458
1459 /* No level skipping support yet */
1460 if (PM_PTE_LEVEL(*pte) != level)
1461 return NULL;
1462
1463 level -= 1;
1464
1465 /* Walk to the next level */
1466 pte = IOMMU_PTE_PAGE(*pte);
1467 pte = &pte[PM_LEVEL_INDEX(level, address)];
1468 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1469 }
1470
1471 if (PM_PTE_LEVEL(*pte) == 0x07) {
1472 unsigned long pte_mask;
1473
1474 /*
1475 * If we have a series of large PTEs, make
1476 * sure to return a pointer to the first one.
1477 */
1478 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1479 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1480 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1481 }
1482
1483 return pte;
1484 }
1485
1486 /*
1487 * Generic mapping functions. It maps a physical address into a DMA
1488 * address space. It allocates the page table pages if necessary.
1489 * In the future it can be extended to a generic mapping function
1490 * supporting all features of AMD IOMMU page tables like level skipping
1491 * and full 64 bit address spaces.
1492 */
1493 static int iommu_map_page(struct protection_domain *dom,
1494 unsigned long bus_addr,
1495 unsigned long phys_addr,
1496 unsigned long page_size,
1497 int prot,
1498 gfp_t gfp)
1499 {
1500 u64 __pte, *pte;
1501 int i, count;
1502
1503 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1504 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1505
1506 if (!(prot & IOMMU_PROT_MASK))
1507 return -EINVAL;
1508
1509 count = PAGE_SIZE_PTE_COUNT(page_size);
1510 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1511
1512 if (!pte)
1513 return -ENOMEM;
1514
1515 for (i = 0; i < count; ++i)
1516 if (IOMMU_PTE_PRESENT(pte[i]))
1517 return -EBUSY;
1518
1519 if (count > 1) {
1520 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1521 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1522 } else
1523 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1524
1525 if (prot & IOMMU_PROT_IR)
1526 __pte |= IOMMU_PTE_IR;
1527 if (prot & IOMMU_PROT_IW)
1528 __pte |= IOMMU_PTE_IW;
1529
1530 for (i = 0; i < count; ++i)
1531 pte[i] = __pte;
1532
1533 update_domain(dom);
1534
1535 return 0;
1536 }
1537
1538 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1539 unsigned long bus_addr,
1540 unsigned long page_size)
1541 {
1542 unsigned long long unmapped;
1543 unsigned long unmap_size;
1544 u64 *pte;
1545
1546 BUG_ON(!is_power_of_2(page_size));
1547
1548 unmapped = 0;
1549
1550 while (unmapped < page_size) {
1551
1552 pte = fetch_pte(dom, bus_addr, &unmap_size);
1553
1554 if (pte) {
1555 int i, count;
1556
1557 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1558 for (i = 0; i < count; i++)
1559 pte[i] = 0ULL;
1560 }
1561
1562 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1563 unmapped += unmap_size;
1564 }
1565
1566 BUG_ON(unmapped && !is_power_of_2(unmapped));
1567
1568 return unmapped;
1569 }
1570
1571 /****************************************************************************
1572 *
1573 * The next functions belong to the address allocator for the dma_ops
1574 * interface functions.
1575 *
1576 ****************************************************************************/
1577
1578
1579 static unsigned long dma_ops_alloc_iova(struct device *dev,
1580 struct dma_ops_domain *dma_dom,
1581 unsigned int pages, u64 dma_mask)
1582 {
1583 unsigned long pfn = 0;
1584
1585 pages = __roundup_pow_of_two(pages);
1586
1587 if (dma_mask > DMA_BIT_MASK(32))
1588 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1589 IOVA_PFN(DMA_BIT_MASK(32)), false);
1590
1591 if (!pfn)
1592 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1593 IOVA_PFN(dma_mask), true);
1594
1595 return (pfn << PAGE_SHIFT);
1596 }
1597
1598 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1599 unsigned long address,
1600 unsigned int pages)
1601 {
1602 pages = __roundup_pow_of_two(pages);
1603 address >>= PAGE_SHIFT;
1604
1605 free_iova_fast(&dma_dom->iovad, address, pages);
1606 }
1607
1608 /****************************************************************************
1609 *
1610 * The next functions belong to the domain allocation. A domain is
1611 * allocated for every IOMMU as the default domain. If device isolation
1612 * is enabled, every device get its own domain. The most important thing
1613 * about domains is the page table mapping the DMA address space they
1614 * contain.
1615 *
1616 ****************************************************************************/
1617
1618 /*
1619 * This function adds a protection domain to the global protection domain list
1620 */
1621 static void add_domain_to_list(struct protection_domain *domain)
1622 {
1623 unsigned long flags;
1624
1625 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1626 list_add(&domain->list, &amd_iommu_pd_list);
1627 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1628 }
1629
1630 /*
1631 * This function removes a protection domain to the global
1632 * protection domain list
1633 */
1634 static void del_domain_from_list(struct protection_domain *domain)
1635 {
1636 unsigned long flags;
1637
1638 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1639 list_del(&domain->list);
1640 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1641 }
1642
1643 static u16 domain_id_alloc(void)
1644 {
1645 int id;
1646
1647 spin_lock(&pd_bitmap_lock);
1648 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1649 BUG_ON(id == 0);
1650 if (id > 0 && id < MAX_DOMAIN_ID)
1651 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1652 else
1653 id = 0;
1654 spin_unlock(&pd_bitmap_lock);
1655
1656 return id;
1657 }
1658
1659 static void domain_id_free(int id)
1660 {
1661 spin_lock(&pd_bitmap_lock);
1662 if (id > 0 && id < MAX_DOMAIN_ID)
1663 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1664 spin_unlock(&pd_bitmap_lock);
1665 }
1666
1667 #define DEFINE_FREE_PT_FN(LVL, FN) \
1668 static void free_pt_##LVL (unsigned long __pt) \
1669 { \
1670 unsigned long p; \
1671 u64 *pt; \
1672 int i; \
1673 \
1674 pt = (u64 *)__pt; \
1675 \
1676 for (i = 0; i < 512; ++i) { \
1677 /* PTE present? */ \
1678 if (!IOMMU_PTE_PRESENT(pt[i])) \
1679 continue; \
1680 \
1681 /* Large PTE? */ \
1682 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1683 PM_PTE_LEVEL(pt[i]) == 7) \
1684 continue; \
1685 \
1686 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1687 FN(p); \
1688 } \
1689 free_page((unsigned long)pt); \
1690 }
1691
1692 DEFINE_FREE_PT_FN(l2, free_page)
1693 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1694 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1695 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1696 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1697
1698 static void free_pagetable(struct protection_domain *domain)
1699 {
1700 unsigned long root = (unsigned long)domain->pt_root;
1701
1702 switch (domain->mode) {
1703 case PAGE_MODE_NONE:
1704 break;
1705 case PAGE_MODE_1_LEVEL:
1706 free_page(root);
1707 break;
1708 case PAGE_MODE_2_LEVEL:
1709 free_pt_l2(root);
1710 break;
1711 case PAGE_MODE_3_LEVEL:
1712 free_pt_l3(root);
1713 break;
1714 case PAGE_MODE_4_LEVEL:
1715 free_pt_l4(root);
1716 break;
1717 case PAGE_MODE_5_LEVEL:
1718 free_pt_l5(root);
1719 break;
1720 case PAGE_MODE_6_LEVEL:
1721 free_pt_l6(root);
1722 break;
1723 default:
1724 BUG();
1725 }
1726 }
1727
1728 static void free_gcr3_tbl_level1(u64 *tbl)
1729 {
1730 u64 *ptr;
1731 int i;
1732
1733 for (i = 0; i < 512; ++i) {
1734 if (!(tbl[i] & GCR3_VALID))
1735 continue;
1736
1737 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1738
1739 free_page((unsigned long)ptr);
1740 }
1741 }
1742
1743 static void free_gcr3_tbl_level2(u64 *tbl)
1744 {
1745 u64 *ptr;
1746 int i;
1747
1748 for (i = 0; i < 512; ++i) {
1749 if (!(tbl[i] & GCR3_VALID))
1750 continue;
1751
1752 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1753
1754 free_gcr3_tbl_level1(ptr);
1755 }
1756 }
1757
1758 static void free_gcr3_table(struct protection_domain *domain)
1759 {
1760 if (domain->glx == 2)
1761 free_gcr3_tbl_level2(domain->gcr3_tbl);
1762 else if (domain->glx == 1)
1763 free_gcr3_tbl_level1(domain->gcr3_tbl);
1764 else
1765 BUG_ON(domain->glx != 0);
1766
1767 free_page((unsigned long)domain->gcr3_tbl);
1768 }
1769
1770 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1771 {
1772 domain_flush_tlb(&dom->domain);
1773 domain_flush_complete(&dom->domain);
1774 }
1775
1776 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1777 {
1778 struct dma_ops_domain *dom;
1779
1780 dom = container_of(iovad, struct dma_ops_domain, iovad);
1781
1782 dma_ops_domain_flush_tlb(dom);
1783 }
1784
1785 /*
1786 * Free a domain, only used if something went wrong in the
1787 * allocation path and we need to free an already allocated page table
1788 */
1789 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1790 {
1791 if (!dom)
1792 return;
1793
1794 del_domain_from_list(&dom->domain);
1795
1796 put_iova_domain(&dom->iovad);
1797
1798 free_pagetable(&dom->domain);
1799
1800 if (dom->domain.id)
1801 domain_id_free(dom->domain.id);
1802
1803 kfree(dom);
1804 }
1805
1806 /*
1807 * Allocates a new protection domain usable for the dma_ops functions.
1808 * It also initializes the page table and the address allocator data
1809 * structures required for the dma_ops interface
1810 */
1811 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1812 {
1813 struct dma_ops_domain *dma_dom;
1814
1815 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1816 if (!dma_dom)
1817 return NULL;
1818
1819 if (protection_domain_init(&dma_dom->domain))
1820 goto free_dma_dom;
1821
1822 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1823 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1824 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1825 if (!dma_dom->domain.pt_root)
1826 goto free_dma_dom;
1827
1828 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1829
1830 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1831 goto free_dma_dom;
1832
1833 /* Initialize reserved ranges */
1834 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1835
1836 add_domain_to_list(&dma_dom->domain);
1837
1838 return dma_dom;
1839
1840 free_dma_dom:
1841 dma_ops_domain_free(dma_dom);
1842
1843 return NULL;
1844 }
1845
1846 /*
1847 * little helper function to check whether a given protection domain is a
1848 * dma_ops domain
1849 */
1850 static bool dma_ops_domain(struct protection_domain *domain)
1851 {
1852 return domain->flags & PD_DMA_OPS_MASK;
1853 }
1854
1855 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1856 bool ats, bool ppr)
1857 {
1858 u64 pte_root = 0;
1859 u64 flags = 0;
1860 u32 old_domid;
1861
1862 if (domain->mode != PAGE_MODE_NONE)
1863 pte_root = iommu_virt_to_phys(domain->pt_root);
1864
1865 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1866 << DEV_ENTRY_MODE_SHIFT;
1867 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1868
1869 flags = amd_iommu_dev_table[devid].data[1];
1870
1871 if (ats)
1872 flags |= DTE_FLAG_IOTLB;
1873
1874 if (ppr) {
1875 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1876
1877 if (iommu_feature(iommu, FEATURE_EPHSUP))
1878 pte_root |= 1ULL << DEV_ENTRY_PPR;
1879 }
1880
1881 if (domain->flags & PD_IOMMUV2_MASK) {
1882 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1883 u64 glx = domain->glx;
1884 u64 tmp;
1885
1886 pte_root |= DTE_FLAG_GV;
1887 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1888
1889 /* First mask out possible old values for GCR3 table */
1890 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1891 flags &= ~tmp;
1892
1893 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1894 flags &= ~tmp;
1895
1896 /* Encode GCR3 table into DTE */
1897 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1898 pte_root |= tmp;
1899
1900 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1901 flags |= tmp;
1902
1903 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1904 flags |= tmp;
1905 }
1906
1907 flags &= ~DEV_DOMID_MASK;
1908 flags |= domain->id;
1909
1910 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1911 amd_iommu_dev_table[devid].data[1] = flags;
1912 amd_iommu_dev_table[devid].data[0] = pte_root;
1913
1914 /*
1915 * A kdump kernel might be replacing a domain ID that was copied from
1916 * the previous kernel--if so, it needs to flush the translation cache
1917 * entries for the old domain ID that is being overwritten
1918 */
1919 if (old_domid) {
1920 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1921
1922 amd_iommu_flush_tlb_domid(iommu, old_domid);
1923 }
1924 }
1925
1926 static void clear_dte_entry(u16 devid)
1927 {
1928 /* remove entry from the device table seen by the hardware */
1929 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1930 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1931
1932 amd_iommu_apply_erratum_63(devid);
1933 }
1934
1935 static void do_attach(struct iommu_dev_data *dev_data,
1936 struct protection_domain *domain)
1937 {
1938 struct amd_iommu *iommu;
1939 u16 alias;
1940 bool ats;
1941
1942 iommu = amd_iommu_rlookup_table[dev_data->devid];
1943 alias = dev_data->alias;
1944 ats = dev_data->ats.enabled;
1945
1946 /* Update data structures */
1947 dev_data->domain = domain;
1948 list_add(&dev_data->list, &domain->dev_list);
1949
1950 /* Do reference counting */
1951 domain->dev_iommu[iommu->index] += 1;
1952 domain->dev_cnt += 1;
1953
1954 /* Update device table */
1955 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1956 if (alias != dev_data->devid)
1957 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1958
1959 device_flush_dte(dev_data);
1960 }
1961
1962 static void do_detach(struct iommu_dev_data *dev_data)
1963 {
1964 struct protection_domain *domain = dev_data->domain;
1965 struct amd_iommu *iommu;
1966 u16 alias;
1967
1968 iommu = amd_iommu_rlookup_table[dev_data->devid];
1969 alias = dev_data->alias;
1970
1971 /* Update data structures */
1972 dev_data->domain = NULL;
1973 list_del(&dev_data->list);
1974 clear_dte_entry(dev_data->devid);
1975 if (alias != dev_data->devid)
1976 clear_dte_entry(alias);
1977
1978 /* Flush the DTE entry */
1979 device_flush_dte(dev_data);
1980
1981 /* Flush IOTLB */
1982 domain_flush_tlb_pde(domain);
1983
1984 /* Wait for the flushes to finish */
1985 domain_flush_complete(domain);
1986
1987 /* decrease reference counters - needs to happen after the flushes */
1988 domain->dev_iommu[iommu->index] -= 1;
1989 domain->dev_cnt -= 1;
1990 }
1991
1992 /*
1993 * If a device is not yet associated with a domain, this function makes the
1994 * device visible in the domain
1995 */
1996 static int __attach_device(struct iommu_dev_data *dev_data,
1997 struct protection_domain *domain)
1998 {
1999 int ret;
2000
2001 /* lock domain */
2002 spin_lock(&domain->lock);
2003
2004 ret = -EBUSY;
2005 if (dev_data->domain != NULL)
2006 goto out_unlock;
2007
2008 /* Attach alias group root */
2009 do_attach(dev_data, domain);
2010
2011 ret = 0;
2012
2013 out_unlock:
2014
2015 /* ready */
2016 spin_unlock(&domain->lock);
2017
2018 return ret;
2019 }
2020
2021
2022 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2023 {
2024 pci_disable_ats(pdev);
2025 pci_disable_pri(pdev);
2026 pci_disable_pasid(pdev);
2027 }
2028
2029 /* FIXME: Change generic reset-function to do the same */
2030 static int pri_reset_while_enabled(struct pci_dev *pdev)
2031 {
2032 u16 control;
2033 int pos;
2034
2035 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2036 if (!pos)
2037 return -EINVAL;
2038
2039 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2040 control |= PCI_PRI_CTRL_RESET;
2041 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2042
2043 return 0;
2044 }
2045
2046 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2047 {
2048 bool reset_enable;
2049 int reqs, ret;
2050
2051 /* FIXME: Hardcode number of outstanding requests for now */
2052 reqs = 32;
2053 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2054 reqs = 1;
2055 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2056
2057 /* Only allow access to user-accessible pages */
2058 ret = pci_enable_pasid(pdev, 0);
2059 if (ret)
2060 goto out_err;
2061
2062 /* First reset the PRI state of the device */
2063 ret = pci_reset_pri(pdev);
2064 if (ret)
2065 goto out_err;
2066
2067 /* Enable PRI */
2068 ret = pci_enable_pri(pdev, reqs);
2069 if (ret)
2070 goto out_err;
2071
2072 if (reset_enable) {
2073 ret = pri_reset_while_enabled(pdev);
2074 if (ret)
2075 goto out_err;
2076 }
2077
2078 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2079 if (ret)
2080 goto out_err;
2081
2082 return 0;
2083
2084 out_err:
2085 pci_disable_pri(pdev);
2086 pci_disable_pasid(pdev);
2087
2088 return ret;
2089 }
2090
2091 /* FIXME: Move this to PCI code */
2092 #define PCI_PRI_TLP_OFF (1 << 15)
2093
2094 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2095 {
2096 u16 status;
2097 int pos;
2098
2099 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2100 if (!pos)
2101 return false;
2102
2103 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2104
2105 return (status & PCI_PRI_TLP_OFF) ? true : false;
2106 }
2107
2108 /*
2109 * If a device is not yet associated with a domain, this function makes the
2110 * device visible in the domain
2111 */
2112 static int attach_device(struct device *dev,
2113 struct protection_domain *domain)
2114 {
2115 struct pci_dev *pdev;
2116 struct iommu_dev_data *dev_data;
2117 unsigned long flags;
2118 int ret;
2119
2120 dev_data = get_dev_data(dev);
2121
2122 if (!dev_is_pci(dev))
2123 goto skip_ats_check;
2124
2125 pdev = to_pci_dev(dev);
2126 if (domain->flags & PD_IOMMUV2_MASK) {
2127 if (!dev_data->passthrough)
2128 return -EINVAL;
2129
2130 if (dev_data->iommu_v2) {
2131 if (pdev_iommuv2_enable(pdev) != 0)
2132 return -EINVAL;
2133
2134 dev_data->ats.enabled = true;
2135 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2136 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2137 }
2138 } else if (amd_iommu_iotlb_sup &&
2139 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2140 dev_data->ats.enabled = true;
2141 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2142 }
2143
2144 skip_ats_check:
2145 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2146 ret = __attach_device(dev_data, domain);
2147 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2148
2149 /*
2150 * We might boot into a crash-kernel here. The crashed kernel
2151 * left the caches in the IOMMU dirty. So we have to flush
2152 * here to evict all dirty stuff.
2153 */
2154 domain_flush_tlb_pde(domain);
2155
2156 domain_flush_complete(domain);
2157
2158 return ret;
2159 }
2160
2161 /*
2162 * Removes a device from a protection domain (unlocked)
2163 */
2164 static void __detach_device(struct iommu_dev_data *dev_data)
2165 {
2166 struct protection_domain *domain;
2167
2168 domain = dev_data->domain;
2169
2170 spin_lock(&domain->lock);
2171
2172 do_detach(dev_data);
2173
2174 spin_unlock(&domain->lock);
2175 }
2176
2177 /*
2178 * Removes a device from a protection domain (with devtable_lock held)
2179 */
2180 static void detach_device(struct device *dev)
2181 {
2182 struct protection_domain *domain;
2183 struct iommu_dev_data *dev_data;
2184 unsigned long flags;
2185
2186 dev_data = get_dev_data(dev);
2187 domain = dev_data->domain;
2188
2189 /*
2190 * First check if the device is still attached. It might already
2191 * be detached from its domain because the generic
2192 * iommu_detach_group code detached it and we try again here in
2193 * our alias handling.
2194 */
2195 if (WARN_ON(!dev_data->domain))
2196 return;
2197
2198 /* lock device table */
2199 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2200 __detach_device(dev_data);
2201 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2202
2203 if (!dev_is_pci(dev))
2204 return;
2205
2206 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2207 pdev_iommuv2_disable(to_pci_dev(dev));
2208 else if (dev_data->ats.enabled)
2209 pci_disable_ats(to_pci_dev(dev));
2210
2211 dev_data->ats.enabled = false;
2212 }
2213
2214 static int amd_iommu_add_device(struct device *dev)
2215 {
2216 struct iommu_dev_data *dev_data;
2217 struct iommu_domain *domain;
2218 struct amd_iommu *iommu;
2219 int ret, devid;
2220
2221 if (!check_device(dev) || get_dev_data(dev))
2222 return 0;
2223
2224 devid = get_device_id(dev);
2225 if (devid < 0)
2226 return devid;
2227
2228 iommu = amd_iommu_rlookup_table[devid];
2229
2230 ret = iommu_init_device(dev);
2231 if (ret) {
2232 if (ret != -ENOTSUPP)
2233 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2234 dev_name(dev));
2235
2236 iommu_ignore_device(dev);
2237 dev->dma_ops = &dma_direct_ops;
2238 goto out;
2239 }
2240 init_iommu_group(dev);
2241
2242 dev_data = get_dev_data(dev);
2243
2244 BUG_ON(!dev_data);
2245
2246 if (iommu_pass_through || dev_data->iommu_v2)
2247 iommu_request_dm_for_dev(dev);
2248
2249 /* Domains are initialized for this device - have a look what we ended up with */
2250 domain = iommu_get_domain_for_dev(dev);
2251 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2252 dev_data->passthrough = true;
2253 else
2254 dev->dma_ops = &amd_iommu_dma_ops;
2255
2256 out:
2257 iommu_completion_wait(iommu);
2258
2259 return 0;
2260 }
2261
2262 static void amd_iommu_remove_device(struct device *dev)
2263 {
2264 struct amd_iommu *iommu;
2265 int devid;
2266
2267 if (!check_device(dev))
2268 return;
2269
2270 devid = get_device_id(dev);
2271 if (devid < 0)
2272 return;
2273
2274 iommu = amd_iommu_rlookup_table[devid];
2275
2276 iommu_uninit_device(dev);
2277 iommu_completion_wait(iommu);
2278 }
2279
2280 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2281 {
2282 if (dev_is_pci(dev))
2283 return pci_device_group(dev);
2284
2285 return acpihid_device_group(dev);
2286 }
2287
2288 /*****************************************************************************
2289 *
2290 * The next functions belong to the dma_ops mapping/unmapping code.
2291 *
2292 *****************************************************************************/
2293
2294 /*
2295 * In the dma_ops path we only have the struct device. This function
2296 * finds the corresponding IOMMU, the protection domain and the
2297 * requestor id for a given device.
2298 * If the device is not yet associated with a domain this is also done
2299 * in this function.
2300 */
2301 static struct protection_domain *get_domain(struct device *dev)
2302 {
2303 struct protection_domain *domain;
2304 struct iommu_domain *io_domain;
2305
2306 if (!check_device(dev))
2307 return ERR_PTR(-EINVAL);
2308
2309 domain = get_dev_data(dev)->domain;
2310 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2311 get_dev_data(dev)->defer_attach = false;
2312 io_domain = iommu_get_domain_for_dev(dev);
2313 domain = to_pdomain(io_domain);
2314 attach_device(dev, domain);
2315 }
2316 if (domain == NULL)
2317 return ERR_PTR(-EBUSY);
2318
2319 if (!dma_ops_domain(domain))
2320 return ERR_PTR(-EBUSY);
2321
2322 return domain;
2323 }
2324
2325 static void update_device_table(struct protection_domain *domain)
2326 {
2327 struct iommu_dev_data *dev_data;
2328
2329 list_for_each_entry(dev_data, &domain->dev_list, list) {
2330 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2331 dev_data->iommu_v2);
2332
2333 if (dev_data->devid == dev_data->alias)
2334 continue;
2335
2336 /* There is an alias, update device table entry for it */
2337 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2338 dev_data->iommu_v2);
2339 }
2340 }
2341
2342 static void update_domain(struct protection_domain *domain)
2343 {
2344 if (!domain->updated)
2345 return;
2346
2347 update_device_table(domain);
2348
2349 domain_flush_devices(domain);
2350 domain_flush_tlb_pde(domain);
2351
2352 domain->updated = false;
2353 }
2354
2355 static int dir2prot(enum dma_data_direction direction)
2356 {
2357 if (direction == DMA_TO_DEVICE)
2358 return IOMMU_PROT_IR;
2359 else if (direction == DMA_FROM_DEVICE)
2360 return IOMMU_PROT_IW;
2361 else if (direction == DMA_BIDIRECTIONAL)
2362 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2363 else
2364 return 0;
2365 }
2366
2367 /*
2368 * This function contains common code for mapping of a physically
2369 * contiguous memory region into DMA address space. It is used by all
2370 * mapping functions provided with this IOMMU driver.
2371 * Must be called with the domain lock held.
2372 */
2373 static dma_addr_t __map_single(struct device *dev,
2374 struct dma_ops_domain *dma_dom,
2375 phys_addr_t paddr,
2376 size_t size,
2377 enum dma_data_direction direction,
2378 u64 dma_mask)
2379 {
2380 dma_addr_t offset = paddr & ~PAGE_MASK;
2381 dma_addr_t address, start, ret;
2382 unsigned int pages;
2383 int prot = 0;
2384 int i;
2385
2386 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2387 paddr &= PAGE_MASK;
2388
2389 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2390 if (address == AMD_IOMMU_MAPPING_ERROR)
2391 goto out;
2392
2393 prot = dir2prot(direction);
2394
2395 start = address;
2396 for (i = 0; i < pages; ++i) {
2397 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2398 PAGE_SIZE, prot, GFP_ATOMIC);
2399 if (ret)
2400 goto out_unmap;
2401
2402 paddr += PAGE_SIZE;
2403 start += PAGE_SIZE;
2404 }
2405 address += offset;
2406
2407 if (unlikely(amd_iommu_np_cache)) {
2408 domain_flush_pages(&dma_dom->domain, address, size);
2409 domain_flush_complete(&dma_dom->domain);
2410 }
2411
2412 out:
2413 return address;
2414
2415 out_unmap:
2416
2417 for (--i; i >= 0; --i) {
2418 start -= PAGE_SIZE;
2419 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2420 }
2421
2422 domain_flush_tlb(&dma_dom->domain);
2423 domain_flush_complete(&dma_dom->domain);
2424
2425 dma_ops_free_iova(dma_dom, address, pages);
2426
2427 return AMD_IOMMU_MAPPING_ERROR;
2428 }
2429
2430 /*
2431 * Does the reverse of the __map_single function. Must be called with
2432 * the domain lock held too
2433 */
2434 static void __unmap_single(struct dma_ops_domain *dma_dom,
2435 dma_addr_t dma_addr,
2436 size_t size,
2437 int dir)
2438 {
2439 dma_addr_t i, start;
2440 unsigned int pages;
2441
2442 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2443 dma_addr &= PAGE_MASK;
2444 start = dma_addr;
2445
2446 for (i = 0; i < pages; ++i) {
2447 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2448 start += PAGE_SIZE;
2449 }
2450
2451 if (amd_iommu_unmap_flush) {
2452 domain_flush_tlb(&dma_dom->domain);
2453 domain_flush_complete(&dma_dom->domain);
2454 dma_ops_free_iova(dma_dom, dma_addr, pages);
2455 } else {
2456 pages = __roundup_pow_of_two(pages);
2457 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2458 }
2459 }
2460
2461 /*
2462 * The exported map_single function for dma_ops.
2463 */
2464 static dma_addr_t map_page(struct device *dev, struct page *page,
2465 unsigned long offset, size_t size,
2466 enum dma_data_direction dir,
2467 unsigned long attrs)
2468 {
2469 phys_addr_t paddr = page_to_phys(page) + offset;
2470 struct protection_domain *domain;
2471 struct dma_ops_domain *dma_dom;
2472 u64 dma_mask;
2473
2474 domain = get_domain(dev);
2475 if (PTR_ERR(domain) == -EINVAL)
2476 return (dma_addr_t)paddr;
2477 else if (IS_ERR(domain))
2478 return AMD_IOMMU_MAPPING_ERROR;
2479
2480 dma_mask = *dev->dma_mask;
2481 dma_dom = to_dma_ops_domain(domain);
2482
2483 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2484 }
2485
2486 /*
2487 * The exported unmap_single function for dma_ops.
2488 */
2489 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2490 enum dma_data_direction dir, unsigned long attrs)
2491 {
2492 struct protection_domain *domain;
2493 struct dma_ops_domain *dma_dom;
2494
2495 domain = get_domain(dev);
2496 if (IS_ERR(domain))
2497 return;
2498
2499 dma_dom = to_dma_ops_domain(domain);
2500
2501 __unmap_single(dma_dom, dma_addr, size, dir);
2502 }
2503
2504 static int sg_num_pages(struct device *dev,
2505 struct scatterlist *sglist,
2506 int nelems)
2507 {
2508 unsigned long mask, boundary_size;
2509 struct scatterlist *s;
2510 int i, npages = 0;
2511
2512 mask = dma_get_seg_boundary(dev);
2513 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2514 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2515
2516 for_each_sg(sglist, s, nelems, i) {
2517 int p, n;
2518
2519 s->dma_address = npages << PAGE_SHIFT;
2520 p = npages % boundary_size;
2521 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2522 if (p + n > boundary_size)
2523 npages += boundary_size - p;
2524 npages += n;
2525 }
2526
2527 return npages;
2528 }
2529
2530 /*
2531 * The exported map_sg function for dma_ops (handles scatter-gather
2532 * lists).
2533 */
2534 static int map_sg(struct device *dev, struct scatterlist *sglist,
2535 int nelems, enum dma_data_direction direction,
2536 unsigned long attrs)
2537 {
2538 int mapped_pages = 0, npages = 0, prot = 0, i;
2539 struct protection_domain *domain;
2540 struct dma_ops_domain *dma_dom;
2541 struct scatterlist *s;
2542 unsigned long address;
2543 u64 dma_mask;
2544
2545 domain = get_domain(dev);
2546 if (IS_ERR(domain))
2547 return 0;
2548
2549 dma_dom = to_dma_ops_domain(domain);
2550 dma_mask = *dev->dma_mask;
2551
2552 npages = sg_num_pages(dev, sglist, nelems);
2553
2554 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2555 if (address == AMD_IOMMU_MAPPING_ERROR)
2556 goto out_err;
2557
2558 prot = dir2prot(direction);
2559
2560 /* Map all sg entries */
2561 for_each_sg(sglist, s, nelems, i) {
2562 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2563
2564 for (j = 0; j < pages; ++j) {
2565 unsigned long bus_addr, phys_addr;
2566 int ret;
2567
2568 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2569 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2570 ret = iommu_map_page(domain, bus_addr, phys_addr,
2571 PAGE_SIZE, prot,
2572 GFP_ATOMIC | __GFP_NOWARN);
2573 if (ret)
2574 goto out_unmap;
2575
2576 mapped_pages += 1;
2577 }
2578 }
2579
2580 /* Everything is mapped - write the right values into s->dma_address */
2581 for_each_sg(sglist, s, nelems, i) {
2582 /*
2583 * Add in the remaining piece of the scatter-gather offset that
2584 * was masked out when we were determining the physical address
2585 * via (sg_phys(s) & PAGE_MASK) earlier.
2586 */
2587 s->dma_address += address + (s->offset & ~PAGE_MASK);
2588 s->dma_length = s->length;
2589 }
2590
2591 return nelems;
2592
2593 out_unmap:
2594 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2595 dev_name(dev), npages);
2596
2597 for_each_sg(sglist, s, nelems, i) {
2598 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2599
2600 for (j = 0; j < pages; ++j) {
2601 unsigned long bus_addr;
2602
2603 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2604 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2605
2606 if (--mapped_pages == 0)
2607 goto out_free_iova;
2608 }
2609 }
2610
2611 out_free_iova:
2612 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2613
2614 out_err:
2615 return 0;
2616 }
2617
2618 /*
2619 * The exported map_sg function for dma_ops (handles scatter-gather
2620 * lists).
2621 */
2622 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2623 int nelems, enum dma_data_direction dir,
2624 unsigned long attrs)
2625 {
2626 struct protection_domain *domain;
2627 struct dma_ops_domain *dma_dom;
2628 unsigned long startaddr;
2629 int npages = 2;
2630
2631 domain = get_domain(dev);
2632 if (IS_ERR(domain))
2633 return;
2634
2635 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2636 dma_dom = to_dma_ops_domain(domain);
2637 npages = sg_num_pages(dev, sglist, nelems);
2638
2639 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2640 }
2641
2642 /*
2643 * The exported alloc_coherent function for dma_ops.
2644 */
2645 static void *alloc_coherent(struct device *dev, size_t size,
2646 dma_addr_t *dma_addr, gfp_t flag,
2647 unsigned long attrs)
2648 {
2649 u64 dma_mask = dev->coherent_dma_mask;
2650 struct protection_domain *domain;
2651 struct dma_ops_domain *dma_dom;
2652 struct page *page;
2653
2654 domain = get_domain(dev);
2655 if (PTR_ERR(domain) == -EINVAL) {
2656 page = alloc_pages(flag, get_order(size));
2657 *dma_addr = page_to_phys(page);
2658 return page_address(page);
2659 } else if (IS_ERR(domain))
2660 return NULL;
2661
2662 dma_dom = to_dma_ops_domain(domain);
2663 size = PAGE_ALIGN(size);
2664 dma_mask = dev->coherent_dma_mask;
2665 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2666 flag |= __GFP_ZERO;
2667
2668 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2669 if (!page) {
2670 if (!gfpflags_allow_blocking(flag))
2671 return NULL;
2672
2673 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2674 get_order(size), flag & __GFP_NOWARN);
2675 if (!page)
2676 return NULL;
2677 }
2678
2679 if (!dma_mask)
2680 dma_mask = *dev->dma_mask;
2681
2682 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2683 size, DMA_BIDIRECTIONAL, dma_mask);
2684
2685 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2686 goto out_free;
2687
2688 return page_address(page);
2689
2690 out_free:
2691
2692 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2693 __free_pages(page, get_order(size));
2694
2695 return NULL;
2696 }
2697
2698 /*
2699 * The exported free_coherent function for dma_ops.
2700 */
2701 static void free_coherent(struct device *dev, size_t size,
2702 void *virt_addr, dma_addr_t dma_addr,
2703 unsigned long attrs)
2704 {
2705 struct protection_domain *domain;
2706 struct dma_ops_domain *dma_dom;
2707 struct page *page;
2708
2709 page = virt_to_page(virt_addr);
2710 size = PAGE_ALIGN(size);
2711
2712 domain = get_domain(dev);
2713 if (IS_ERR(domain))
2714 goto free_mem;
2715
2716 dma_dom = to_dma_ops_domain(domain);
2717
2718 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2719
2720 free_mem:
2721 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2722 __free_pages(page, get_order(size));
2723 }
2724
2725 /*
2726 * This function is called by the DMA layer to find out if we can handle a
2727 * particular device. It is part of the dma_ops.
2728 */
2729 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2730 {
2731 if (!dma_direct_supported(dev, mask))
2732 return 0;
2733 return check_device(dev);
2734 }
2735
2736 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2737 {
2738 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2739 }
2740
2741 static const struct dma_map_ops amd_iommu_dma_ops = {
2742 .alloc = alloc_coherent,
2743 .free = free_coherent,
2744 .map_page = map_page,
2745 .unmap_page = unmap_page,
2746 .map_sg = map_sg,
2747 .unmap_sg = unmap_sg,
2748 .dma_supported = amd_iommu_dma_supported,
2749 .mapping_error = amd_iommu_mapping_error,
2750 };
2751
2752 static int init_reserved_iova_ranges(void)
2753 {
2754 struct pci_dev *pdev = NULL;
2755 struct iova *val;
2756
2757 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2758
2759 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2760 &reserved_rbtree_key);
2761
2762 /* MSI memory range */
2763 val = reserve_iova(&reserved_iova_ranges,
2764 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2765 if (!val) {
2766 pr_err("Reserving MSI range failed\n");
2767 return -ENOMEM;
2768 }
2769
2770 /* HT memory range */
2771 val = reserve_iova(&reserved_iova_ranges,
2772 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2773 if (!val) {
2774 pr_err("Reserving HT range failed\n");
2775 return -ENOMEM;
2776 }
2777
2778 /*
2779 * Memory used for PCI resources
2780 * FIXME: Check whether we can reserve the PCI-hole completly
2781 */
2782 for_each_pci_dev(pdev) {
2783 int i;
2784
2785 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2786 struct resource *r = &pdev->resource[i];
2787
2788 if (!(r->flags & IORESOURCE_MEM))
2789 continue;
2790
2791 val = reserve_iova(&reserved_iova_ranges,
2792 IOVA_PFN(r->start),
2793 IOVA_PFN(r->end));
2794 if (!val) {
2795 pr_err("Reserve pci-resource range failed\n");
2796 return -ENOMEM;
2797 }
2798 }
2799 }
2800
2801 return 0;
2802 }
2803
2804 int __init amd_iommu_init_api(void)
2805 {
2806 int ret, err = 0;
2807
2808 ret = iova_cache_get();
2809 if (ret)
2810 return ret;
2811
2812 ret = init_reserved_iova_ranges();
2813 if (ret)
2814 return ret;
2815
2816 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2817 if (err)
2818 return err;
2819 #ifdef CONFIG_ARM_AMBA
2820 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2821 if (err)
2822 return err;
2823 #endif
2824 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2825 if (err)
2826 return err;
2827
2828 return 0;
2829 }
2830
2831 int __init amd_iommu_init_dma_ops(void)
2832 {
2833 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2834 iommu_detected = 1;
2835
2836 /*
2837 * In case we don't initialize SWIOTLB (actually the common case
2838 * when AMD IOMMU is enabled and SME is not active), make sure there
2839 * are global dma_ops set as a fall-back for devices not handled by
2840 * this driver (for example non-PCI devices). When SME is active,
2841 * make sure that swiotlb variable remains set so the global dma_ops
2842 * continue to be SWIOTLB.
2843 */
2844 if (!swiotlb)
2845 dma_ops = &dma_direct_ops;
2846
2847 if (amd_iommu_unmap_flush)
2848 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2849 else
2850 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2851
2852 return 0;
2853
2854 }
2855
2856 /*****************************************************************************
2857 *
2858 * The following functions belong to the exported interface of AMD IOMMU
2859 *
2860 * This interface allows access to lower level functions of the IOMMU
2861 * like protection domain handling and assignement of devices to domains
2862 * which is not possible with the dma_ops interface.
2863 *
2864 *****************************************************************************/
2865
2866 static void cleanup_domain(struct protection_domain *domain)
2867 {
2868 struct iommu_dev_data *entry;
2869 unsigned long flags;
2870
2871 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2872
2873 while (!list_empty(&domain->dev_list)) {
2874 entry = list_first_entry(&domain->dev_list,
2875 struct iommu_dev_data, list);
2876 BUG_ON(!entry->domain);
2877 __detach_device(entry);
2878 }
2879
2880 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2881 }
2882
2883 static void protection_domain_free(struct protection_domain *domain)
2884 {
2885 if (!domain)
2886 return;
2887
2888 del_domain_from_list(domain);
2889
2890 if (domain->id)
2891 domain_id_free(domain->id);
2892
2893 kfree(domain);
2894 }
2895
2896 static int protection_domain_init(struct protection_domain *domain)
2897 {
2898 spin_lock_init(&domain->lock);
2899 mutex_init(&domain->api_lock);
2900 domain->id = domain_id_alloc();
2901 if (!domain->id)
2902 return -ENOMEM;
2903 INIT_LIST_HEAD(&domain->dev_list);
2904
2905 return 0;
2906 }
2907
2908 static struct protection_domain *protection_domain_alloc(void)
2909 {
2910 struct protection_domain *domain;
2911
2912 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2913 if (!domain)
2914 return NULL;
2915
2916 if (protection_domain_init(domain))
2917 goto out_err;
2918
2919 add_domain_to_list(domain);
2920
2921 return domain;
2922
2923 out_err:
2924 kfree(domain);
2925
2926 return NULL;
2927 }
2928
2929 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2930 {
2931 struct protection_domain *pdomain;
2932 struct dma_ops_domain *dma_domain;
2933
2934 switch (type) {
2935 case IOMMU_DOMAIN_UNMANAGED:
2936 pdomain = protection_domain_alloc();
2937 if (!pdomain)
2938 return NULL;
2939
2940 pdomain->mode = PAGE_MODE_3_LEVEL;
2941 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2942 if (!pdomain->pt_root) {
2943 protection_domain_free(pdomain);
2944 return NULL;
2945 }
2946
2947 pdomain->domain.geometry.aperture_start = 0;
2948 pdomain->domain.geometry.aperture_end = ~0ULL;
2949 pdomain->domain.geometry.force_aperture = true;
2950
2951 break;
2952 case IOMMU_DOMAIN_DMA:
2953 dma_domain = dma_ops_domain_alloc();
2954 if (!dma_domain) {
2955 pr_err("AMD-Vi: Failed to allocate\n");
2956 return NULL;
2957 }
2958 pdomain = &dma_domain->domain;
2959 break;
2960 case IOMMU_DOMAIN_IDENTITY:
2961 pdomain = protection_domain_alloc();
2962 if (!pdomain)
2963 return NULL;
2964
2965 pdomain->mode = PAGE_MODE_NONE;
2966 break;
2967 default:
2968 return NULL;
2969 }
2970
2971 return &pdomain->domain;
2972 }
2973
2974 static void amd_iommu_domain_free(struct iommu_domain *dom)
2975 {
2976 struct protection_domain *domain;
2977 struct dma_ops_domain *dma_dom;
2978
2979 domain = to_pdomain(dom);
2980
2981 if (domain->dev_cnt > 0)
2982 cleanup_domain(domain);
2983
2984 BUG_ON(domain->dev_cnt != 0);
2985
2986 if (!dom)
2987 return;
2988
2989 switch (dom->type) {
2990 case IOMMU_DOMAIN_DMA:
2991 /* Now release the domain */
2992 dma_dom = to_dma_ops_domain(domain);
2993 dma_ops_domain_free(dma_dom);
2994 break;
2995 default:
2996 if (domain->mode != PAGE_MODE_NONE)
2997 free_pagetable(domain);
2998
2999 if (domain->flags & PD_IOMMUV2_MASK)
3000 free_gcr3_table(domain);
3001
3002 protection_domain_free(domain);
3003 break;
3004 }
3005 }
3006
3007 static void amd_iommu_detach_device(struct iommu_domain *dom,
3008 struct device *dev)
3009 {
3010 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3011 struct amd_iommu *iommu;
3012 int devid;
3013
3014 if (!check_device(dev))
3015 return;
3016
3017 devid = get_device_id(dev);
3018 if (devid < 0)
3019 return;
3020
3021 if (dev_data->domain != NULL)
3022 detach_device(dev);
3023
3024 iommu = amd_iommu_rlookup_table[devid];
3025 if (!iommu)
3026 return;
3027
3028 #ifdef CONFIG_IRQ_REMAP
3029 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3030 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3031 dev_data->use_vapic = 0;
3032 #endif
3033
3034 iommu_completion_wait(iommu);
3035 }
3036
3037 static int amd_iommu_attach_device(struct iommu_domain *dom,
3038 struct device *dev)
3039 {
3040 struct protection_domain *domain = to_pdomain(dom);
3041 struct iommu_dev_data *dev_data;
3042 struct amd_iommu *iommu;
3043 int ret;
3044
3045 if (!check_device(dev))
3046 return -EINVAL;
3047
3048 dev_data = dev->archdata.iommu;
3049
3050 iommu = amd_iommu_rlookup_table[dev_data->devid];
3051 if (!iommu)
3052 return -EINVAL;
3053
3054 if (dev_data->domain)
3055 detach_device(dev);
3056
3057 ret = attach_device(dev, domain);
3058
3059 #ifdef CONFIG_IRQ_REMAP
3060 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3061 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3062 dev_data->use_vapic = 1;
3063 else
3064 dev_data->use_vapic = 0;
3065 }
3066 #endif
3067
3068 iommu_completion_wait(iommu);
3069
3070 return ret;
3071 }
3072
3073 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3074 phys_addr_t paddr, size_t page_size, int iommu_prot)
3075 {
3076 struct protection_domain *domain = to_pdomain(dom);
3077 int prot = 0;
3078 int ret;
3079
3080 if (domain->mode == PAGE_MODE_NONE)
3081 return -EINVAL;
3082
3083 if (iommu_prot & IOMMU_READ)
3084 prot |= IOMMU_PROT_IR;
3085 if (iommu_prot & IOMMU_WRITE)
3086 prot |= IOMMU_PROT_IW;
3087
3088 mutex_lock(&domain->api_lock);
3089 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3090 mutex_unlock(&domain->api_lock);
3091
3092 return ret;
3093 }
3094
3095 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3096 size_t page_size)
3097 {
3098 struct protection_domain *domain = to_pdomain(dom);
3099 size_t unmap_size;
3100
3101 if (domain->mode == PAGE_MODE_NONE)
3102 return 0;
3103
3104 mutex_lock(&domain->api_lock);
3105 unmap_size = iommu_unmap_page(domain, iova, page_size);
3106 mutex_unlock(&domain->api_lock);
3107
3108 return unmap_size;
3109 }
3110
3111 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3112 dma_addr_t iova)
3113 {
3114 struct protection_domain *domain = to_pdomain(dom);
3115 unsigned long offset_mask, pte_pgsize;
3116 u64 *pte, __pte;
3117
3118 if (domain->mode == PAGE_MODE_NONE)
3119 return iova;
3120
3121 pte = fetch_pte(domain, iova, &pte_pgsize);
3122
3123 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3124 return 0;
3125
3126 offset_mask = pte_pgsize - 1;
3127 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3128
3129 return (__pte & ~offset_mask) | (iova & offset_mask);
3130 }
3131
3132 static bool amd_iommu_capable(enum iommu_cap cap)
3133 {
3134 switch (cap) {
3135 case IOMMU_CAP_CACHE_COHERENCY:
3136 return true;
3137 case IOMMU_CAP_INTR_REMAP:
3138 return (irq_remapping_enabled == 1);
3139 case IOMMU_CAP_NOEXEC:
3140 return false;
3141 }
3142
3143 return false;
3144 }
3145
3146 static void amd_iommu_get_resv_regions(struct device *dev,
3147 struct list_head *head)
3148 {
3149 struct iommu_resv_region *region;
3150 struct unity_map_entry *entry;
3151 int devid;
3152
3153 devid = get_device_id(dev);
3154 if (devid < 0)
3155 return;
3156
3157 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3158 int type, prot = 0;
3159 size_t length;
3160
3161 if (devid < entry->devid_start || devid > entry->devid_end)
3162 continue;
3163
3164 type = IOMMU_RESV_DIRECT;
3165 length = entry->address_end - entry->address_start;
3166 if (entry->prot & IOMMU_PROT_IR)
3167 prot |= IOMMU_READ;
3168 if (entry->prot & IOMMU_PROT_IW)
3169 prot |= IOMMU_WRITE;
3170 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3171 /* Exclusion range */
3172 type = IOMMU_RESV_RESERVED;
3173
3174 region = iommu_alloc_resv_region(entry->address_start,
3175 length, prot, type);
3176 if (!region) {
3177 pr_err("Out of memory allocating dm-regions for %s\n",
3178 dev_name(dev));
3179 return;
3180 }
3181 list_add_tail(&region->list, head);
3182 }
3183
3184 region = iommu_alloc_resv_region(MSI_RANGE_START,
3185 MSI_RANGE_END - MSI_RANGE_START + 1,
3186 0, IOMMU_RESV_MSI);
3187 if (!region)
3188 return;
3189 list_add_tail(&region->list, head);
3190
3191 region = iommu_alloc_resv_region(HT_RANGE_START,
3192 HT_RANGE_END - HT_RANGE_START + 1,
3193 0, IOMMU_RESV_RESERVED);
3194 if (!region)
3195 return;
3196 list_add_tail(&region->list, head);
3197 }
3198
3199 static void amd_iommu_put_resv_regions(struct device *dev,
3200 struct list_head *head)
3201 {
3202 struct iommu_resv_region *entry, *next;
3203
3204 list_for_each_entry_safe(entry, next, head, list)
3205 kfree(entry);
3206 }
3207
3208 static void amd_iommu_apply_resv_region(struct device *dev,
3209 struct iommu_domain *domain,
3210 struct iommu_resv_region *region)
3211 {
3212 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3213 unsigned long start, end;
3214
3215 start = IOVA_PFN(region->start);
3216 end = IOVA_PFN(region->start + region->length - 1);
3217
3218 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3219 }
3220
3221 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3222 struct device *dev)
3223 {
3224 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3225 return dev_data->defer_attach;
3226 }
3227
3228 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3229 {
3230 struct protection_domain *dom = to_pdomain(domain);
3231
3232 domain_flush_tlb_pde(dom);
3233 domain_flush_complete(dom);
3234 }
3235
3236 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3237 unsigned long iova, size_t size)
3238 {
3239 }
3240
3241 const struct iommu_ops amd_iommu_ops = {
3242 .capable = amd_iommu_capable,
3243 .domain_alloc = amd_iommu_domain_alloc,
3244 .domain_free = amd_iommu_domain_free,
3245 .attach_dev = amd_iommu_attach_device,
3246 .detach_dev = amd_iommu_detach_device,
3247 .map = amd_iommu_map,
3248 .unmap = amd_iommu_unmap,
3249 .iova_to_phys = amd_iommu_iova_to_phys,
3250 .add_device = amd_iommu_add_device,
3251 .remove_device = amd_iommu_remove_device,
3252 .device_group = amd_iommu_device_group,
3253 .get_resv_regions = amd_iommu_get_resv_regions,
3254 .put_resv_regions = amd_iommu_put_resv_regions,
3255 .apply_resv_region = amd_iommu_apply_resv_region,
3256 .is_attach_deferred = amd_iommu_is_attach_deferred,
3257 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3258 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3259 .iotlb_range_add = amd_iommu_iotlb_range_add,
3260 .iotlb_sync = amd_iommu_flush_iotlb_all,
3261 };
3262
3263 /*****************************************************************************
3264 *
3265 * The next functions do a basic initialization of IOMMU for pass through
3266 * mode
3267 *
3268 * In passthrough mode the IOMMU is initialized and enabled but not used for
3269 * DMA-API translation.
3270 *
3271 *****************************************************************************/
3272
3273 /* IOMMUv2 specific functions */
3274 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3275 {
3276 return atomic_notifier_chain_register(&ppr_notifier, nb);
3277 }
3278 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3279
3280 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3281 {
3282 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3283 }
3284 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3285
3286 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3287 {
3288 struct protection_domain *domain = to_pdomain(dom);
3289 unsigned long flags;
3290
3291 spin_lock_irqsave(&domain->lock, flags);
3292
3293 /* Update data structure */
3294 domain->mode = PAGE_MODE_NONE;
3295 domain->updated = true;
3296
3297 /* Make changes visible to IOMMUs */
3298 update_domain(domain);
3299
3300 /* Page-table is not visible to IOMMU anymore, so free it */
3301 free_pagetable(domain);
3302
3303 spin_unlock_irqrestore(&domain->lock, flags);
3304 }
3305 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3306
3307 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3308 {
3309 struct protection_domain *domain = to_pdomain(dom);
3310 unsigned long flags;
3311 int levels, ret;
3312
3313 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3314 return -EINVAL;
3315
3316 /* Number of GCR3 table levels required */
3317 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3318 levels += 1;
3319
3320 if (levels > amd_iommu_max_glx_val)
3321 return -EINVAL;
3322
3323 spin_lock_irqsave(&domain->lock, flags);
3324
3325 /*
3326 * Save us all sanity checks whether devices already in the
3327 * domain support IOMMUv2. Just force that the domain has no
3328 * devices attached when it is switched into IOMMUv2 mode.
3329 */
3330 ret = -EBUSY;
3331 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3332 goto out;
3333
3334 ret = -ENOMEM;
3335 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3336 if (domain->gcr3_tbl == NULL)
3337 goto out;
3338
3339 domain->glx = levels;
3340 domain->flags |= PD_IOMMUV2_MASK;
3341 domain->updated = true;
3342
3343 update_domain(domain);
3344
3345 ret = 0;
3346
3347 out:
3348 spin_unlock_irqrestore(&domain->lock, flags);
3349
3350 return ret;
3351 }
3352 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3353
3354 static int __flush_pasid(struct protection_domain *domain, int pasid,
3355 u64 address, bool size)
3356 {
3357 struct iommu_dev_data *dev_data;
3358 struct iommu_cmd cmd;
3359 int i, ret;
3360
3361 if (!(domain->flags & PD_IOMMUV2_MASK))
3362 return -EINVAL;
3363
3364 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3365
3366 /*
3367 * IOMMU TLB needs to be flushed before Device TLB to
3368 * prevent device TLB refill from IOMMU TLB
3369 */
3370 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3371 if (domain->dev_iommu[i] == 0)
3372 continue;
3373
3374 ret = iommu_queue_command(amd_iommus[i], &cmd);
3375 if (ret != 0)
3376 goto out;
3377 }
3378
3379 /* Wait until IOMMU TLB flushes are complete */
3380 domain_flush_complete(domain);
3381
3382 /* Now flush device TLBs */
3383 list_for_each_entry(dev_data, &domain->dev_list, list) {
3384 struct amd_iommu *iommu;
3385 int qdep;
3386
3387 /*
3388 There might be non-IOMMUv2 capable devices in an IOMMUv2
3389 * domain.
3390 */
3391 if (!dev_data->ats.enabled)
3392 continue;
3393
3394 qdep = dev_data->ats.qdep;
3395 iommu = amd_iommu_rlookup_table[dev_data->devid];
3396
3397 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3398 qdep, address, size);
3399
3400 ret = iommu_queue_command(iommu, &cmd);
3401 if (ret != 0)
3402 goto out;
3403 }
3404
3405 /* Wait until all device TLBs are flushed */
3406 domain_flush_complete(domain);
3407
3408 ret = 0;
3409
3410 out:
3411
3412 return ret;
3413 }
3414
3415 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3416 u64 address)
3417 {
3418 return __flush_pasid(domain, pasid, address, false);
3419 }
3420
3421 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3422 u64 address)
3423 {
3424 struct protection_domain *domain = to_pdomain(dom);
3425 unsigned long flags;
3426 int ret;
3427
3428 spin_lock_irqsave(&domain->lock, flags);
3429 ret = __amd_iommu_flush_page(domain, pasid, address);
3430 spin_unlock_irqrestore(&domain->lock, flags);
3431
3432 return ret;
3433 }
3434 EXPORT_SYMBOL(amd_iommu_flush_page);
3435
3436 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3437 {
3438 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3439 true);
3440 }
3441
3442 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3443 {
3444 struct protection_domain *domain = to_pdomain(dom);
3445 unsigned long flags;
3446 int ret;
3447
3448 spin_lock_irqsave(&domain->lock, flags);
3449 ret = __amd_iommu_flush_tlb(domain, pasid);
3450 spin_unlock_irqrestore(&domain->lock, flags);
3451
3452 return ret;
3453 }
3454 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3455
3456 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3457 {
3458 int index;
3459 u64 *pte;
3460
3461 while (true) {
3462
3463 index = (pasid >> (9 * level)) & 0x1ff;
3464 pte = &root[index];
3465
3466 if (level == 0)
3467 break;
3468
3469 if (!(*pte & GCR3_VALID)) {
3470 if (!alloc)
3471 return NULL;
3472
3473 root = (void *)get_zeroed_page(GFP_ATOMIC);
3474 if (root == NULL)
3475 return NULL;
3476
3477 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3478 }
3479
3480 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3481
3482 level -= 1;
3483 }
3484
3485 return pte;
3486 }
3487
3488 static int __set_gcr3(struct protection_domain *domain, int pasid,
3489 unsigned long cr3)
3490 {
3491 u64 *pte;
3492
3493 if (domain->mode != PAGE_MODE_NONE)
3494 return -EINVAL;
3495
3496 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3497 if (pte == NULL)
3498 return -ENOMEM;
3499
3500 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3501
3502 return __amd_iommu_flush_tlb(domain, pasid);
3503 }
3504
3505 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3506 {
3507 u64 *pte;
3508
3509 if (domain->mode != PAGE_MODE_NONE)
3510 return -EINVAL;
3511
3512 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3513 if (pte == NULL)
3514 return 0;
3515
3516 *pte = 0;
3517
3518 return __amd_iommu_flush_tlb(domain, pasid);
3519 }
3520
3521 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3522 unsigned long cr3)
3523 {
3524 struct protection_domain *domain = to_pdomain(dom);
3525 unsigned long flags;
3526 int ret;
3527
3528 spin_lock_irqsave(&domain->lock, flags);
3529 ret = __set_gcr3(domain, pasid, cr3);
3530 spin_unlock_irqrestore(&domain->lock, flags);
3531
3532 return ret;
3533 }
3534 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3535
3536 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3537 {
3538 struct protection_domain *domain = to_pdomain(dom);
3539 unsigned long flags;
3540 int ret;
3541
3542 spin_lock_irqsave(&domain->lock, flags);
3543 ret = __clear_gcr3(domain, pasid);
3544 spin_unlock_irqrestore(&domain->lock, flags);
3545
3546 return ret;
3547 }
3548 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3549
3550 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3551 int status, int tag)
3552 {
3553 struct iommu_dev_data *dev_data;
3554 struct amd_iommu *iommu;
3555 struct iommu_cmd cmd;
3556
3557 dev_data = get_dev_data(&pdev->dev);
3558 iommu = amd_iommu_rlookup_table[dev_data->devid];
3559
3560 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3561 tag, dev_data->pri_tlp);
3562
3563 return iommu_queue_command(iommu, &cmd);
3564 }
3565 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3566
3567 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3568 {
3569 struct protection_domain *pdomain;
3570
3571 pdomain = get_domain(&pdev->dev);
3572 if (IS_ERR(pdomain))
3573 return NULL;
3574
3575 /* Only return IOMMUv2 domains */
3576 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3577 return NULL;
3578
3579 return &pdomain->domain;
3580 }
3581 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3582
3583 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3584 {
3585 struct iommu_dev_data *dev_data;
3586
3587 if (!amd_iommu_v2_supported())
3588 return;
3589
3590 dev_data = get_dev_data(&pdev->dev);
3591 dev_data->errata |= (1 << erratum);
3592 }
3593 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3594
3595 int amd_iommu_device_info(struct pci_dev *pdev,
3596 struct amd_iommu_device_info *info)
3597 {
3598 int max_pasids;
3599 int pos;
3600
3601 if (pdev == NULL || info == NULL)
3602 return -EINVAL;
3603
3604 if (!amd_iommu_v2_supported())
3605 return -EINVAL;
3606
3607 memset(info, 0, sizeof(*info));
3608
3609 if (!pci_ats_disabled()) {
3610 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3611 if (pos)
3612 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3613 }
3614
3615 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3616 if (pos)
3617 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3618
3619 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3620 if (pos) {
3621 int features;
3622
3623 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3624 max_pasids = min(max_pasids, (1 << 20));
3625
3626 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3627 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3628
3629 features = pci_pasid_features(pdev);
3630 if (features & PCI_PASID_CAP_EXEC)
3631 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3632 if (features & PCI_PASID_CAP_PRIV)
3633 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3634 }
3635
3636 return 0;
3637 }
3638 EXPORT_SYMBOL(amd_iommu_device_info);
3639
3640 #ifdef CONFIG_IRQ_REMAP
3641
3642 /*****************************************************************************
3643 *
3644 * Interrupt Remapping Implementation
3645 *
3646 *****************************************************************************/
3647
3648 static struct irq_chip amd_ir_chip;
3649 static DEFINE_SPINLOCK(iommu_table_lock);
3650
3651 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3652 {
3653 u64 dte;
3654
3655 dte = amd_iommu_dev_table[devid].data[2];
3656 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3657 dte |= iommu_virt_to_phys(table->table);
3658 dte |= DTE_IRQ_REMAP_INTCTL;
3659 dte |= DTE_IRQ_TABLE_LEN;
3660 dte |= DTE_IRQ_REMAP_ENABLE;
3661
3662 amd_iommu_dev_table[devid].data[2] = dte;
3663 }
3664
3665 static struct irq_remap_table *get_irq_table(u16 devid)
3666 {
3667 struct irq_remap_table *table;
3668
3669 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3670 "%s: no iommu for devid %x\n", __func__, devid))
3671 return NULL;
3672
3673 table = irq_lookup_table[devid];
3674 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3675 return NULL;
3676
3677 return table;
3678 }
3679
3680 static struct irq_remap_table *__alloc_irq_table(void)
3681 {
3682 struct irq_remap_table *table;
3683
3684 table = kzalloc(sizeof(*table), GFP_KERNEL);
3685 if (!table)
3686 return NULL;
3687
3688 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3689 if (!table->table) {
3690 kfree(table);
3691 return NULL;
3692 }
3693 raw_spin_lock_init(&table->lock);
3694
3695 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3696 memset(table->table, 0,
3697 MAX_IRQS_PER_TABLE * sizeof(u32));
3698 else
3699 memset(table->table, 0,
3700 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3701 return table;
3702 }
3703
3704 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3705 struct irq_remap_table *table)
3706 {
3707 irq_lookup_table[devid] = table;
3708 set_dte_irq_entry(devid, table);
3709 iommu_flush_dte(iommu, devid);
3710 }
3711
3712 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3713 void *data)
3714 {
3715 struct irq_remap_table *table = data;
3716
3717 irq_lookup_table[alias] = table;
3718 set_dte_irq_entry(alias, table);
3719
3720 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3721
3722 return 0;
3723 }
3724
3725 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3726 {
3727 struct irq_remap_table *table = NULL;
3728 struct irq_remap_table *new_table = NULL;
3729 struct amd_iommu *iommu;
3730 unsigned long flags;
3731 u16 alias;
3732
3733 spin_lock_irqsave(&iommu_table_lock, flags);
3734
3735 iommu = amd_iommu_rlookup_table[devid];
3736 if (!iommu)
3737 goto out_unlock;
3738
3739 table = irq_lookup_table[devid];
3740 if (table)
3741 goto out_unlock;
3742
3743 alias = amd_iommu_alias_table[devid];
3744 table = irq_lookup_table[alias];
3745 if (table) {
3746 set_remap_table_entry(iommu, devid, table);
3747 goto out_wait;
3748 }
3749 spin_unlock_irqrestore(&iommu_table_lock, flags);
3750
3751 /* Nothing there yet, allocate new irq remapping table */
3752 new_table = __alloc_irq_table();
3753 if (!new_table)
3754 return NULL;
3755
3756 spin_lock_irqsave(&iommu_table_lock, flags);
3757
3758 table = irq_lookup_table[devid];
3759 if (table)
3760 goto out_unlock;
3761
3762 table = irq_lookup_table[alias];
3763 if (table) {
3764 set_remap_table_entry(iommu, devid, table);
3765 goto out_wait;
3766 }
3767
3768 table = new_table;
3769 new_table = NULL;
3770
3771 if (pdev)
3772 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3773 table);
3774 else
3775 set_remap_table_entry(iommu, devid, table);
3776
3777 if (devid != alias)
3778 set_remap_table_entry(iommu, alias, table);
3779
3780 out_wait:
3781 iommu_completion_wait(iommu);
3782
3783 out_unlock:
3784 spin_unlock_irqrestore(&iommu_table_lock, flags);
3785
3786 if (new_table) {
3787 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3788 kfree(new_table);
3789 }
3790 return table;
3791 }
3792
3793 static int alloc_irq_index(u16 devid, int count, bool align,
3794 struct pci_dev *pdev)
3795 {
3796 struct irq_remap_table *table;
3797 int index, c, alignment = 1;
3798 unsigned long flags;
3799 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3800
3801 if (!iommu)
3802 return -ENODEV;
3803
3804 table = alloc_irq_table(devid, pdev);
3805 if (!table)
3806 return -ENODEV;
3807
3808 if (align)
3809 alignment = roundup_pow_of_two(count);
3810
3811 raw_spin_lock_irqsave(&table->lock, flags);
3812
3813 /* Scan table for free entries */
3814 for (index = ALIGN(table->min_index, alignment), c = 0;
3815 index < MAX_IRQS_PER_TABLE;) {
3816 if (!iommu->irte_ops->is_allocated(table, index)) {
3817 c += 1;
3818 } else {
3819 c = 0;
3820 index = ALIGN(index + 1, alignment);
3821 continue;
3822 }
3823
3824 if (c == count) {
3825 for (; c != 0; --c)
3826 iommu->irte_ops->set_allocated(table, index - c + 1);
3827
3828 index -= count - 1;
3829 goto out;
3830 }
3831
3832 index++;
3833 }
3834
3835 index = -ENOSPC;
3836
3837 out:
3838 raw_spin_unlock_irqrestore(&table->lock, flags);
3839
3840 return index;
3841 }
3842
3843 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3844 struct amd_ir_data *data)
3845 {
3846 struct irq_remap_table *table;
3847 struct amd_iommu *iommu;
3848 unsigned long flags;
3849 struct irte_ga *entry;
3850
3851 iommu = amd_iommu_rlookup_table[devid];
3852 if (iommu == NULL)
3853 return -EINVAL;
3854
3855 table = get_irq_table(devid);
3856 if (!table)
3857 return -ENOMEM;
3858
3859 raw_spin_lock_irqsave(&table->lock, flags);
3860
3861 entry = (struct irte_ga *)table->table;
3862 entry = &entry[index];
3863 entry->lo.fields_remap.valid = 0;
3864 entry->hi.val = irte->hi.val;
3865 entry->lo.val = irte->lo.val;
3866 entry->lo.fields_remap.valid = 1;
3867 if (data)
3868 data->ref = entry;
3869
3870 raw_spin_unlock_irqrestore(&table->lock, flags);
3871
3872 iommu_flush_irt(iommu, devid);
3873 iommu_completion_wait(iommu);
3874
3875 return 0;
3876 }
3877
3878 static int modify_irte(u16 devid, int index, union irte *irte)
3879 {
3880 struct irq_remap_table *table;
3881 struct amd_iommu *iommu;
3882 unsigned long flags;
3883
3884 iommu = amd_iommu_rlookup_table[devid];
3885 if (iommu == NULL)
3886 return -EINVAL;
3887
3888 table = get_irq_table(devid);
3889 if (!table)
3890 return -ENOMEM;
3891
3892 raw_spin_lock_irqsave(&table->lock, flags);
3893 table->table[index] = irte->val;
3894 raw_spin_unlock_irqrestore(&table->lock, flags);
3895
3896 iommu_flush_irt(iommu, devid);
3897 iommu_completion_wait(iommu);
3898
3899 return 0;
3900 }
3901
3902 static void free_irte(u16 devid, int index)
3903 {
3904 struct irq_remap_table *table;
3905 struct amd_iommu *iommu;
3906 unsigned long flags;
3907
3908 iommu = amd_iommu_rlookup_table[devid];
3909 if (iommu == NULL)
3910 return;
3911
3912 table = get_irq_table(devid);
3913 if (!table)
3914 return;
3915
3916 raw_spin_lock_irqsave(&table->lock, flags);
3917 iommu->irte_ops->clear_allocated(table, index);
3918 raw_spin_unlock_irqrestore(&table->lock, flags);
3919
3920 iommu_flush_irt(iommu, devid);
3921 iommu_completion_wait(iommu);
3922 }
3923
3924 static void irte_prepare(void *entry,
3925 u32 delivery_mode, u32 dest_mode,
3926 u8 vector, u32 dest_apicid, int devid)
3927 {
3928 union irte *irte = (union irte *) entry;
3929
3930 irte->val = 0;
3931 irte->fields.vector = vector;
3932 irte->fields.int_type = delivery_mode;
3933 irte->fields.destination = dest_apicid;
3934 irte->fields.dm = dest_mode;
3935 irte->fields.valid = 1;
3936 }
3937
3938 static void irte_ga_prepare(void *entry,
3939 u32 delivery_mode, u32 dest_mode,
3940 u8 vector, u32 dest_apicid, int devid)
3941 {
3942 struct irte_ga *irte = (struct irte_ga *) entry;
3943
3944 irte->lo.val = 0;
3945 irte->hi.val = 0;
3946 irte->lo.fields_remap.int_type = delivery_mode;
3947 irte->lo.fields_remap.dm = dest_mode;
3948 irte->hi.fields.vector = vector;
3949 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3950 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3951 irte->lo.fields_remap.valid = 1;
3952 }
3953
3954 static void irte_activate(void *entry, u16 devid, u16 index)
3955 {
3956 union irte *irte = (union irte *) entry;
3957
3958 irte->fields.valid = 1;
3959 modify_irte(devid, index, irte);
3960 }
3961
3962 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3963 {
3964 struct irte_ga *irte = (struct irte_ga *) entry;
3965
3966 irte->lo.fields_remap.valid = 1;
3967 modify_irte_ga(devid, index, irte, NULL);
3968 }
3969
3970 static void irte_deactivate(void *entry, u16 devid, u16 index)
3971 {
3972 union irte *irte = (union irte *) entry;
3973
3974 irte->fields.valid = 0;
3975 modify_irte(devid, index, irte);
3976 }
3977
3978 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3979 {
3980 struct irte_ga *irte = (struct irte_ga *) entry;
3981
3982 irte->lo.fields_remap.valid = 0;
3983 modify_irte_ga(devid, index, irte, NULL);
3984 }
3985
3986 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3987 u8 vector, u32 dest_apicid)
3988 {
3989 union irte *irte = (union irte *) entry;
3990
3991 irte->fields.vector = vector;
3992 irte->fields.destination = dest_apicid;
3993 modify_irte(devid, index, irte);
3994 }
3995
3996 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3997 u8 vector, u32 dest_apicid)
3998 {
3999 struct irte_ga *irte = (struct irte_ga *) entry;
4000
4001 if (!irte->lo.fields_remap.guest_mode) {
4002 irte->hi.fields.vector = vector;
4003 irte->lo.fields_remap.destination =
4004 APICID_TO_IRTE_DEST_LO(dest_apicid);
4005 irte->hi.fields.destination =
4006 APICID_TO_IRTE_DEST_HI(dest_apicid);
4007 modify_irte_ga(devid, index, irte, NULL);
4008 }
4009 }
4010
4011 #define IRTE_ALLOCATED (~1U)
4012 static void irte_set_allocated(struct irq_remap_table *table, int index)
4013 {
4014 table->table[index] = IRTE_ALLOCATED;
4015 }
4016
4017 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4018 {
4019 struct irte_ga *ptr = (struct irte_ga *)table->table;
4020 struct irte_ga *irte = &ptr[index];
4021
4022 memset(&irte->lo.val, 0, sizeof(u64));
4023 memset(&irte->hi.val, 0, sizeof(u64));
4024 irte->hi.fields.vector = 0xff;
4025 }
4026
4027 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4028 {
4029 union irte *ptr = (union irte *)table->table;
4030 union irte *irte = &ptr[index];
4031
4032 return irte->val != 0;
4033 }
4034
4035 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4036 {
4037 struct irte_ga *ptr = (struct irte_ga *)table->table;
4038 struct irte_ga *irte = &ptr[index];
4039
4040 return irte->hi.fields.vector != 0;
4041 }
4042
4043 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4044 {
4045 table->table[index] = 0;
4046 }
4047
4048 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4049 {
4050 struct irte_ga *ptr = (struct irte_ga *)table->table;
4051 struct irte_ga *irte = &ptr[index];
4052
4053 memset(&irte->lo.val, 0, sizeof(u64));
4054 memset(&irte->hi.val, 0, sizeof(u64));
4055 }
4056
4057 static int get_devid(struct irq_alloc_info *info)
4058 {
4059 int devid = -1;
4060
4061 switch (info->type) {
4062 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4063 devid = get_ioapic_devid(info->ioapic_id);
4064 break;
4065 case X86_IRQ_ALLOC_TYPE_HPET:
4066 devid = get_hpet_devid(info->hpet_id);
4067 break;
4068 case X86_IRQ_ALLOC_TYPE_MSI:
4069 case X86_IRQ_ALLOC_TYPE_MSIX:
4070 devid = get_device_id(&info->msi_dev->dev);
4071 break;
4072 default:
4073 BUG_ON(1);
4074 break;
4075 }
4076
4077 return devid;
4078 }
4079
4080 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4081 {
4082 struct amd_iommu *iommu;
4083 int devid;
4084
4085 if (!info)
4086 return NULL;
4087
4088 devid = get_devid(info);
4089 if (devid >= 0) {
4090 iommu = amd_iommu_rlookup_table[devid];
4091 if (iommu)
4092 return iommu->ir_domain;
4093 }
4094
4095 return NULL;
4096 }
4097
4098 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4099 {
4100 struct amd_iommu *iommu;
4101 int devid;
4102
4103 if (!info)
4104 return NULL;
4105
4106 switch (info->type) {
4107 case X86_IRQ_ALLOC_TYPE_MSI:
4108 case X86_IRQ_ALLOC_TYPE_MSIX:
4109 devid = get_device_id(&info->msi_dev->dev);
4110 if (devid < 0)
4111 return NULL;
4112
4113 iommu = amd_iommu_rlookup_table[devid];
4114 if (iommu)
4115 return iommu->msi_domain;
4116 break;
4117 default:
4118 break;
4119 }
4120
4121 return NULL;
4122 }
4123
4124 struct irq_remap_ops amd_iommu_irq_ops = {
4125 .prepare = amd_iommu_prepare,
4126 .enable = amd_iommu_enable,
4127 .disable = amd_iommu_disable,
4128 .reenable = amd_iommu_reenable,
4129 .enable_faulting = amd_iommu_enable_faulting,
4130 .get_ir_irq_domain = get_ir_irq_domain,
4131 .get_irq_domain = get_irq_domain,
4132 };
4133
4134 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4135 struct irq_cfg *irq_cfg,
4136 struct irq_alloc_info *info,
4137 int devid, int index, int sub_handle)
4138 {
4139 struct irq_2_irte *irte_info = &data->irq_2_irte;
4140 struct msi_msg *msg = &data->msi_entry;
4141 struct IO_APIC_route_entry *entry;
4142 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4143
4144 if (!iommu)
4145 return;
4146
4147 data->irq_2_irte.devid = devid;
4148 data->irq_2_irte.index = index + sub_handle;
4149 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4150 apic->irq_dest_mode, irq_cfg->vector,
4151 irq_cfg->dest_apicid, devid);
4152
4153 switch (info->type) {
4154 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4155 /* Setup IOAPIC entry */
4156 entry = info->ioapic_entry;
4157 info->ioapic_entry = NULL;
4158 memset(entry, 0, sizeof(*entry));
4159 entry->vector = index;
4160 entry->mask = 0;
4161 entry->trigger = info->ioapic_trigger;
4162 entry->polarity = info->ioapic_polarity;
4163 /* Mask level triggered irqs. */
4164 if (info->ioapic_trigger)
4165 entry->mask = 1;
4166 break;
4167
4168 case X86_IRQ_ALLOC_TYPE_HPET:
4169 case X86_IRQ_ALLOC_TYPE_MSI:
4170 case X86_IRQ_ALLOC_TYPE_MSIX:
4171 msg->address_hi = MSI_ADDR_BASE_HI;
4172 msg->address_lo = MSI_ADDR_BASE_LO;
4173 msg->data = irte_info->index;
4174 break;
4175
4176 default:
4177 BUG_ON(1);
4178 break;
4179 }
4180 }
4181
4182 struct amd_irte_ops irte_32_ops = {
4183 .prepare = irte_prepare,
4184 .activate = irte_activate,
4185 .deactivate = irte_deactivate,
4186 .set_affinity = irte_set_affinity,
4187 .set_allocated = irte_set_allocated,
4188 .is_allocated = irte_is_allocated,
4189 .clear_allocated = irte_clear_allocated,
4190 };
4191
4192 struct amd_irte_ops irte_128_ops = {
4193 .prepare = irte_ga_prepare,
4194 .activate = irte_ga_activate,
4195 .deactivate = irte_ga_deactivate,
4196 .set_affinity = irte_ga_set_affinity,
4197 .set_allocated = irte_ga_set_allocated,
4198 .is_allocated = irte_ga_is_allocated,
4199 .clear_allocated = irte_ga_clear_allocated,
4200 };
4201
4202 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4203 unsigned int nr_irqs, void *arg)
4204 {
4205 struct irq_alloc_info *info = arg;
4206 struct irq_data *irq_data;
4207 struct amd_ir_data *data = NULL;
4208 struct irq_cfg *cfg;
4209 int i, ret, devid;
4210 int index;
4211
4212 if (!info)
4213 return -EINVAL;
4214 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4215 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4216 return -EINVAL;
4217
4218 /*
4219 * With IRQ remapping enabled, don't need contiguous CPU vectors
4220 * to support multiple MSI interrupts.
4221 */
4222 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4223 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4224
4225 devid = get_devid(info);
4226 if (devid < 0)
4227 return -EINVAL;
4228
4229 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4230 if (ret < 0)
4231 return ret;
4232
4233 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4234 struct irq_remap_table *table;
4235 struct amd_iommu *iommu;
4236
4237 table = alloc_irq_table(devid, NULL);
4238 if (table) {
4239 if (!table->min_index) {
4240 /*
4241 * Keep the first 32 indexes free for IOAPIC
4242 * interrupts.
4243 */
4244 table->min_index = 32;
4245 iommu = amd_iommu_rlookup_table[devid];
4246 for (i = 0; i < 32; ++i)
4247 iommu->irte_ops->set_allocated(table, i);
4248 }
4249 WARN_ON(table->min_index != 32);
4250 index = info->ioapic_pin;
4251 } else {
4252 index = -ENOMEM;
4253 }
4254 } else if (info->type == X86_IRQ_ALLOC_TYPE_MSI ||
4255 info->type == X86_IRQ_ALLOC_TYPE_MSIX) {
4256 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4257
4258 index = alloc_irq_index(devid, nr_irqs, align, info->msi_dev);
4259 } else {
4260 index = alloc_irq_index(devid, nr_irqs, false, NULL);
4261 }
4262
4263 if (index < 0) {
4264 pr_warn("Failed to allocate IRTE\n");
4265 ret = index;
4266 goto out_free_parent;
4267 }
4268
4269 for (i = 0; i < nr_irqs; i++) {
4270 irq_data = irq_domain_get_irq_data(domain, virq + i);
4271 cfg = irqd_cfg(irq_data);
4272 if (!irq_data || !cfg) {
4273 ret = -EINVAL;
4274 goto out_free_data;
4275 }
4276
4277 ret = -ENOMEM;
4278 data = kzalloc(sizeof(*data), GFP_KERNEL);
4279 if (!data)
4280 goto out_free_data;
4281
4282 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4283 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4284 else
4285 data->entry = kzalloc(sizeof(struct irte_ga),
4286 GFP_KERNEL);
4287 if (!data->entry) {
4288 kfree(data);
4289 goto out_free_data;
4290 }
4291
4292 irq_data->hwirq = (devid << 16) + i;
4293 irq_data->chip_data = data;
4294 irq_data->chip = &amd_ir_chip;
4295 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4296 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4297 }
4298
4299 return 0;
4300
4301 out_free_data:
4302 for (i--; i >= 0; i--) {
4303 irq_data = irq_domain_get_irq_data(domain, virq + i);
4304 if (irq_data)
4305 kfree(irq_data->chip_data);
4306 }
4307 for (i = 0; i < nr_irqs; i++)
4308 free_irte(devid, index + i);
4309 out_free_parent:
4310 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4311 return ret;
4312 }
4313
4314 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4315 unsigned int nr_irqs)
4316 {
4317 struct irq_2_irte *irte_info;
4318 struct irq_data *irq_data;
4319 struct amd_ir_data *data;
4320 int i;
4321
4322 for (i = 0; i < nr_irqs; i++) {
4323 irq_data = irq_domain_get_irq_data(domain, virq + i);
4324 if (irq_data && irq_data->chip_data) {
4325 data = irq_data->chip_data;
4326 irte_info = &data->irq_2_irte;
4327 free_irte(irte_info->devid, irte_info->index);
4328 kfree(data->entry);
4329 kfree(data);
4330 }
4331 }
4332 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4333 }
4334
4335 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4336 struct amd_ir_data *ir_data,
4337 struct irq_2_irte *irte_info,
4338 struct irq_cfg *cfg);
4339
4340 static int irq_remapping_activate(struct irq_domain *domain,
4341 struct irq_data *irq_data, bool reserve)
4342 {
4343 struct amd_ir_data *data = irq_data->chip_data;
4344 struct irq_2_irte *irte_info = &data->irq_2_irte;
4345 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4346 struct irq_cfg *cfg = irqd_cfg(irq_data);
4347
4348 if (!iommu)
4349 return 0;
4350
4351 iommu->irte_ops->activate(data->entry, irte_info->devid,
4352 irte_info->index);
4353 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4354 return 0;
4355 }
4356
4357 static void irq_remapping_deactivate(struct irq_domain *domain,
4358 struct irq_data *irq_data)
4359 {
4360 struct amd_ir_data *data = irq_data->chip_data;
4361 struct irq_2_irte *irte_info = &data->irq_2_irte;
4362 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4363
4364 if (iommu)
4365 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4366 irte_info->index);
4367 }
4368
4369 static const struct irq_domain_ops amd_ir_domain_ops = {
4370 .alloc = irq_remapping_alloc,
4371 .free = irq_remapping_free,
4372 .activate = irq_remapping_activate,
4373 .deactivate = irq_remapping_deactivate,
4374 };
4375
4376 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4377 {
4378 struct amd_iommu *iommu;
4379 struct amd_iommu_pi_data *pi_data = vcpu_info;
4380 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4381 struct amd_ir_data *ir_data = data->chip_data;
4382 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4383 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4384 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4385
4386 /* Note:
4387 * This device has never been set up for guest mode.
4388 * we should not modify the IRTE
4389 */
4390 if (!dev_data || !dev_data->use_vapic)
4391 return 0;
4392
4393 pi_data->ir_data = ir_data;
4394
4395 /* Note:
4396 * SVM tries to set up for VAPIC mode, but we are in
4397 * legacy mode. So, we force legacy mode instead.
4398 */
4399 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4400 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4401 __func__);
4402 pi_data->is_guest_mode = false;
4403 }
4404
4405 iommu = amd_iommu_rlookup_table[irte_info->devid];
4406 if (iommu == NULL)
4407 return -EINVAL;
4408
4409 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4410 if (pi_data->is_guest_mode) {
4411 /* Setting */
4412 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4413 irte->hi.fields.vector = vcpu_pi_info->vector;
4414 irte->lo.fields_vapic.ga_log_intr = 1;
4415 irte->lo.fields_vapic.guest_mode = 1;
4416 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4417
4418 ir_data->cached_ga_tag = pi_data->ga_tag;
4419 } else {
4420 /* Un-Setting */
4421 struct irq_cfg *cfg = irqd_cfg(data);
4422
4423 irte->hi.val = 0;
4424 irte->lo.val = 0;
4425 irte->hi.fields.vector = cfg->vector;
4426 irte->lo.fields_remap.guest_mode = 0;
4427 irte->lo.fields_remap.destination =
4428 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4429 irte->hi.fields.destination =
4430 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4431 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4432 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4433
4434 /*
4435 * This communicates the ga_tag back to the caller
4436 * so that it can do all the necessary clean up.
4437 */
4438 ir_data->cached_ga_tag = 0;
4439 }
4440
4441 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4442 }
4443
4444
4445 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4446 struct amd_ir_data *ir_data,
4447 struct irq_2_irte *irte_info,
4448 struct irq_cfg *cfg)
4449 {
4450
4451 /*
4452 * Atomically updates the IRTE with the new destination, vector
4453 * and flushes the interrupt entry cache.
4454 */
4455 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4456 irte_info->index, cfg->vector,
4457 cfg->dest_apicid);
4458 }
4459
4460 static int amd_ir_set_affinity(struct irq_data *data,
4461 const struct cpumask *mask, bool force)
4462 {
4463 struct amd_ir_data *ir_data = data->chip_data;
4464 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4465 struct irq_cfg *cfg = irqd_cfg(data);
4466 struct irq_data *parent = data->parent_data;
4467 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4468 int ret;
4469
4470 if (!iommu)
4471 return -ENODEV;
4472
4473 ret = parent->chip->irq_set_affinity(parent, mask, force);
4474 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4475 return ret;
4476
4477 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4478 /*
4479 * After this point, all the interrupts will start arriving
4480 * at the new destination. So, time to cleanup the previous
4481 * vector allocation.
4482 */
4483 send_cleanup_vector(cfg);
4484
4485 return IRQ_SET_MASK_OK_DONE;
4486 }
4487
4488 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4489 {
4490 struct amd_ir_data *ir_data = irq_data->chip_data;
4491
4492 *msg = ir_data->msi_entry;
4493 }
4494
4495 static struct irq_chip amd_ir_chip = {
4496 .name = "AMD-IR",
4497 .irq_ack = apic_ack_irq,
4498 .irq_set_affinity = amd_ir_set_affinity,
4499 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4500 .irq_compose_msi_msg = ir_compose_msi_msg,
4501 };
4502
4503 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4504 {
4505 struct fwnode_handle *fn;
4506
4507 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4508 if (!fn)
4509 return -ENOMEM;
4510 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4511 irq_domain_free_fwnode(fn);
4512 if (!iommu->ir_domain)
4513 return -ENOMEM;
4514
4515 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4516 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4517 "AMD-IR-MSI",
4518 iommu->index);
4519 return 0;
4520 }
4521
4522 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4523 {
4524 unsigned long flags;
4525 struct amd_iommu *iommu;
4526 struct irq_remap_table *table;
4527 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4528 int devid = ir_data->irq_2_irte.devid;
4529 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4530 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4531
4532 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4533 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4534 return 0;
4535
4536 iommu = amd_iommu_rlookup_table[devid];
4537 if (!iommu)
4538 return -ENODEV;
4539
4540 table = get_irq_table(devid);
4541 if (!table)
4542 return -ENODEV;
4543
4544 raw_spin_lock_irqsave(&table->lock, flags);
4545
4546 if (ref->lo.fields_vapic.guest_mode) {
4547 if (cpu >= 0) {
4548 ref->lo.fields_vapic.destination =
4549 APICID_TO_IRTE_DEST_LO(cpu);
4550 ref->hi.fields.destination =
4551 APICID_TO_IRTE_DEST_HI(cpu);
4552 }
4553 ref->lo.fields_vapic.is_run = is_run;
4554 barrier();
4555 }
4556
4557 raw_spin_unlock_irqrestore(&table->lock, flags);
4558
4559 iommu_flush_irt(iommu, devid);
4560 iommu_completion_wait(iommu);
4561 return 0;
4562 }
4563 EXPORT_SYMBOL(amd_iommu_update_ga);
4564 #endif
Linux with added FPC-III support