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Linux 4.19.133
[linux/fpc-iii.git] / drivers / iommu / omap-iommu.c
blobd2fb347aa4ffcbe5885a3b083b431aa09b6d93d1
1 /*
2 * omap iommu: tlb and pagetable primitives
3 *
4 * Copyright (C) 2008-2010 Nokia Corporation
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
6 *
7 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
8 * Paul Mundt and Toshihiro Kobayashi
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/ioport.h>
20 #include <linux/platform_device.h>
21 #include <linux/iommu.h>
22 #include <linux/omap-iommu.h>
23 #include <linux/mutex.h>
24 #include <linux/spinlock.h>
25 #include <linux/io.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/of.h>
28 #include <linux/of_iommu.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_platform.h>
31 #include <linux/regmap.h>
32 #include <linux/mfd/syscon.h>
33
34 #include <linux/platform_data/iommu-omap.h>
35
36 #include "omap-iopgtable.h"
37 #include "omap-iommu.h"
38
39 static const struct iommu_ops omap_iommu_ops;
40
41 #define to_iommu(dev) \
42 ((struct omap_iommu *)platform_get_drvdata(to_platform_device(dev)))
43
44 /* bitmap of the page sizes currently supported */
45 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
46
47 #define MMU_LOCK_BASE_SHIFT 10
48 #define MMU_LOCK_BASE_MASK (0x1f << MMU_LOCK_BASE_SHIFT)
49 #define MMU_LOCK_BASE(x) \
50 ((x & MMU_LOCK_BASE_MASK) >> MMU_LOCK_BASE_SHIFT)
51
52 #define MMU_LOCK_VICT_SHIFT 4
53 #define MMU_LOCK_VICT_MASK (0x1f << MMU_LOCK_VICT_SHIFT)
54 #define MMU_LOCK_VICT(x) \
55 ((x & MMU_LOCK_VICT_MASK) >> MMU_LOCK_VICT_SHIFT)
56
57 static struct platform_driver omap_iommu_driver;
58 static struct kmem_cache *iopte_cachep;
59
60 /**
61 * to_omap_domain - Get struct omap_iommu_domain from generic iommu_domain
62 * @dom: generic iommu domain handle
63 **/
64 static struct omap_iommu_domain *to_omap_domain(struct iommu_domain *dom)
65 {
66 return container_of(dom, struct omap_iommu_domain, domain);
67 }
68
69 /**
70 * omap_iommu_save_ctx - Save registers for pm off-mode support
71 * @dev: client device
72 **/
73 void omap_iommu_save_ctx(struct device *dev)
74 {
75 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
76 struct omap_iommu *obj;
77 u32 *p;
78 int i;
79
80 if (!arch_data)
81 return;
82
83 while (arch_data->iommu_dev) {
84 obj = arch_data->iommu_dev;
85 p = obj->ctx;
86 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
87 p[i] = iommu_read_reg(obj, i * sizeof(u32));
88 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
89 p[i]);
90 }
91 arch_data++;
92 }
93 }
94 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
95
96 /**
97 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
98 * @dev: client device
99 **/
100 void omap_iommu_restore_ctx(struct device *dev)
101 {
102 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
103 struct omap_iommu *obj;
104 u32 *p;
105 int i;
106
107 if (!arch_data)
108 return;
109
110 while (arch_data->iommu_dev) {
111 obj = arch_data->iommu_dev;
112 p = obj->ctx;
113 for (i = 0; i < (MMU_REG_SIZE / sizeof(u32)); i++) {
114 iommu_write_reg(obj, p[i], i * sizeof(u32));
115 dev_dbg(obj->dev, "%s\t[%02d] %08x\n", __func__, i,
116 p[i]);
117 }
118 arch_data++;
119 }
120 }
121 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
122
123 static void dra7_cfg_dspsys_mmu(struct omap_iommu *obj, bool enable)
124 {
125 u32 val, mask;
126
127 if (!obj->syscfg)
128 return;
129
130 mask = (1 << (obj->id * DSP_SYS_MMU_CONFIG_EN_SHIFT));
131 val = enable ? mask : 0;
132 regmap_update_bits(obj->syscfg, DSP_SYS_MMU_CONFIG, mask, val);
133 }
134
135 static void __iommu_set_twl(struct omap_iommu *obj, bool on)
136 {
137 u32 l = iommu_read_reg(obj, MMU_CNTL);
138
139 if (on)
140 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
141 else
142 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
143
144 l &= ~MMU_CNTL_MASK;
145 if (on)
146 l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
147 else
148 l |= (MMU_CNTL_MMU_EN);
149
150 iommu_write_reg(obj, l, MMU_CNTL);
151 }
152
153 static int omap2_iommu_enable(struct omap_iommu *obj)
154 {
155 u32 l, pa;
156
157 if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K))
158 return -EINVAL;
159
160 pa = virt_to_phys(obj->iopgd);
161 if (!IS_ALIGNED(pa, SZ_16K))
162 return -EINVAL;
163
164 l = iommu_read_reg(obj, MMU_REVISION);
165 dev_info(obj->dev, "%s: version %d.%d\n", obj->name,
166 (l >> 4) & 0xf, l & 0xf);
167
168 iommu_write_reg(obj, pa, MMU_TTB);
169
170 dra7_cfg_dspsys_mmu(obj, true);
171
172 if (obj->has_bus_err_back)
173 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
174
175 __iommu_set_twl(obj, true);
176
177 return 0;
178 }
179
180 static void omap2_iommu_disable(struct omap_iommu *obj)
181 {
182 u32 l = iommu_read_reg(obj, MMU_CNTL);
183
184 l &= ~MMU_CNTL_MASK;
185 iommu_write_reg(obj, l, MMU_CNTL);
186 dra7_cfg_dspsys_mmu(obj, false);
187
188 dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
189 }
190
191 static int iommu_enable(struct omap_iommu *obj)
192 {
193 int err;
194 struct platform_device *pdev = to_platform_device(obj->dev);
195 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
196
197 if (pdata && pdata->deassert_reset) {
198 err = pdata->deassert_reset(pdev, pdata->reset_name);
199 if (err) {
200 dev_err(obj->dev, "deassert_reset failed: %d\n", err);
201 return err;
202 }
203 }
204
205 pm_runtime_get_sync(obj->dev);
206
207 err = omap2_iommu_enable(obj);
208
209 return err;
210 }
211
212 static void iommu_disable(struct omap_iommu *obj)
213 {
214 struct platform_device *pdev = to_platform_device(obj->dev);
215 struct iommu_platform_data *pdata = dev_get_platdata(&pdev->dev);
216
217 omap2_iommu_disable(obj);
218
219 pm_runtime_put_sync(obj->dev);
220
221 if (pdata && pdata->assert_reset)
222 pdata->assert_reset(pdev, pdata->reset_name);
223 }
224
225 /*
226 * TLB operations
227 */
228 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
229 {
230 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK;
231 u32 mask = get_cam_va_mask(cr->cam & page_size);
232
233 return cr->cam & mask;
234 }
235
236 static u32 get_iopte_attr(struct iotlb_entry *e)
237 {
238 u32 attr;
239
240 attr = e->mixed << 5;
241 attr |= e->endian;
242 attr |= e->elsz >> 3;
243 attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
244 (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
245 return attr;
246 }
247
248 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
249 {
250 u32 status, fault_addr;
251
252 status = iommu_read_reg(obj, MMU_IRQSTATUS);
253 status &= MMU_IRQ_MASK;
254 if (!status) {
255 *da = 0;
256 return 0;
257 }
258
259 fault_addr = iommu_read_reg(obj, MMU_FAULT_AD);
260 *da = fault_addr;
261
262 iommu_write_reg(obj, status, MMU_IRQSTATUS);
263
264 return status;
265 }
266
267 void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
268 {
269 u32 val;
270
271 val = iommu_read_reg(obj, MMU_LOCK);
272
273 l->base = MMU_LOCK_BASE(val);
274 l->vict = MMU_LOCK_VICT(val);
275 }
276
277 void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
278 {
279 u32 val;
280
281 val = (l->base << MMU_LOCK_BASE_SHIFT);
282 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
283
284 iommu_write_reg(obj, val, MMU_LOCK);
285 }
286
287 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
288 {
289 cr->cam = iommu_read_reg(obj, MMU_READ_CAM);
290 cr->ram = iommu_read_reg(obj, MMU_READ_RAM);
291 }
292
293 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
294 {
295 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
296 iommu_write_reg(obj, cr->ram, MMU_RAM);
297
298 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
299 iommu_write_reg(obj, 1, MMU_LD_TLB);
300 }
301
302 /* only used in iotlb iteration for-loop */
303 struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
304 {
305 struct cr_regs cr;
306 struct iotlb_lock l;
307
308 iotlb_lock_get(obj, &l);
309 l.vict = n;
310 iotlb_lock_set(obj, &l);
311 iotlb_read_cr(obj, &cr);
312
313 return cr;
314 }
315
316 #ifdef PREFETCH_IOTLB
317 static struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
318 struct iotlb_entry *e)
319 {
320 struct cr_regs *cr;
321
322 if (!e)
323 return NULL;
324
325 if (e->da & ~(get_cam_va_mask(e->pgsz))) {
326 dev_err(obj->dev, "%s:\twrong alignment: %08x\n", __func__,
327 e->da);
328 return ERR_PTR(-EINVAL);
329 }
330
331 cr = kmalloc(sizeof(*cr), GFP_KERNEL);
332 if (!cr)
333 return ERR_PTR(-ENOMEM);
334
335 cr->cam = (e->da & MMU_CAM_VATAG_MASK) | e->prsvd | e->pgsz | e->valid;
336 cr->ram = e->pa | e->endian | e->elsz | e->mixed;
337
338 return cr;
339 }
340
341 /**
342 * load_iotlb_entry - Set an iommu tlb entry
343 * @obj: target iommu
344 * @e: an iommu tlb entry info
345 **/
346 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
347 {
348 int err = 0;
349 struct iotlb_lock l;
350 struct cr_regs *cr;
351
352 if (!obj || !obj->nr_tlb_entries || !e)
353 return -EINVAL;
354
355 pm_runtime_get_sync(obj->dev);
356
357 iotlb_lock_get(obj, &l);
358 if (l.base == obj->nr_tlb_entries) {
359 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
360 err = -EBUSY;
361 goto out;
362 }
363 if (!e->prsvd) {
364 int i;
365 struct cr_regs tmp;
366
367 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
368 if (!iotlb_cr_valid(&tmp))
369 break;
370
371 if (i == obj->nr_tlb_entries) {
372 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
373 err = -EBUSY;
374 goto out;
375 }
376
377 iotlb_lock_get(obj, &l);
378 } else {
379 l.vict = l.base;
380 iotlb_lock_set(obj, &l);
381 }
382
383 cr = iotlb_alloc_cr(obj, e);
384 if (IS_ERR(cr)) {
385 pm_runtime_put_sync(obj->dev);
386 return PTR_ERR(cr);
387 }
388
389 iotlb_load_cr(obj, cr);
390 kfree(cr);
391
392 if (e->prsvd)
393 l.base++;
394 /* increment victim for next tlb load */
395 if (++l.vict == obj->nr_tlb_entries)
396 l.vict = l.base;
397 iotlb_lock_set(obj, &l);
398 out:
399 pm_runtime_put_sync(obj->dev);
400 return err;
401 }
402
403 #else /* !PREFETCH_IOTLB */
404
405 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
406 {
407 return 0;
408 }
409
410 #endif /* !PREFETCH_IOTLB */
411
412 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
413 {
414 return load_iotlb_entry(obj, e);
415 }
416
417 /**
418 * flush_iotlb_page - Clear an iommu tlb entry
419 * @obj: target iommu
420 * @da: iommu device virtual address
421 *
422 * Clear an iommu tlb entry which includes 'da' address.
423 **/
424 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
425 {
426 int i;
427 struct cr_regs cr;
428
429 pm_runtime_get_sync(obj->dev);
430
431 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
432 u32 start;
433 size_t bytes;
434
435 if (!iotlb_cr_valid(&cr))
436 continue;
437
438 start = iotlb_cr_to_virt(&cr);
439 bytes = iopgsz_to_bytes(cr.cam & 3);
440
441 if ((start <= da) && (da < start + bytes)) {
442 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
443 __func__, start, da, bytes);
444 iotlb_load_cr(obj, &cr);
445 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
446 break;
447 }
448 }
449 pm_runtime_put_sync(obj->dev);
450
451 if (i == obj->nr_tlb_entries)
452 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
453 }
454
455 /**
456 * flush_iotlb_all - Clear all iommu tlb entries
457 * @obj: target iommu
458 **/
459 static void flush_iotlb_all(struct omap_iommu *obj)
460 {
461 struct iotlb_lock l;
462
463 pm_runtime_get_sync(obj->dev);
464
465 l.base = 0;
466 l.vict = 0;
467 iotlb_lock_set(obj, &l);
468
469 iommu_write_reg(obj, 1, MMU_GFLUSH);
470
471 pm_runtime_put_sync(obj->dev);
472 }
473
474 /*
475 * H/W pagetable operations
476 */
477 static void flush_iopte_range(struct device *dev, dma_addr_t dma,
478 unsigned long offset, int num_entries)
479 {
480 size_t size = num_entries * sizeof(u32);
481
482 dma_sync_single_range_for_device(dev, dma, offset, size, DMA_TO_DEVICE);
483 }
484
485 static void iopte_free(struct omap_iommu *obj, u32 *iopte, bool dma_valid)
486 {
487 dma_addr_t pt_dma;
488
489 /* Note: freed iopte's must be clean ready for re-use */
490 if (iopte) {
491 if (dma_valid) {
492 pt_dma = virt_to_phys(iopte);
493 dma_unmap_single(obj->dev, pt_dma, IOPTE_TABLE_SIZE,
494 DMA_TO_DEVICE);
495 }
496
497 kmem_cache_free(iopte_cachep, iopte);
498 }
499 }
500
501 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd,
502 dma_addr_t *pt_dma, u32 da)
503 {
504 u32 *iopte;
505 unsigned long offset = iopgd_index(da) * sizeof(da);
506
507 /* a table has already existed */
508 if (*iopgd)
509 goto pte_ready;
510
511 /*
512 * do the allocation outside the page table lock
513 */
514 spin_unlock(&obj->page_table_lock);
515 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
516 spin_lock(&obj->page_table_lock);
517
518 if (!*iopgd) {
519 if (!iopte)
520 return ERR_PTR(-ENOMEM);
521
522 *pt_dma = dma_map_single(obj->dev, iopte, IOPTE_TABLE_SIZE,
523 DMA_TO_DEVICE);
524 if (dma_mapping_error(obj->dev, *pt_dma)) {
525 dev_err(obj->dev, "DMA map error for L2 table\n");
526 iopte_free(obj, iopte, false);
527 return ERR_PTR(-ENOMEM);
528 }
529
530 /*
531 * we rely on dma address and the physical address to be
532 * the same for mapping the L2 table
533 */
534 if (WARN_ON(*pt_dma != virt_to_phys(iopte))) {
535 dev_err(obj->dev, "DMA translation error for L2 table\n");
536 dma_unmap_single(obj->dev, *pt_dma, IOPTE_TABLE_SIZE,
537 DMA_TO_DEVICE);
538 iopte_free(obj, iopte, false);
539 return ERR_PTR(-ENOMEM);
540 }
541
542 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
543
544 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
545 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
546 } else {
547 /* We raced, free the reduniovant table */
548 iopte_free(obj, iopte, false);
549 }
550
551 pte_ready:
552 iopte = iopte_offset(iopgd, da);
553 *pt_dma = iopgd_page_paddr(iopgd);
554 dev_vdbg(obj->dev,
555 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
556 __func__, da, iopgd, *iopgd, iopte, *iopte);
557
558 return iopte;
559 }
560
561 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
562 {
563 u32 *iopgd = iopgd_offset(obj, da);
564 unsigned long offset = iopgd_index(da) * sizeof(da);
565
566 if ((da | pa) & ~IOSECTION_MASK) {
567 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
568 __func__, da, pa, IOSECTION_SIZE);
569 return -EINVAL;
570 }
571
572 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
573 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
574 return 0;
575 }
576
577 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
578 {
579 u32 *iopgd = iopgd_offset(obj, da);
580 unsigned long offset = iopgd_index(da) * sizeof(da);
581 int i;
582
583 if ((da | pa) & ~IOSUPER_MASK) {
584 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
585 __func__, da, pa, IOSUPER_SIZE);
586 return -EINVAL;
587 }
588
589 for (i = 0; i < 16; i++)
590 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
591 flush_iopte_range(obj->dev, obj->pd_dma, offset, 16);
592 return 0;
593 }
594
595 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
596 {
597 u32 *iopgd = iopgd_offset(obj, da);
598 dma_addr_t pt_dma;
599 u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
600 unsigned long offset = iopte_index(da) * sizeof(da);
601
602 if (IS_ERR(iopte))
603 return PTR_ERR(iopte);
604
605 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
606 flush_iopte_range(obj->dev, pt_dma, offset, 1);
607
608 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
609 __func__, da, pa, iopte, *iopte);
610
611 return 0;
612 }
613
614 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
615 {
616 u32 *iopgd = iopgd_offset(obj, da);
617 dma_addr_t pt_dma;
618 u32 *iopte = iopte_alloc(obj, iopgd, &pt_dma, da);
619 unsigned long offset = iopte_index(da) * sizeof(da);
620 int i;
621
622 if ((da | pa) & ~IOLARGE_MASK) {
623 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
624 __func__, da, pa, IOLARGE_SIZE);
625 return -EINVAL;
626 }
627
628 if (IS_ERR(iopte))
629 return PTR_ERR(iopte);
630
631 for (i = 0; i < 16; i++)
632 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
633 flush_iopte_range(obj->dev, pt_dma, offset, 16);
634 return 0;
635 }
636
637 static int
638 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
639 {
640 int (*fn)(struct omap_iommu *, u32, u32, u32);
641 u32 prot;
642 int err;
643
644 if (!obj || !e)
645 return -EINVAL;
646
647 switch (e->pgsz) {
648 case MMU_CAM_PGSZ_16M:
649 fn = iopgd_alloc_super;
650 break;
651 case MMU_CAM_PGSZ_1M:
652 fn = iopgd_alloc_section;
653 break;
654 case MMU_CAM_PGSZ_64K:
655 fn = iopte_alloc_large;
656 break;
657 case MMU_CAM_PGSZ_4K:
658 fn = iopte_alloc_page;
659 break;
660 default:
661 fn = NULL;
662 break;
663 }
664
665 if (WARN_ON(!fn))
666 return -EINVAL;
667
668 prot = get_iopte_attr(e);
669
670 spin_lock(&obj->page_table_lock);
671 err = fn(obj, e->da, e->pa, prot);
672 spin_unlock(&obj->page_table_lock);
673
674 return err;
675 }
676
677 /**
678 * omap_iopgtable_store_entry - Make an iommu pte entry
679 * @obj: target iommu
680 * @e: an iommu tlb entry info
681 **/
682 static int
683 omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
684 {
685 int err;
686
687 flush_iotlb_page(obj, e->da);
688 err = iopgtable_store_entry_core(obj, e);
689 if (!err)
690 prefetch_iotlb_entry(obj, e);
691 return err;
692 }
693
694 /**
695 * iopgtable_lookup_entry - Lookup an iommu pte entry
696 * @obj: target iommu
697 * @da: iommu device virtual address
698 * @ppgd: iommu pgd entry pointer to be returned
699 * @ppte: iommu pte entry pointer to be returned
700 **/
701 static void
702 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
703 {
704 u32 *iopgd, *iopte = NULL;
705
706 iopgd = iopgd_offset(obj, da);
707 if (!*iopgd)
708 goto out;
709
710 if (iopgd_is_table(*iopgd))
711 iopte = iopte_offset(iopgd, da);
712 out:
713 *ppgd = iopgd;
714 *ppte = iopte;
715 }
716
717 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
718 {
719 size_t bytes;
720 u32 *iopgd = iopgd_offset(obj, da);
721 int nent = 1;
722 dma_addr_t pt_dma;
723 unsigned long pd_offset = iopgd_index(da) * sizeof(da);
724 unsigned long pt_offset = iopte_index(da) * sizeof(da);
725
726 if (!*iopgd)
727 return 0;
728
729 if (iopgd_is_table(*iopgd)) {
730 int i;
731 u32 *iopte = iopte_offset(iopgd, da);
732
733 bytes = IOPTE_SIZE;
734 if (*iopte & IOPTE_LARGE) {
735 nent *= 16;
736 /* rewind to the 1st entry */
737 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
738 }
739 bytes *= nent;
740 memset(iopte, 0, nent * sizeof(*iopte));
741 pt_dma = iopgd_page_paddr(iopgd);
742 flush_iopte_range(obj->dev, pt_dma, pt_offset, nent);
743
744 /*
745 * do table walk to check if this table is necessary or not
746 */
747 iopte = iopte_offset(iopgd, 0);
748 for (i = 0; i < PTRS_PER_IOPTE; i++)
749 if (iopte[i])
750 goto out;
751
752 iopte_free(obj, iopte, true);
753 nent = 1; /* for the next L1 entry */
754 } else {
755 bytes = IOPGD_SIZE;
756 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
757 nent *= 16;
758 /* rewind to the 1st entry */
759 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
760 }
761 bytes *= nent;
762 }
763 memset(iopgd, 0, nent * sizeof(*iopgd));
764 flush_iopte_range(obj->dev, obj->pd_dma, pd_offset, nent);
765 out:
766 return bytes;
767 }
768
769 /**
770 * iopgtable_clear_entry - Remove an iommu pte entry
771 * @obj: target iommu
772 * @da: iommu device virtual address
773 **/
774 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
775 {
776 size_t bytes;
777
778 spin_lock(&obj->page_table_lock);
779
780 bytes = iopgtable_clear_entry_core(obj, da);
781 flush_iotlb_page(obj, da);
782
783 spin_unlock(&obj->page_table_lock);
784
785 return bytes;
786 }
787
788 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
789 {
790 unsigned long offset;
791 int i;
792
793 spin_lock(&obj->page_table_lock);
794
795 for (i = 0; i < PTRS_PER_IOPGD; i++) {
796 u32 da;
797 u32 *iopgd;
798
799 da = i << IOPGD_SHIFT;
800 iopgd = iopgd_offset(obj, da);
801 offset = iopgd_index(da) * sizeof(da);
802
803 if (!*iopgd)
804 continue;
805
806 if (iopgd_is_table(*iopgd))
807 iopte_free(obj, iopte_offset(iopgd, 0), true);
808
809 *iopgd = 0;
810 flush_iopte_range(obj->dev, obj->pd_dma, offset, 1);
811 }
812
813 flush_iotlb_all(obj);
814
815 spin_unlock(&obj->page_table_lock);
816 }
817
818 /*
819 * Device IOMMU generic operations
820 */
821 static irqreturn_t iommu_fault_handler(int irq, void *data)
822 {
823 u32 da, errs;
824 u32 *iopgd, *iopte;
825 struct omap_iommu *obj = data;
826 struct iommu_domain *domain = obj->domain;
827 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
828
829 if (!omap_domain->dev)
830 return IRQ_NONE;
831
832 errs = iommu_report_fault(obj, &da);
833 if (errs == 0)
834 return IRQ_HANDLED;
835
836 /* Fault callback or TLB/PTE Dynamic loading */
837 if (!report_iommu_fault(domain, obj->dev, da, 0))
838 return IRQ_HANDLED;
839
840 iommu_write_reg(obj, 0, MMU_IRQENABLE);
841
842 iopgd = iopgd_offset(obj, da);
843
844 if (!iopgd_is_table(*iopgd)) {
845 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:px%08x\n",
846 obj->name, errs, da, iopgd, *iopgd);
847 return IRQ_NONE;
848 }
849
850 iopte = iopte_offset(iopgd, da);
851
852 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x pte:0x%p *pte:0x%08x\n",
853 obj->name, errs, da, iopgd, *iopgd, iopte, *iopte);
854
855 return IRQ_NONE;
856 }
857
858 /**
859 * omap_iommu_attach() - attach iommu device to an iommu domain
860 * @obj: target omap iommu device
861 * @iopgd: page table
862 **/
863 static int omap_iommu_attach(struct omap_iommu *obj, u32 *iopgd)
864 {
865 int err;
866
867 spin_lock(&obj->iommu_lock);
868
869 obj->pd_dma = dma_map_single(obj->dev, iopgd, IOPGD_TABLE_SIZE,
870 DMA_TO_DEVICE);
871 if (dma_mapping_error(obj->dev, obj->pd_dma)) {
872 dev_err(obj->dev, "DMA map error for L1 table\n");
873 err = -ENOMEM;
874 goto out_err;
875 }
876
877 obj->iopgd = iopgd;
878 err = iommu_enable(obj);
879 if (err)
880 goto out_err;
881 flush_iotlb_all(obj);
882
883 spin_unlock(&obj->iommu_lock);
884
885 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
886
887 return 0;
888
889 out_err:
890 spin_unlock(&obj->iommu_lock);
891
892 return err;
893 }
894
895 /**
896 * omap_iommu_detach - release iommu device
897 * @obj: target iommu
898 **/
899 static void omap_iommu_detach(struct omap_iommu *obj)
900 {
901 if (!obj || IS_ERR(obj))
902 return;
903
904 spin_lock(&obj->iommu_lock);
905
906 dma_unmap_single(obj->dev, obj->pd_dma, IOPGD_TABLE_SIZE,
907 DMA_TO_DEVICE);
908 iommu_disable(obj);
909 obj->pd_dma = 0;
910 obj->iopgd = NULL;
911
912 spin_unlock(&obj->iommu_lock);
913
914 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
915 }
916
917 static bool omap_iommu_can_register(struct platform_device *pdev)
918 {
919 struct device_node *np = pdev->dev.of_node;
920
921 if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
922 return true;
923
924 /*
925 * restrict IOMMU core registration only for processor-port MDMA MMUs
926 * on DRA7 DSPs
927 */
928 if ((!strcmp(dev_name(&pdev->dev), "40d01000.mmu")) ||
929 (!strcmp(dev_name(&pdev->dev), "41501000.mmu")))
930 return true;
931
932 return false;
933 }
934
935 static int omap_iommu_dra7_get_dsp_system_cfg(struct platform_device *pdev,
936 struct omap_iommu *obj)
937 {
938 struct device_node *np = pdev->dev.of_node;
939 int ret;
940
941 if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
942 return 0;
943
944 if (!of_property_read_bool(np, "ti,syscon-mmuconfig")) {
945 dev_err(&pdev->dev, "ti,syscon-mmuconfig property is missing\n");
946 return -EINVAL;
947 }
948
949 obj->syscfg =
950 syscon_regmap_lookup_by_phandle(np, "ti,syscon-mmuconfig");
951 if (IS_ERR(obj->syscfg)) {
952 /* can fail with -EPROBE_DEFER */
953 ret = PTR_ERR(obj->syscfg);
954 return ret;
955 }
956
957 if (of_property_read_u32_index(np, "ti,syscon-mmuconfig", 1,
958 &obj->id)) {
959 dev_err(&pdev->dev, "couldn't get the IOMMU instance id within subsystem\n");
960 return -EINVAL;
961 }
962
963 if (obj->id != 0 && obj->id != 1) {
964 dev_err(&pdev->dev, "invalid IOMMU instance id\n");
965 return -EINVAL;
966 }
967
968 return 0;
969 }
970
971 /*
972 * OMAP Device MMU(IOMMU) detection
973 */
974 static int omap_iommu_probe(struct platform_device *pdev)
975 {
976 int err = -ENODEV;
977 int irq;
978 struct omap_iommu *obj;
979 struct resource *res;
980 struct device_node *of = pdev->dev.of_node;
981
982 if (!of) {
983 pr_err("%s: only DT-based devices are supported\n", __func__);
984 return -ENODEV;
985 }
986
987 obj = devm_kzalloc(&pdev->dev, sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
988 if (!obj)
989 return -ENOMEM;
990
991 obj->name = dev_name(&pdev->dev);
992 obj->nr_tlb_entries = 32;
993 err = of_property_read_u32(of, "ti,#tlb-entries", &obj->nr_tlb_entries);
994 if (err && err != -EINVAL)
995 return err;
996 if (obj->nr_tlb_entries != 32 && obj->nr_tlb_entries != 8)
997 return -EINVAL;
998 if (of_find_property(of, "ti,iommu-bus-err-back", NULL))
999 obj->has_bus_err_back = MMU_GP_REG_BUS_ERR_BACK_EN;
1000
1001 obj->dev = &pdev->dev;
1002 obj->ctx = (void *)obj + sizeof(*obj);
1003
1004 spin_lock_init(&obj->iommu_lock);
1005 spin_lock_init(&obj->page_table_lock);
1006
1007 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1008 obj->regbase = devm_ioremap_resource(obj->dev, res);
1009 if (IS_ERR(obj->regbase))
1010 return PTR_ERR(obj->regbase);
1011
1012 err = omap_iommu_dra7_get_dsp_system_cfg(pdev, obj);
1013 if (err)
1014 return err;
1015
1016 irq = platform_get_irq(pdev, 0);
1017 if (irq < 0)
1018 return -ENODEV;
1019
1020 err = devm_request_irq(obj->dev, irq, iommu_fault_handler, IRQF_SHARED,
1021 dev_name(obj->dev), obj);
1022 if (err < 0)
1023 return err;
1024 platform_set_drvdata(pdev, obj);
1025
1026 if (omap_iommu_can_register(pdev)) {
1027 obj->group = iommu_group_alloc();
1028 if (IS_ERR(obj->group))
1029 return PTR_ERR(obj->group);
1030
1031 err = iommu_device_sysfs_add(&obj->iommu, obj->dev, NULL,
1032 obj->name);
1033 if (err)
1034 goto out_group;
1035
1036 iommu_device_set_ops(&obj->iommu, &omap_iommu_ops);
1037
1038 err = iommu_device_register(&obj->iommu);
1039 if (err)
1040 goto out_sysfs;
1041 }
1042
1043 pm_runtime_irq_safe(obj->dev);
1044 pm_runtime_enable(obj->dev);
1045
1046 omap_iommu_debugfs_add(obj);
1047
1048 dev_info(&pdev->dev, "%s registered\n", obj->name);
1049
1050 return 0;
1051
1052 out_sysfs:
1053 iommu_device_sysfs_remove(&obj->iommu);
1054 out_group:
1055 iommu_group_put(obj->group);
1056 return err;
1057 }
1058
1059 static int omap_iommu_remove(struct platform_device *pdev)
1060 {
1061 struct omap_iommu *obj = platform_get_drvdata(pdev);
1062
1063 if (obj->group) {
1064 iommu_group_put(obj->group);
1065 obj->group = NULL;
1066
1067 iommu_device_sysfs_remove(&obj->iommu);
1068 iommu_device_unregister(&obj->iommu);
1069 }
1070
1071 omap_iommu_debugfs_remove(obj);
1072
1073 pm_runtime_disable(obj->dev);
1074
1075 dev_info(&pdev->dev, "%s removed\n", obj->name);
1076 return 0;
1077 }
1078
1079 static const struct of_device_id omap_iommu_of_match[] = {
1080 { .compatible = "ti,omap2-iommu" },
1081 { .compatible = "ti,omap4-iommu" },
1082 { .compatible = "ti,dra7-iommu" },
1083 { .compatible = "ti,dra7-dsp-iommu" },
1084 {},
1085 };
1086
1087 static struct platform_driver omap_iommu_driver = {
1088 .probe = omap_iommu_probe,
1089 .remove = omap_iommu_remove,
1090 .driver = {
1091 .name = "omap-iommu",
1092 .of_match_table = of_match_ptr(omap_iommu_of_match),
1093 },
1094 };
1095
1096 static u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa, int pgsz)
1097 {
1098 memset(e, 0, sizeof(*e));
1099
1100 e->da = da;
1101 e->pa = pa;
1102 e->valid = MMU_CAM_V;
1103 e->pgsz = pgsz;
1104 e->endian = MMU_RAM_ENDIAN_LITTLE;
1105 e->elsz = MMU_RAM_ELSZ_8;
1106 e->mixed = 0;
1107
1108 return iopgsz_to_bytes(e->pgsz);
1109 }
1110
1111 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1112 phys_addr_t pa, size_t bytes, int prot)
1113 {
1114 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1115 struct device *dev = omap_domain->dev;
1116 struct omap_iommu_device *iommu;
1117 struct omap_iommu *oiommu;
1118 struct iotlb_entry e;
1119 int omap_pgsz;
1120 u32 ret = -EINVAL;
1121 int i;
1122
1123 omap_pgsz = bytes_to_iopgsz(bytes);
1124 if (omap_pgsz < 0) {
1125 dev_err(dev, "invalid size to map: %d\n", bytes);
1126 return -EINVAL;
1127 }
1128
1129 dev_dbg(dev, "mapping da 0x%lx to pa %pa size 0x%x\n", da, &pa, bytes);
1130
1131 iotlb_init_entry(&e, da, pa, omap_pgsz);
1132
1133 iommu = omap_domain->iommus;
1134 for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1135 oiommu = iommu->iommu_dev;
1136 ret = omap_iopgtable_store_entry(oiommu, &e);
1137 if (ret) {
1138 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n",
1139 ret);
1140 break;
1141 }
1142 }
1143
1144 if (ret) {
1145 while (i--) {
1146 iommu--;
1147 oiommu = iommu->iommu_dev;
1148 iopgtable_clear_entry(oiommu, da);
1149 }
1150 }
1151
1152 return ret;
1153 }
1154
1155 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1156 size_t size)
1157 {
1158 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1159 struct device *dev = omap_domain->dev;
1160 struct omap_iommu_device *iommu;
1161 struct omap_iommu *oiommu;
1162 bool error = false;
1163 size_t bytes = 0;
1164 int i;
1165
1166 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1167
1168 iommu = omap_domain->iommus;
1169 for (i = 0; i < omap_domain->num_iommus; i++, iommu++) {
1170 oiommu = iommu->iommu_dev;
1171 bytes = iopgtable_clear_entry(oiommu, da);
1172 if (!bytes)
1173 error = true;
1174 }
1175
1176 /*
1177 * simplify return - we are only checking if any of the iommus
1178 * reported an error, but not if all of them are unmapping the
1179 * same number of entries. This should not occur due to the
1180 * mirror programming.
1181 */
1182 return error ? 0 : bytes;
1183 }
1184
1185 static int omap_iommu_count(struct device *dev)
1186 {
1187 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1188 int count = 0;
1189
1190 while (arch_data->iommu_dev) {
1191 count++;
1192 arch_data++;
1193 }
1194
1195 return count;
1196 }
1197
1198 /* caller should call cleanup if this function fails */
1199 static int omap_iommu_attach_init(struct device *dev,
1200 struct omap_iommu_domain *odomain)
1201 {
1202 struct omap_iommu_device *iommu;
1203 int i;
1204
1205 odomain->num_iommus = omap_iommu_count(dev);
1206 if (!odomain->num_iommus)
1207 return -EINVAL;
1208
1209 odomain->iommus = kcalloc(odomain->num_iommus, sizeof(*iommu),
1210 GFP_ATOMIC);
1211 if (!odomain->iommus)
1212 return -ENOMEM;
1213
1214 iommu = odomain->iommus;
1215 for (i = 0; i < odomain->num_iommus; i++, iommu++) {
1216 iommu->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_ATOMIC);
1217 if (!iommu->pgtable)
1218 return -ENOMEM;
1219
1220 /*
1221 * should never fail, but please keep this around to ensure
1222 * we keep the hardware happy
1223 */
1224 if (WARN_ON(!IS_ALIGNED((long)iommu->pgtable,
1225 IOPGD_TABLE_SIZE)))
1226 return -EINVAL;
1227 }
1228
1229 return 0;
1230 }
1231
1232 static void omap_iommu_detach_fini(struct omap_iommu_domain *odomain)
1233 {
1234 int i;
1235 struct omap_iommu_device *iommu = odomain->iommus;
1236
1237 for (i = 0; iommu && i < odomain->num_iommus; i++, iommu++)
1238 kfree(iommu->pgtable);
1239
1240 kfree(odomain->iommus);
1241 odomain->num_iommus = 0;
1242 odomain->iommus = NULL;
1243 }
1244
1245 static int
1246 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1247 {
1248 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1249 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1250 struct omap_iommu_device *iommu;
1251 struct omap_iommu *oiommu;
1252 int ret = 0;
1253 int i;
1254
1255 if (!arch_data || !arch_data->iommu_dev) {
1256 dev_err(dev, "device doesn't have an associated iommu\n");
1257 return -EINVAL;
1258 }
1259
1260 spin_lock(&omap_domain->lock);
1261
1262 /* only a single client device can be attached to a domain */
1263 if (omap_domain->dev) {
1264 dev_err(dev, "iommu domain is already attached\n");
1265 ret = -EBUSY;
1266 goto out;
1267 }
1268
1269 ret = omap_iommu_attach_init(dev, omap_domain);
1270 if (ret) {
1271 dev_err(dev, "failed to allocate required iommu data %d\n",
1272 ret);
1273 goto init_fail;
1274 }
1275
1276 iommu = omap_domain->iommus;
1277 for (i = 0; i < omap_domain->num_iommus; i++, iommu++, arch_data++) {
1278 /* configure and enable the omap iommu */
1279 oiommu = arch_data->iommu_dev;
1280 ret = omap_iommu_attach(oiommu, iommu->pgtable);
1281 if (ret) {
1282 dev_err(dev, "can't get omap iommu: %d\n", ret);
1283 goto attach_fail;
1284 }
1285
1286 oiommu->domain = domain;
1287 iommu->iommu_dev = oiommu;
1288 }
1289
1290 omap_domain->dev = dev;
1291
1292 goto out;
1293
1294 attach_fail:
1295 while (i--) {
1296 iommu--;
1297 arch_data--;
1298 oiommu = iommu->iommu_dev;
1299 omap_iommu_detach(oiommu);
1300 iommu->iommu_dev = NULL;
1301 oiommu->domain = NULL;
1302 }
1303 init_fail:
1304 omap_iommu_detach_fini(omap_domain);
1305 out:
1306 spin_unlock(&omap_domain->lock);
1307 return ret;
1308 }
1309
1310 static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain,
1311 struct device *dev)
1312 {
1313 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1314 struct omap_iommu_device *iommu = omap_domain->iommus;
1315 struct omap_iommu *oiommu;
1316 int i;
1317
1318 if (!omap_domain->dev) {
1319 dev_err(dev, "domain has no attached device\n");
1320 return;
1321 }
1322
1323 /* only a single device is supported per domain for now */
1324 if (omap_domain->dev != dev) {
1325 dev_err(dev, "invalid attached device\n");
1326 return;
1327 }
1328
1329 /*
1330 * cleanup in the reverse order of attachment - this addresses
1331 * any h/w dependencies between multiple instances, if any
1332 */
1333 iommu += (omap_domain->num_iommus - 1);
1334 arch_data += (omap_domain->num_iommus - 1);
1335 for (i = 0; i < omap_domain->num_iommus; i++, iommu--, arch_data--) {
1336 oiommu = iommu->iommu_dev;
1337 iopgtable_clear_entry_all(oiommu);
1338
1339 omap_iommu_detach(oiommu);
1340 iommu->iommu_dev = NULL;
1341 oiommu->domain = NULL;
1342 }
1343
1344 omap_iommu_detach_fini(omap_domain);
1345
1346 omap_domain->dev = NULL;
1347 }
1348
1349 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1350 struct device *dev)
1351 {
1352 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1353
1354 spin_lock(&omap_domain->lock);
1355 _omap_iommu_detach_dev(omap_domain, dev);
1356 spin_unlock(&omap_domain->lock);
1357 }
1358
1359 static struct iommu_domain *omap_iommu_domain_alloc(unsigned type)
1360 {
1361 struct omap_iommu_domain *omap_domain;
1362
1363 if (type != IOMMU_DOMAIN_UNMANAGED)
1364 return NULL;
1365
1366 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1367 if (!omap_domain)
1368 return NULL;
1369
1370 spin_lock_init(&omap_domain->lock);
1371
1372 omap_domain->domain.geometry.aperture_start = 0;
1373 omap_domain->domain.geometry.aperture_end = (1ULL << 32) - 1;
1374 omap_domain->domain.geometry.force_aperture = true;
1375
1376 return &omap_domain->domain;
1377 }
1378
1379 static void omap_iommu_domain_free(struct iommu_domain *domain)
1380 {
1381 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1382
1383 /*
1384 * An iommu device is still attached
1385 * (currently, only one device can be attached) ?
1386 */
1387 if (omap_domain->dev)
1388 _omap_iommu_detach_dev(omap_domain, omap_domain->dev);
1389
1390 kfree(omap_domain);
1391 }
1392
1393 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1394 dma_addr_t da)
1395 {
1396 struct omap_iommu_domain *omap_domain = to_omap_domain(domain);
1397 struct omap_iommu_device *iommu = omap_domain->iommus;
1398 struct omap_iommu *oiommu = iommu->iommu_dev;
1399 struct device *dev = oiommu->dev;
1400 u32 *pgd, *pte;
1401 phys_addr_t ret = 0;
1402
1403 /*
1404 * all the iommus within the domain will have identical programming,
1405 * so perform the lookup using just the first iommu
1406 */
1407 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1408
1409 if (pte) {
1410 if (iopte_is_small(*pte))
1411 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1412 else if (iopte_is_large(*pte))
1413 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1414 else
1415 dev_err(dev, "bogus pte 0x%x, da 0x%llx", *pte,
1416 (unsigned long long)da);
1417 } else {
1418 if (iopgd_is_section(*pgd))
1419 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1420 else if (iopgd_is_super(*pgd))
1421 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1422 else
1423 dev_err(dev, "bogus pgd 0x%x, da 0x%llx", *pgd,
1424 (unsigned long long)da);
1425 }
1426
1427 return ret;
1428 }
1429
1430 static int omap_iommu_add_device(struct device *dev)
1431 {
1432 struct omap_iommu_arch_data *arch_data, *tmp;
1433 struct omap_iommu *oiommu;
1434 struct iommu_group *group;
1435 struct device_node *np;
1436 struct platform_device *pdev;
1437 int num_iommus, i;
1438 int ret;
1439
1440 /*
1441 * Allocate the archdata iommu structure for DT-based devices.
1442 *
1443 * TODO: Simplify this when removing non-DT support completely from the
1444 * IOMMU users.
1445 */
1446 if (!dev->of_node)
1447 return 0;
1448
1449 /*
1450 * retrieve the count of IOMMU nodes using phandle size as element size
1451 * since #iommu-cells = 0 for OMAP
1452 */
1453 num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus",
1454 sizeof(phandle));
1455 if (num_iommus < 0)
1456 return 0;
1457
1458 arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL);
1459 if (!arch_data)
1460 return -ENOMEM;
1461
1462 for (i = 0, tmp = arch_data; i < num_iommus; i++, tmp++) {
1463 np = of_parse_phandle(dev->of_node, "iommus", i);
1464 if (!np) {
1465 kfree(arch_data);
1466 return -EINVAL;
1467 }
1468
1469 pdev = of_find_device_by_node(np);
1470 if (WARN_ON(!pdev)) {
1471 of_node_put(np);
1472 kfree(arch_data);
1473 return -EINVAL;
1474 }
1475
1476 oiommu = platform_get_drvdata(pdev);
1477 if (!oiommu) {
1478 of_node_put(np);
1479 kfree(arch_data);
1480 return -EINVAL;
1481 }
1482
1483 tmp->iommu_dev = oiommu;
1484
1485 of_node_put(np);
1486 }
1487
1488 /*
1489 * use the first IOMMU alone for the sysfs device linking.
1490 * TODO: Evaluate if a single iommu_group needs to be
1491 * maintained for both IOMMUs
1492 */
1493 oiommu = arch_data->iommu_dev;
1494 ret = iommu_device_link(&oiommu->iommu, dev);
1495 if (ret) {
1496 kfree(arch_data);
1497 return ret;
1498 }
1499
1500 dev->archdata.iommu = arch_data;
1501
1502 /*
1503 * IOMMU group initialization calls into omap_iommu_device_group, which
1504 * needs a valid dev->archdata.iommu pointer
1505 */
1506 group = iommu_group_get_for_dev(dev);
1507 if (IS_ERR(group)) {
1508 iommu_device_unlink(&oiommu->iommu, dev);
1509 dev->archdata.iommu = NULL;
1510 kfree(arch_data);
1511 return PTR_ERR(group);
1512 }
1513 iommu_group_put(group);
1514
1515 return 0;
1516 }
1517
1518 static void omap_iommu_remove_device(struct device *dev)
1519 {
1520 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1521
1522 if (!dev->of_node || !arch_data)
1523 return;
1524
1525 iommu_device_unlink(&arch_data->iommu_dev->iommu, dev);
1526 iommu_group_remove_device(dev);
1527
1528 dev->archdata.iommu = NULL;
1529 kfree(arch_data);
1530
1531 }
1532
1533 static struct iommu_group *omap_iommu_device_group(struct device *dev)
1534 {
1535 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1536 struct iommu_group *group = ERR_PTR(-EINVAL);
1537
1538 if (arch_data->iommu_dev)
1539 group = iommu_group_ref_get(arch_data->iommu_dev->group);
1540
1541 return group;
1542 }
1543
1544 static const struct iommu_ops omap_iommu_ops = {
1545 .domain_alloc = omap_iommu_domain_alloc,
1546 .domain_free = omap_iommu_domain_free,
1547 .attach_dev = omap_iommu_attach_dev,
1548 .detach_dev = omap_iommu_detach_dev,
1549 .map = omap_iommu_map,
1550 .unmap = omap_iommu_unmap,
1551 .iova_to_phys = omap_iommu_iova_to_phys,
1552 .add_device = omap_iommu_add_device,
1553 .remove_device = omap_iommu_remove_device,
1554 .device_group = omap_iommu_device_group,
1555 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
1556 };
1557
1558 static int __init omap_iommu_init(void)
1559 {
1560 struct kmem_cache *p;
1561 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1562 size_t align = 1 << 10; /* L2 pagetable alignement */
1563 struct device_node *np;
1564 int ret;
1565
1566 np = of_find_matching_node(NULL, omap_iommu_of_match);
1567 if (!np)
1568 return 0;
1569
1570 of_node_put(np);
1571
1572 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1573 NULL);
1574 if (!p)
1575 return -ENOMEM;
1576 iopte_cachep = p;
1577
1578 omap_iommu_debugfs_init();
1579
1580 ret = platform_driver_register(&omap_iommu_driver);
1581 if (ret) {
1582 pr_err("%s: failed to register driver\n", __func__);
1583 goto fail_driver;
1584 }
1585
1586 ret = bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1587 if (ret)
1588 goto fail_bus;
1589
1590 return 0;
1591
1592 fail_bus:
1593 platform_driver_unregister(&omap_iommu_driver);
1594 fail_driver:
1595 kmem_cache_destroy(iopte_cachep);
1596 return ret;
1597 }
1598 subsys_initcall(omap_iommu_init);
1599 /* must be ready before omap3isp is probed */
Linux with added FPC-III support