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Linux 4.19.133
[linux/fpc-iii.git] / drivers / media / i2c / ov6650.c
blob33a67a3685e6880966e5377be10394c64046c786
1 /*
2 * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
3 *
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
5 *
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
8 *
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
12 *
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 *
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 */
26
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/v4l2-mediabus.h>
32 #include <linux/module.h>
33
34 #include <media/v4l2-clk.h>
35 #include <media/v4l2-ctrls.h>
36 #include <media/v4l2-device.h>
37
38 /* Register definitions */
39 #define REG_GAIN 0x00 /* range 00 - 3F */
40 #define REG_BLUE 0x01
41 #define REG_RED 0x02
42 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
43 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
44
45 #define REG_BRT 0x06
46
47 #define REG_PIDH 0x0a
48 #define REG_PIDL 0x0b
49
50 #define REG_AECH 0x10
51 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
52 /* [7:6] Input system clock (MHz)*/
53 /* 00=8, 01=12, 10=16, 11=24 */
54 /* [5:0]: Internal Clock Pre-Scaler */
55 #define REG_COMA 0x12 /* [7] Reset */
56 #define REG_COMB 0x13
57 #define REG_COMC 0x14
58 #define REG_COMD 0x15
59 #define REG_COML 0x16
60 #define REG_HSTRT 0x17
61 #define REG_HSTOP 0x18
62 #define REG_VSTRT 0x19
63 #define REG_VSTOP 0x1a
64 #define REG_PSHFT 0x1b
65 #define REG_MIDH 0x1c
66 #define REG_MIDL 0x1d
67 #define REG_HSYNS 0x1e
68 #define REG_HSYNE 0x1f
69 #define REG_COME 0x20
70 #define REG_YOFF 0x21
71 #define REG_UOFF 0x22
72 #define REG_VOFF 0x23
73 #define REG_AEW 0x24
74 #define REG_AEB 0x25
75 #define REG_COMF 0x26
76 #define REG_COMG 0x27
77 #define REG_COMH 0x28
78 #define REG_COMI 0x29
79
80 #define REG_FRARL 0x2b
81 #define REG_COMJ 0x2c
82 #define REG_COMK 0x2d
83 #define REG_AVGY 0x2e
84 #define REG_REF0 0x2f
85 #define REG_REF1 0x30
86 #define REG_REF2 0x31
87 #define REG_FRAJH 0x32
88 #define REG_FRAJL 0x33
89 #define REG_FACT 0x34
90 #define REG_L1AEC 0x35
91 #define REG_AVGU 0x36
92 #define REG_AVGV 0x37
93
94 #define REG_SPCB 0x60
95 #define REG_SPCC 0x61
96 #define REG_GAM1 0x62
97 #define REG_GAM2 0x63
98 #define REG_GAM3 0x64
99 #define REG_SPCD 0x65
100
101 #define REG_SPCE 0x68
102 #define REG_ADCL 0x69
103
104 #define REG_RMCO 0x6c
105 #define REG_GMCO 0x6d
106 #define REG_BMCO 0x6e
107
108
109 /* Register bits, values, etc. */
110 #define OV6650_PIDH 0x66 /* high byte of product ID number */
111 #define OV6650_PIDL 0x50 /* low byte of product ID number */
112 #define OV6650_MIDH 0x7F /* high byte of mfg ID */
113 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
114
115 #define DEF_GAIN 0x00
116 #define DEF_BLUE 0x80
117 #define DEF_RED 0x80
118
119 #define SAT_SHIFT 4
120 #define SAT_MASK (0xf << SAT_SHIFT)
121 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
122
123 #define HUE_EN BIT(5)
124 #define HUE_MASK 0x1f
125 #define DEF_HUE 0x10
126 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
127
128 #define DEF_AECH 0x4D
129
130 #define CLKRC_6MHz 0x00
131 #define CLKRC_12MHz 0x40
132 #define CLKRC_16MHz 0x80
133 #define CLKRC_24MHz 0xc0
134 #define CLKRC_DIV_MASK 0x3f
135 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
136
137 #define COMA_RESET BIT(7)
138 #define COMA_QCIF BIT(5)
139 #define COMA_RAW_RGB BIT(4)
140 #define COMA_RGB BIT(3)
141 #define COMA_BW BIT(2)
142 #define COMA_WORD_SWAP BIT(1)
143 #define COMA_BYTE_SWAP BIT(0)
144 #define DEF_COMA 0x00
145
146 #define COMB_FLIP_V BIT(7)
147 #define COMB_FLIP_H BIT(5)
148 #define COMB_BAND_FILTER BIT(4)
149 #define COMB_AWB BIT(2)
150 #define COMB_AGC BIT(1)
151 #define COMB_AEC BIT(0)
152 #define DEF_COMB 0x5f
153
154 #define COML_ONE_CHANNEL BIT(7)
155
156 #define DEF_HSTRT 0x24
157 #define DEF_HSTOP 0xd4
158 #define DEF_VSTRT 0x04
159 #define DEF_VSTOP 0x94
160
161 #define COMF_HREF_LOW BIT(4)
162
163 #define COMJ_PCLK_RISING BIT(4)
164 #define COMJ_VSYNC_HIGH BIT(0)
165
166 /* supported resolutions */
167 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
168 #define W_CIF (W_QCIF << 1)
169 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
170 #define H_CIF (H_QCIF << 1)
171
172 #define FRAME_RATE_MAX 30
173
174
175 struct ov6650_reg {
176 u8 reg;
177 u8 val;
178 };
179
180 struct ov6650 {
181 struct v4l2_subdev subdev;
182 struct v4l2_ctrl_handler hdl;
183 struct {
184 /* exposure/autoexposure cluster */
185 struct v4l2_ctrl *autoexposure;
186 struct v4l2_ctrl *exposure;
187 };
188 struct {
189 /* gain/autogain cluster */
190 struct v4l2_ctrl *autogain;
191 struct v4l2_ctrl *gain;
192 };
193 struct {
194 /* blue/red/autowhitebalance cluster */
195 struct v4l2_ctrl *autowb;
196 struct v4l2_ctrl *blue;
197 struct v4l2_ctrl *red;
198 };
199 struct v4l2_clk *clk;
200 bool half_scale; /* scale down output by 2 */
201 struct v4l2_rect rect; /* sensor cropping window */
202 unsigned long pclk_limit; /* from host */
203 unsigned long pclk_max; /* from resolution and format */
204 struct v4l2_fract tpf; /* as requested with s_frame_interval */
205 u32 code;
206 };
207
208
209 static u32 ov6650_codes[] = {
210 MEDIA_BUS_FMT_YUYV8_2X8,
211 MEDIA_BUS_FMT_UYVY8_2X8,
212 MEDIA_BUS_FMT_YVYU8_2X8,
213 MEDIA_BUS_FMT_VYUY8_2X8,
214 MEDIA_BUS_FMT_SBGGR8_1X8,
215 MEDIA_BUS_FMT_Y8_1X8,
216 };
217
218 static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
219 .width = W_CIF,
220 .height = H_CIF,
221 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
222 .colorspace = V4L2_COLORSPACE_SRGB,
223 .field = V4L2_FIELD_NONE,
224 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
225 .quantization = V4L2_QUANTIZATION_DEFAULT,
226 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
227 };
228
229 /* read a register */
230 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
231 {
232 int ret;
233 u8 data = reg;
234 struct i2c_msg msg = {
235 .addr = client->addr,
236 .flags = 0,
237 .len = 1,
238 .buf = &data,
239 };
240
241 ret = i2c_transfer(client->adapter, &msg, 1);
242 if (ret < 0)
243 goto err;
244
245 msg.flags = I2C_M_RD;
246 ret = i2c_transfer(client->adapter, &msg, 1);
247 if (ret < 0)
248 goto err;
249
250 *val = data;
251 return 0;
252
253 err:
254 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
255 return ret;
256 }
257
258 /* write a register */
259 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
260 {
261 int ret;
262 unsigned char data[2] = { reg, val };
263 struct i2c_msg msg = {
264 .addr = client->addr,
265 .flags = 0,
266 .len = 2,
267 .buf = data,
268 };
269
270 ret = i2c_transfer(client->adapter, &msg, 1);
271 udelay(100);
272
273 if (ret < 0) {
274 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
275 return ret;
276 }
277 return 0;
278 }
279
280
281 /* Read a register, alter its bits, write it back */
282 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
283 {
284 u8 val;
285 int ret;
286
287 ret = ov6650_reg_read(client, reg, &val);
288 if (ret) {
289 dev_err(&client->dev,
290 "[Read]-Modify-Write of register 0x%02x failed!\n",
291 reg);
292 return ret;
293 }
294
295 val &= ~mask;
296 val |= set;
297
298 ret = ov6650_reg_write(client, reg, val);
299 if (ret)
300 dev_err(&client->dev,
301 "Read-Modify-[Write] of register 0x%02x failed!\n",
302 reg);
303
304 return ret;
305 }
306
307 static struct ov6650 *to_ov6650(const struct i2c_client *client)
308 {
309 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
310 }
311
312 /* Start/Stop streaming from the device */
313 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
314 {
315 return 0;
316 }
317
318 /* Get status of additional camera capabilities */
319 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
320 {
321 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
322 struct v4l2_subdev *sd = &priv->subdev;
323 struct i2c_client *client = v4l2_get_subdevdata(sd);
324 uint8_t reg, reg2;
325 int ret;
326
327 switch (ctrl->id) {
328 case V4L2_CID_AUTOGAIN:
329 ret = ov6650_reg_read(client, REG_GAIN, &reg);
330 if (!ret)
331 priv->gain->val = reg;
332 return ret;
333 case V4L2_CID_AUTO_WHITE_BALANCE:
334 ret = ov6650_reg_read(client, REG_BLUE, &reg);
335 if (!ret)
336 ret = ov6650_reg_read(client, REG_RED, &reg2);
337 if (!ret) {
338 priv->blue->val = reg;
339 priv->red->val = reg2;
340 }
341 return ret;
342 case V4L2_CID_EXPOSURE_AUTO:
343 ret = ov6650_reg_read(client, REG_AECH, &reg);
344 if (!ret)
345 priv->exposure->val = reg;
346 return ret;
347 }
348 return -EINVAL;
349 }
350
351 /* Set status of additional camera capabilities */
352 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
353 {
354 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
355 struct v4l2_subdev *sd = &priv->subdev;
356 struct i2c_client *client = v4l2_get_subdevdata(sd);
357 int ret;
358
359 switch (ctrl->id) {
360 case V4L2_CID_AUTOGAIN:
361 ret = ov6650_reg_rmw(client, REG_COMB,
362 ctrl->val ? COMB_AGC : 0, COMB_AGC);
363 if (!ret && !ctrl->val)
364 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
365 return ret;
366 case V4L2_CID_AUTO_WHITE_BALANCE:
367 ret = ov6650_reg_rmw(client, REG_COMB,
368 ctrl->val ? COMB_AWB : 0, COMB_AWB);
369 if (!ret && !ctrl->val) {
370 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
371 if (!ret)
372 ret = ov6650_reg_write(client, REG_RED,
373 priv->red->val);
374 }
375 return ret;
376 case V4L2_CID_SATURATION:
377 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
378 SAT_MASK);
379 case V4L2_CID_HUE:
380 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
381 HUE_MASK);
382 case V4L2_CID_BRIGHTNESS:
383 return ov6650_reg_write(client, REG_BRT, ctrl->val);
384 case V4L2_CID_EXPOSURE_AUTO:
385 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
386 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
387 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
388 ret = ov6650_reg_write(client, REG_AECH,
389 priv->exposure->val);
390 return ret;
391 case V4L2_CID_GAMMA:
392 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
393 case V4L2_CID_VFLIP:
394 return ov6650_reg_rmw(client, REG_COMB,
395 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
396 case V4L2_CID_HFLIP:
397 return ov6650_reg_rmw(client, REG_COMB,
398 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
399 }
400
401 return -EINVAL;
402 }
403
404 #ifdef CONFIG_VIDEO_ADV_DEBUG
405 static int ov6650_get_register(struct v4l2_subdev *sd,
406 struct v4l2_dbg_register *reg)
407 {
408 struct i2c_client *client = v4l2_get_subdevdata(sd);
409 int ret;
410 u8 val;
411
412 if (reg->reg & ~0xff)
413 return -EINVAL;
414
415 reg->size = 1;
416
417 ret = ov6650_reg_read(client, reg->reg, &val);
418 if (!ret)
419 reg->val = (__u64)val;
420
421 return ret;
422 }
423
424 static int ov6650_set_register(struct v4l2_subdev *sd,
425 const struct v4l2_dbg_register *reg)
426 {
427 struct i2c_client *client = v4l2_get_subdevdata(sd);
428
429 if (reg->reg & ~0xff || reg->val & ~0xff)
430 return -EINVAL;
431
432 return ov6650_reg_write(client, reg->reg, reg->val);
433 }
434 #endif
435
436 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
437 {
438 struct i2c_client *client = v4l2_get_subdevdata(sd);
439 struct ov6650 *priv = to_ov6650(client);
440 int ret = 0;
441
442 if (on)
443 ret = v4l2_clk_enable(priv->clk);
444 else
445 v4l2_clk_disable(priv->clk);
446
447 return ret;
448 }
449
450 static int ov6650_get_selection(struct v4l2_subdev *sd,
451 struct v4l2_subdev_pad_config *cfg,
452 struct v4l2_subdev_selection *sel)
453 {
454 struct i2c_client *client = v4l2_get_subdevdata(sd);
455 struct ov6650 *priv = to_ov6650(client);
456
457 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
458 return -EINVAL;
459
460 switch (sel->target) {
461 case V4L2_SEL_TGT_CROP_BOUNDS:
462 case V4L2_SEL_TGT_CROP_DEFAULT:
463 sel->r.left = DEF_HSTRT << 1;
464 sel->r.top = DEF_VSTRT << 1;
465 sel->r.width = W_CIF;
466 sel->r.height = H_CIF;
467 return 0;
468 case V4L2_SEL_TGT_CROP:
469 sel->r = priv->rect;
470 return 0;
471 default:
472 return -EINVAL;
473 }
474 }
475
476 static int ov6650_set_selection(struct v4l2_subdev *sd,
477 struct v4l2_subdev_pad_config *cfg,
478 struct v4l2_subdev_selection *sel)
479 {
480 struct i2c_client *client = v4l2_get_subdevdata(sd);
481 struct ov6650 *priv = to_ov6650(client);
482 int ret;
483
484 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
485 sel->target != V4L2_SEL_TGT_CROP)
486 return -EINVAL;
487
488 v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1,
489 &sel->r.height, 2, H_CIF, 1, 0);
490 v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1,
491 (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1,
492 &sel->r.top, DEF_VSTRT << 1,
493 (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height,
494 1, 0);
495
496 ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
497 if (!ret) {
498 priv->rect.width += priv->rect.left - sel->r.left;
499 priv->rect.left = sel->r.left;
500 ret = ov6650_reg_write(client, REG_HSTOP,
501 (sel->r.left + sel->r.width) >> 1);
502 }
503 if (!ret) {
504 priv->rect.width = sel->r.width;
505 ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
506 }
507 if (!ret) {
508 priv->rect.height += priv->rect.top - sel->r.top;
509 priv->rect.top = sel->r.top;
510 ret = ov6650_reg_write(client, REG_VSTOP,
511 (sel->r.top + sel->r.height) >> 1);
512 }
513 if (!ret)
514 priv->rect.height = sel->r.height;
515
516 return ret;
517 }
518
519 static int ov6650_get_fmt(struct v4l2_subdev *sd,
520 struct v4l2_subdev_pad_config *cfg,
521 struct v4l2_subdev_format *format)
522 {
523 struct v4l2_mbus_framefmt *mf = &format->format;
524 struct i2c_client *client = v4l2_get_subdevdata(sd);
525 struct ov6650 *priv = to_ov6650(client);
526
527 if (format->pad)
528 return -EINVAL;
529
530 /* initialize response with default media bus frame format */
531 *mf = ov6650_def_fmt;
532
533 /* update media bus format code and frame size */
534 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
535 mf->width = cfg->try_fmt.width;
536 mf->height = cfg->try_fmt.height;
537 mf->code = cfg->try_fmt.code;
538
539 } else {
540 mf->width = priv->rect.width >> priv->half_scale;
541 mf->height = priv->rect.height >> priv->half_scale;
542 mf->code = priv->code;
543 }
544 return 0;
545 }
546
547 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
548 {
549 return width > rect->width >> 1 || height > rect->height >> 1;
550 }
551
552 static u8 to_clkrc(struct v4l2_fract *timeperframe,
553 unsigned long pclk_limit, unsigned long pclk_max)
554 {
555 unsigned long pclk;
556
557 if (timeperframe->numerator && timeperframe->denominator)
558 pclk = pclk_max * timeperframe->denominator /
559 (FRAME_RATE_MAX * timeperframe->numerator);
560 else
561 pclk = pclk_max;
562
563 if (pclk_limit && pclk_limit < pclk)
564 pclk = pclk_limit;
565
566 return (pclk_max - 1) / pclk;
567 }
568
569 /* set the format we will capture in */
570 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
571 {
572 struct i2c_client *client = v4l2_get_subdevdata(sd);
573 struct ov6650 *priv = to_ov6650(client);
574 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
575 struct v4l2_subdev_selection sel = {
576 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
577 .target = V4L2_SEL_TGT_CROP,
578 .r.left = priv->rect.left + (priv->rect.width >> 1) -
579 (mf->width >> (1 - half_scale)),
580 .r.top = priv->rect.top + (priv->rect.height >> 1) -
581 (mf->height >> (1 - half_scale)),
582 .r.width = mf->width << half_scale,
583 .r.height = mf->height << half_scale,
584 };
585 u32 code = mf->code;
586 unsigned long mclk, pclk;
587 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
588 int ret;
589
590 /* select color matrix configuration for given color encoding */
591 switch (code) {
592 case MEDIA_BUS_FMT_Y8_1X8:
593 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
594 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
595 coma_set |= COMA_BW;
596 break;
597 case MEDIA_BUS_FMT_YUYV8_2X8:
598 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
599 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
600 coma_set |= COMA_WORD_SWAP;
601 break;
602 case MEDIA_BUS_FMT_YVYU8_2X8:
603 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
604 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
605 COMA_BYTE_SWAP;
606 break;
607 case MEDIA_BUS_FMT_UYVY8_2X8:
608 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
609 if (half_scale) {
610 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
611 coma_set |= COMA_BYTE_SWAP;
612 } else {
613 coma_mask |= COMA_RGB | COMA_BW;
614 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
615 }
616 break;
617 case MEDIA_BUS_FMT_VYUY8_2X8:
618 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
619 if (half_scale) {
620 coma_mask |= COMA_RGB | COMA_BW;
621 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
622 } else {
623 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
624 coma_set |= COMA_BYTE_SWAP;
625 }
626 break;
627 case MEDIA_BUS_FMT_SBGGR8_1X8:
628 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
629 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
630 coma_set |= COMA_RAW_RGB | COMA_RGB;
631 break;
632 default:
633 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
634 return -EINVAL;
635 }
636
637 if (code == MEDIA_BUS_FMT_Y8_1X8 ||
638 code == MEDIA_BUS_FMT_SBGGR8_1X8) {
639 coml_mask = COML_ONE_CHANNEL;
640 coml_set = 0;
641 priv->pclk_max = 4000000;
642 } else {
643 coml_mask = 0;
644 coml_set = COML_ONE_CHANNEL;
645 priv->pclk_max = 8000000;
646 }
647
648 if (half_scale) {
649 dev_dbg(&client->dev, "max resolution: QCIF\n");
650 coma_set |= COMA_QCIF;
651 priv->pclk_max /= 2;
652 } else {
653 dev_dbg(&client->dev, "max resolution: CIF\n");
654 coma_mask |= COMA_QCIF;
655 }
656
657 clkrc = CLKRC_12MHz;
658 mclk = 12000000;
659 priv->pclk_limit = 1334000;
660 dev_dbg(&client->dev, "using 12MHz input clock\n");
661
662 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
663
664 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
665 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
666 mclk / pclk, 10 * mclk % pclk / pclk);
667
668 ret = ov6650_set_selection(sd, NULL, &sel);
669 if (!ret)
670 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
671 if (!ret)
672 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
673 if (!ret) {
674 priv->half_scale = half_scale;
675
676 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
677 }
678 if (!ret)
679 priv->code = code;
680
681 return ret;
682 }
683
684 static int ov6650_set_fmt(struct v4l2_subdev *sd,
685 struct v4l2_subdev_pad_config *cfg,
686 struct v4l2_subdev_format *format)
687 {
688 struct v4l2_mbus_framefmt *mf = &format->format;
689 struct i2c_client *client = v4l2_get_subdevdata(sd);
690 struct ov6650 *priv = to_ov6650(client);
691
692 if (format->pad)
693 return -EINVAL;
694
695 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
696 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
697 &mf->height, 2, H_CIF, 1, 0);
698
699 switch (mf->code) {
700 case MEDIA_BUS_FMT_Y10_1X10:
701 mf->code = MEDIA_BUS_FMT_Y8_1X8;
702 /* fall through */
703 case MEDIA_BUS_FMT_Y8_1X8:
704 case MEDIA_BUS_FMT_YVYU8_2X8:
705 case MEDIA_BUS_FMT_YUYV8_2X8:
706 case MEDIA_BUS_FMT_VYUY8_2X8:
707 case MEDIA_BUS_FMT_UYVY8_2X8:
708 break;
709 default:
710 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
711 /* fall through */
712 case MEDIA_BUS_FMT_SBGGR8_1X8:
713 break;
714 }
715
716 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
717 /* store media bus format code and frame size in pad config */
718 cfg->try_fmt.width = mf->width;
719 cfg->try_fmt.height = mf->height;
720 cfg->try_fmt.code = mf->code;
721
722 /* return default mbus frame format updated with pad config */
723 *mf = ov6650_def_fmt;
724 mf->width = cfg->try_fmt.width;
725 mf->height = cfg->try_fmt.height;
726 mf->code = cfg->try_fmt.code;
727
728 } else {
729 /* apply new media bus format code and frame size */
730 int ret = ov6650_s_fmt(sd, mf);
731
732 if (ret)
733 return ret;
734
735 /* return default format updated with active size and code */
736 *mf = ov6650_def_fmt;
737 mf->width = priv->rect.width >> priv->half_scale;
738 mf->height = priv->rect.height >> priv->half_scale;
739 mf->code = priv->code;
740 }
741 return 0;
742 }
743
744 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
745 struct v4l2_subdev_pad_config *cfg,
746 struct v4l2_subdev_mbus_code_enum *code)
747 {
748 if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
749 return -EINVAL;
750
751 code->code = ov6650_codes[code->index];
752 return 0;
753 }
754
755 static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
756 struct v4l2_subdev_frame_interval *ival)
757 {
758 struct i2c_client *client = v4l2_get_subdevdata(sd);
759 struct ov6650 *priv = to_ov6650(client);
760
761 ival->interval.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
762 priv->pclk_limit, priv->pclk_max));
763 ival->interval.denominator = FRAME_RATE_MAX;
764
765 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
766 ival->interval.numerator, ival->interval.denominator);
767
768 return 0;
769 }
770
771 static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
772 struct v4l2_subdev_frame_interval *ival)
773 {
774 struct i2c_client *client = v4l2_get_subdevdata(sd);
775 struct ov6650 *priv = to_ov6650(client);
776 struct v4l2_fract *tpf = &ival->interval;
777 int div, ret;
778 u8 clkrc;
779
780 if (tpf->numerator == 0 || tpf->denominator == 0)
781 div = 1; /* Reset to full rate */
782 else
783 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
784
785 if (div == 0)
786 div = 1;
787 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
788 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
789
790 /*
791 * Keep result to be used as tpf limit
792 * for subseqent clock divider calculations
793 */
794 priv->tpf.numerator = div;
795 priv->tpf.denominator = FRAME_RATE_MAX;
796
797 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
798
799 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
800 if (!ret) {
801 tpf->numerator = GET_CLKRC_DIV(clkrc);
802 tpf->denominator = FRAME_RATE_MAX;
803 }
804
805 return ret;
806 }
807
808 /* Soft reset the camera. This has nothing to do with the RESET pin! */
809 static int ov6650_reset(struct i2c_client *client)
810 {
811 int ret;
812
813 dev_dbg(&client->dev, "reset\n");
814
815 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
816 if (ret)
817 dev_err(&client->dev,
818 "An error occurred while entering soft reset!\n");
819
820 return ret;
821 }
822
823 /* program default register values */
824 static int ov6650_prog_dflt(struct i2c_client *client)
825 {
826 int ret;
827
828 dev_dbg(&client->dev, "initializing\n");
829
830 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
831 if (!ret)
832 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
833
834 return ret;
835 }
836
837 static int ov6650_video_probe(struct i2c_client *client)
838 {
839 struct ov6650 *priv = to_ov6650(client);
840 u8 pidh, pidl, midh, midl;
841 int ret;
842
843 priv->clk = v4l2_clk_get(&client->dev, NULL);
844 if (IS_ERR(priv->clk)) {
845 ret = PTR_ERR(priv->clk);
846 dev_err(&client->dev, "v4l2_clk request err: %d\n", ret);
847 return ret;
848 }
849
850 ret = ov6650_s_power(&priv->subdev, 1);
851 if (ret < 0)
852 goto eclkput;
853
854 msleep(20);
855
856 /*
857 * check and show product ID and manufacturer ID
858 */
859 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
860 if (!ret)
861 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
862 if (!ret)
863 ret = ov6650_reg_read(client, REG_MIDH, &midh);
864 if (!ret)
865 ret = ov6650_reg_read(client, REG_MIDL, &midl);
866
867 if (ret)
868 goto done;
869
870 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
871 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
872 pidh, pidl);
873 ret = -ENODEV;
874 goto done;
875 }
876
877 dev_info(&client->dev,
878 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
879 pidh, pidl, midh, midl);
880
881 ret = ov6650_reset(client);
882 if (!ret)
883 ret = ov6650_prog_dflt(client);
884 if (!ret)
885 ret = v4l2_ctrl_handler_setup(&priv->hdl);
886
887 done:
888 ov6650_s_power(&priv->subdev, 0);
889 if (!ret)
890 return 0;
891 eclkput:
892 v4l2_clk_put(priv->clk);
893
894 return ret;
895 }
896
897 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
898 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
899 .s_ctrl = ov6550_s_ctrl,
900 };
901
902 static const struct v4l2_subdev_core_ops ov6650_core_ops = {
903 #ifdef CONFIG_VIDEO_ADV_DEBUG
904 .g_register = ov6650_get_register,
905 .s_register = ov6650_set_register,
906 #endif
907 .s_power = ov6650_s_power,
908 };
909
910 /* Request bus settings on camera side */
911 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
912 struct v4l2_mbus_config *cfg)
913 {
914
915 cfg->flags = V4L2_MBUS_MASTER |
916 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
917 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
918 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
919 V4L2_MBUS_DATA_ACTIVE_HIGH;
920 cfg->type = V4L2_MBUS_PARALLEL;
921
922 return 0;
923 }
924
925 /* Alter bus settings on camera side */
926 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
927 const struct v4l2_mbus_config *cfg)
928 {
929 struct i2c_client *client = v4l2_get_subdevdata(sd);
930 int ret;
931
932 if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
933 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
934 else
935 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
936 if (ret)
937 return ret;
938
939 if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
940 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
941 else
942 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
943 if (ret)
944 return ret;
945
946 if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
947 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
948 else
949 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
950
951 return ret;
952 }
953
954 static const struct v4l2_subdev_video_ops ov6650_video_ops = {
955 .s_stream = ov6650_s_stream,
956 .g_frame_interval = ov6650_g_frame_interval,
957 .s_frame_interval = ov6650_s_frame_interval,
958 .g_mbus_config = ov6650_g_mbus_config,
959 .s_mbus_config = ov6650_s_mbus_config,
960 };
961
962 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
963 .enum_mbus_code = ov6650_enum_mbus_code,
964 .get_selection = ov6650_get_selection,
965 .set_selection = ov6650_set_selection,
966 .get_fmt = ov6650_get_fmt,
967 .set_fmt = ov6650_set_fmt,
968 };
969
970 static const struct v4l2_subdev_ops ov6650_subdev_ops = {
971 .core = &ov6650_core_ops,
972 .video = &ov6650_video_ops,
973 .pad = &ov6650_pad_ops,
974 };
975
976 /*
977 * i2c_driver function
978 */
979 static int ov6650_probe(struct i2c_client *client,
980 const struct i2c_device_id *did)
981 {
982 struct ov6650 *priv;
983 int ret;
984
985 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
986 if (!priv)
987 return -ENOMEM;
988
989 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
990 v4l2_ctrl_handler_init(&priv->hdl, 13);
991 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
992 V4L2_CID_VFLIP, 0, 1, 1, 0);
993 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
994 V4L2_CID_HFLIP, 0, 1, 1, 0);
995 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
996 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
997 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
998 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
999 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1000 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1001 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1002 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1003 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1004 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1005 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1006 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1007 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1008 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1009 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1010 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1011 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1012 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1013 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1014 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1015 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1016 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1017 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1018
1019 priv->subdev.ctrl_handler = &priv->hdl;
1020 if (priv->hdl.error)
1021 return priv->hdl.error;
1022
1023 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1024 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1025 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1026 V4L2_EXPOSURE_MANUAL, true);
1027
1028 priv->rect.left = DEF_HSTRT << 1;
1029 priv->rect.top = DEF_VSTRT << 1;
1030 priv->rect.width = W_CIF;
1031 priv->rect.height = H_CIF;
1032 priv->half_scale = false;
1033 priv->code = MEDIA_BUS_FMT_YUYV8_2X8;
1034
1035 ret = ov6650_video_probe(client);
1036 if (ret)
1037 v4l2_ctrl_handler_free(&priv->hdl);
1038
1039 return ret;
1040 }
1041
1042 static int ov6650_remove(struct i2c_client *client)
1043 {
1044 struct ov6650 *priv = to_ov6650(client);
1045
1046 v4l2_clk_put(priv->clk);
1047 v4l2_device_unregister_subdev(&priv->subdev);
1048 v4l2_ctrl_handler_free(&priv->hdl);
1049 return 0;
1050 }
1051
1052 static const struct i2c_device_id ov6650_id[] = {
1053 { "ov6650", 0 },
1054 { }
1055 };
1056 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1057
1058 static struct i2c_driver ov6650_i2c_driver = {
1059 .driver = {
1060 .name = "ov6650",
1061 },
1062 .probe = ov6650_probe,
1063 .remove = ov6650_remove,
1064 .id_table = ov6650_id,
1065 };
1066
1067 module_i2c_driver(ov6650_i2c_driver);
1068
1069 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1070 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1071 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support