drivers/media/pci/cobalt/cobalt-driver.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  cobalt driver internal defines and structures
   4  *
   5  *  Derived from cx18-driver.h
   6  *
   7  *  Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
   8  *  All rights reserved.
   9  */
  10
  11 #ifndef COBALT_DRIVER_H
  12 #define COBALT_DRIVER_H
  13
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/i2c.h>
  18 #include <linux/list.h>
  19 #include <linux/workqueue.h>
  20 #include <linux/mutex.h>
  21
  22 #include <media/v4l2-common.h>
  23 #include <media/v4l2-ioctl.h>
  24 #include <media/v4l2-device.h>
  25 #include <media/v4l2-fh.h>
  26 #include <media/videobuf2-v4l2.h>
  27 #include <media/videobuf2-dma-sg.h>
  28
  29 #include "m00233_video_measure_memmap_package.h"
  30 #include "m00235_fdma_packer_memmap_package.h"
  31 #include "m00389_cvi_memmap_package.h"
  32 #include "m00460_evcnt_memmap_package.h"
  33 #include "m00473_freewheel_memmap_package.h"
  34 #include "m00479_clk_loss_detector_memmap_package.h"
  35 #include "m00514_syncgen_flow_evcnt_memmap_package.h"
  36
  37 /* System device ID */
  38 #define PCI_DEVICE_ID_COBALT    0x2732
  39
  40 /* Number of cobalt device nodes. */
  41 #define COBALT_NUM_INPUTS       4
  42 #define COBALT_NUM_NODES        6
  43
  44 /* Number of cobalt device streams. */
  45 #define COBALT_NUM_STREAMS      12
  46
  47 #define COBALT_HSMA_IN_NODE     4
  48 #define COBALT_HSMA_OUT_NODE    5
  49
  50 /* Cobalt audio streams */
  51 #define COBALT_AUDIO_IN_STREAM  6
  52 #define COBALT_AUDIO_OUT_STREAM 11
  53
  54 /* DMA stuff */
  55 #define DMA_CHANNELS_MAX        16
  56
  57 /* i2c stuff */
  58 #define I2C_CLIENTS_MAX         16
  59 #define COBALT_NUM_ADAPTERS     5
  60
  61 #define COBALT_CLK              50000000
  62
  63 /* System status register */
  64 #define COBALT_SYSSTAT_DIP0_MSK                 (1 << 0)
  65 #define COBALT_SYSSTAT_DIP1_MSK                 (1 << 1)
  66 #define COBALT_SYSSTAT_HSMA_PRSNTN_MSK          (1 << 2)
  67 #define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK        (1 << 3)
  68 #define COBALT_SYSSTAT_VI0_5V_MSK               (1 << 4)
  69 #define COBALT_SYSSTAT_VI0_INT1_MSK             (1 << 5)
  70 #define COBALT_SYSSTAT_VI0_INT2_MSK             (1 << 6)
  71 #define COBALT_SYSSTAT_VI0_LOST_DATA_MSK        (1 << 7)
  72 #define COBALT_SYSSTAT_VI1_5V_MSK               (1 << 8)
  73 #define COBALT_SYSSTAT_VI1_INT1_MSK             (1 << 9)
  74 #define COBALT_SYSSTAT_VI1_INT2_MSK             (1 << 10)
  75 #define COBALT_SYSSTAT_VI1_LOST_DATA_MSK        (1 << 11)
  76 #define COBALT_SYSSTAT_VI2_5V_MSK               (1 << 12)
  77 #define COBALT_SYSSTAT_VI2_INT1_MSK             (1 << 13)
  78 #define COBALT_SYSSTAT_VI2_INT2_MSK             (1 << 14)
  79 #define COBALT_SYSSTAT_VI2_LOST_DATA_MSK        (1 << 15)
  80 #define COBALT_SYSSTAT_VI3_5V_MSK               (1 << 16)
  81 #define COBALT_SYSSTAT_VI3_INT1_MSK             (1 << 17)
  82 #define COBALT_SYSSTAT_VI3_INT2_MSK             (1 << 18)
  83 #define COBALT_SYSSTAT_VI3_LOST_DATA_MSK        (1 << 19)
  84 #define COBALT_SYSSTAT_VIHSMA_5V_MSK            (1 << 20)
  85 #define COBALT_SYSSTAT_VIHSMA_INT1_MSK          (1 << 21)
  86 #define COBALT_SYSSTAT_VIHSMA_INT2_MSK          (1 << 22)
  87 #define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK     (1 << 23)
  88 #define COBALT_SYSSTAT_VOHSMA_INT1_MSK          (1 << 24)
  89 #define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK    (1 << 25)
  90 #define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK     (1 << 26)
  91 #define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK       (1 << 28)
  92 #define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK     (1 << 29)
  93 #define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK    (1 << 30)
  94 #define COBALT_SYSSTAT_PCIE_SMBCLK_MSK          (1 << 31)
  95
  96 /* Cobalt memory map */
  97 #define COBALT_I2C_0_BASE                       0x0
  98 #define COBALT_I2C_1_BASE                       0x080
  99 #define COBALT_I2C_2_BASE                       0x100
 100 #define COBALT_I2C_3_BASE                       0x180
 101 #define COBALT_I2C_HSMA_BASE                    0x200
 102
 103 #define COBALT_SYS_CTRL_BASE                    0x400
 104 #define COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT      1
 105 #define COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(n)  (4 + 4 * (n))
 106 #define COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(n)   (5 + 4 * (n))
 107 #define COBALT_SYS_CTRL_HPD_TO_CONNECTOR_BIT(n) (6 + 4 * (n))
 108 #define COBALT_SYS_CTRL_AUDIO_IPP_RESETN_BIT(n) (7 + 4 * (n))
 109 #define COBALT_SYS_CTRL_PWRDN0_TO_HSMA_TX_BIT   24
 110 #define COBALT_SYS_CTRL_VIDEO_TX_RESETN_BIT     25
 111 #define COBALT_SYS_CTRL_AUDIO_OPP_RESETN_BIT    27
 112
 113 #define COBALT_SYS_STAT_BASE                    0x500
 114 #define COBALT_SYS_STAT_MASK                    (COBALT_SYS_STAT_BASE + 0x08)
 115 #define COBALT_SYS_STAT_EDGE                    (COBALT_SYS_STAT_BASE + 0x0c)
 116
 117 #define COBALT_HDL_INFO_BASE                    0x4800
 118 #define COBALT_HDL_INFO_SIZE                    0x200
 119
 120 #define COBALT_VID_BASE                         0x10000
 121 #define COBALT_VID_SIZE                         0x1000
 122
 123 #define COBALT_CVI(cobalt, c) \
 124         (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE)
 125 #define COBALT_CVI_VMR(cobalt, c) \
 126         (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x100)
 127 #define COBALT_CVI_EVCNT(cobalt, c) \
 128         (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x200)
 129 #define COBALT_CVI_FREEWHEEL(cobalt, c) \
 130         (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x300)
 131 #define COBALT_CVI_CLK_LOSS(cobalt, c) \
 132         (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x400)
 133 #define COBALT_CVI_PACKER(cobalt, c) \
 134         (cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x500)
 135
 136 #define COBALT_TX_BASE(cobalt) (cobalt->bar1 + COBALT_VID_BASE + 0x5000)
 137
 138 #define DMA_INTERRUPT_STATUS_REG                0x08
 139
 140 #define COBALT_HDL_SEARCH_STR                   "** HDL version info **"
 141
 142 /* Cobalt CPU bus interface */
 143 #define COBALT_BUS_BAR1_BASE                    0x600
 144 #define COBALT_BUS_SRAM_BASE                    0x0
 145 #define COBALT_BUS_CPLD_BASE                    0x00600000
 146 #define COBALT_BUS_FLASH_BASE                   0x08000000
 147
 148 /* FDMA to PCIe packing */
 149 #define COBALT_BYTES_PER_PIXEL_YUYV             2
 150 #define COBALT_BYTES_PER_PIXEL_RGB24            3
 151 #define COBALT_BYTES_PER_PIXEL_RGB32            4
 152
 153 /* debugging */
 154 extern int cobalt_debug;
 155 extern int cobalt_ignore_err;
 156
 157 #define cobalt_err(fmt, arg...)  v4l2_err(&cobalt->v4l2_dev, fmt, ## arg)
 158 #define cobalt_warn(fmt, arg...) v4l2_warn(&cobalt->v4l2_dev, fmt, ## arg)
 159 #define cobalt_info(fmt, arg...) v4l2_info(&cobalt->v4l2_dev, fmt, ## arg)
 160 #define cobalt_dbg(level, fmt, arg...) \
 161         v4l2_dbg(level, cobalt_debug, &cobalt->v4l2_dev, fmt, ## arg)
 162
 163 struct cobalt;
 164 struct cobalt_i2c_regs;
 165
 166 /* Per I2C bus private algo callback data */
 167 struct cobalt_i2c_data {
 168         struct cobalt *cobalt;
 169         struct cobalt_i2c_regs __iomem *regs;
 170 };
 171
 172 struct pci_consistent_buffer {
 173         void *virt;
 174         dma_addr_t bus;
 175         size_t bytes;
 176 };
 177
 178 struct sg_dma_desc_info {
 179         void *virt;
 180         dma_addr_t bus;
 181         unsigned size;
 182         void *last_desc_virt;
 183         struct device *dev;
 184 };
 185
 186 #define COBALT_MAX_WIDTH                        1920
 187 #define COBALT_MAX_HEIGHT                       1200
 188 #define COBALT_MAX_BPP                          3
 189 #define COBALT_MAX_FRAMESZ \
 190         (COBALT_MAX_WIDTH * COBALT_MAX_HEIGHT * COBALT_MAX_BPP)
 191
 192 #define NR_BUFS                                 VIDEO_MAX_FRAME
 193
 194 #define COBALT_STREAM_FL_DMA_IRQ                0
 195 #define COBALT_STREAM_FL_ADV_IRQ                1
 196
 197 struct cobalt_buffer {
 198         struct vb2_v4l2_buffer vb;
 199         struct list_head list;
 200 };
 201
 202 static inline
 203 struct cobalt_buffer *to_cobalt_buffer(struct vb2_v4l2_buffer *vb2)
 204 {
 205         return container_of(vb2, struct cobalt_buffer, vb);
 206 }
 207
 208 struct cobalt_stream {
 209         struct video_device vdev;
 210         struct vb2_queue q;
 211         struct list_head bufs;
 212         struct i2c_adapter *i2c_adap;
 213         struct v4l2_subdev *sd;
 214         struct mutex lock;
 215         spinlock_t irqlock;
 216         struct v4l2_dv_timings timings;
 217         u32 input;
 218         u32 pad_source;
 219         u32 width, height, bpp;
 220         u32 stride;
 221         u32 pixfmt;
 222         u32 sequence;
 223         u32 colorspace;
 224         u32 xfer_func;
 225         u32 ycbcr_enc;
 226         u32 quantization;
 227
 228         u8 dma_channel;
 229         int video_channel;
 230         unsigned dma_fifo_mask;
 231         unsigned adv_irq_mask;
 232         struct sg_dma_desc_info dma_desc_info[NR_BUFS];
 233         unsigned long flags;
 234         bool unstable_frame;
 235         bool enable_cvi;
 236         bool enable_freewheel;
 237         unsigned skip_first_frames;
 238         bool is_output;
 239         bool is_audio;
 240         bool is_dummy;
 241
 242         struct cobalt *cobalt;
 243         struct snd_cobalt_card *alsa;
 244 };
 245
 246 struct snd_cobalt_card;
 247
 248 /* Struct to hold info about cobalt cards */
 249 struct cobalt {
 250         int instance;
 251         struct pci_dev *pci_dev;
 252         struct v4l2_device v4l2_dev;
 253
 254         void __iomem *bar0, *bar1;
 255
 256         u8 card_rev;
 257         u16 device_id;
 258
 259         /* device nodes */
 260         struct cobalt_stream streams[DMA_CHANNELS_MAX];
 261         struct i2c_adapter i2c_adap[COBALT_NUM_ADAPTERS];
 262         struct cobalt_i2c_data i2c_data[COBALT_NUM_ADAPTERS];
 263         bool have_hsma_rx;
 264         bool have_hsma_tx;
 265
 266         /* irq */
 267         struct workqueue_struct *irq_work_queues;
 268         struct work_struct irq_work_queue;              /* work entry */
 269         /* irq counters */
 270         u32 irq_adv1;
 271         u32 irq_adv2;
 272         u32 irq_advout;
 273         u32 irq_dma_tot;
 274         u32 irq_dma[COBALT_NUM_STREAMS];
 275         u32 irq_none;
 276         u32 irq_full_fifo;
 277
 278         /* omnitek dma */
 279         int dma_channels;
 280         int first_fifo_channel;
 281         bool pci_32_bit;
 282
 283         char hdl_info[COBALT_HDL_INFO_SIZE];
 284
 285         /* NOR flash */
 286         struct mtd_info *mtd;
 287 };
 288
 289 static inline struct cobalt *to_cobalt(struct v4l2_device *v4l2_dev)
 290 {
 291         return container_of(v4l2_dev, struct cobalt, v4l2_dev);
 292 }
 293
 294 static inline void cobalt_write_bar0(struct cobalt *cobalt, u32 reg, u32 val)
 295 {
 296         iowrite32(val, cobalt->bar0 + reg);
 297 }
 298
 299 static inline u32 cobalt_read_bar0(struct cobalt *cobalt, u32 reg)
 300 {
 301         return ioread32(cobalt->bar0 + reg);
 302 }
 303
 304 static inline void cobalt_write_bar1(struct cobalt *cobalt, u32 reg, u32 val)
 305 {
 306         iowrite32(val, cobalt->bar1 + reg);
 307 }
 308
 309 static inline u32 cobalt_read_bar1(struct cobalt *cobalt, u32 reg)
 310 {
 311         return ioread32(cobalt->bar1 + reg);
 312 }
 313
 314 static inline u32 cobalt_g_sysctrl(struct cobalt *cobalt)
 315 {
 316         return cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
 317 }
 318
 319 static inline void cobalt_s_bit_sysctrl(struct cobalt *cobalt,
 320                                         int bit, int val)
 321 {
 322         u32 ctrl = cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
 323
 324         cobalt_write_bar1(cobalt, COBALT_SYS_CTRL_BASE,
 325                         (ctrl & ~(1UL << bit)) | (val << bit));
 326 }
 327
 328 static inline u32 cobalt_g_sysstat(struct cobalt *cobalt)
 329 {
 330         return cobalt_read_bar1(cobalt, COBALT_SYS_STAT_BASE);
 331 }
 332
 333 #define ADRS_REG (bar1 + COBALT_BUS_BAR1_BASE + 0)
 334 #define LOWER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 4)
 335 #define UPPER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 6)
 336
 337 static inline u32 cobalt_bus_read32(void __iomem *bar1, u32 bus_adrs)
 338 {
 339         iowrite32(bus_adrs, ADRS_REG);
 340         return ioread32(LOWER_DATA);
 341 }
 342
 343 static inline void cobalt_bus_write16(void __iomem *bar1,
 344                                       u32 bus_adrs, u16 data)
 345 {
 346         iowrite32(bus_adrs, ADRS_REG);
 347         if (bus_adrs & 2)
 348                 iowrite16(data, UPPER_DATA);
 349         else
 350                 iowrite16(data, LOWER_DATA);
 351 }
 352
 353 static inline void cobalt_bus_write32(void __iomem *bar1,
 354                                       u32 bus_adrs, u16 data)
 355 {
 356         iowrite32(bus_adrs, ADRS_REG);
 357         if (bus_adrs & 2)
 358                 iowrite32(data, UPPER_DATA);
 359         else
 360                 iowrite32(data, LOWER_DATA);
 361 }
 362
 363 /*==============Prototypes==================*/
 364
 365 void cobalt_pcie_status_show(struct cobalt *cobalt);
 366
 367 #endif