drivers/media/pci/tw5864/tw5864.h

   1 /*
   2  *  TW5864 driver  - common header file
   3  *
   4  *  Copyright (C) 2016 Bluecherry, LLC <maintainers@bluecherrydvr.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  */
  16
  17 #include <linux/pci.h>
  18 #include <linux/videodev2.h>
  19 #include <linux/notifier.h>
  20 #include <linux/delay.h>
  21 #include <linux/mutex.h>
  22 #include <linux/io.h>
  23 #include <linux/interrupt.h>
  24
  25 #include <media/v4l2-common.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/v4l2-ctrls.h>
  28 #include <media/v4l2-device.h>
  29 #include <media/videobuf2-dma-sg.h>
  30
  31 #include "tw5864-reg.h"
  32
  33 #define PCI_DEVICE_ID_TECHWELL_5864 0x5864
  34
  35 #define TW5864_NORMS V4L2_STD_ALL
  36
  37 /* ----------------------------------------------------------- */
  38 /* card configuration   */
  39
  40 #define TW5864_INPUTS 4
  41
  42 /* The TW5864 uses 192 (16x12) detection cells in full screen for motion
  43  * detection. Each detection cell is composed of 44 pixels and 20 lines for
  44  * NTSC and 24 lines for PAL.
  45  */
  46 #define MD_CELLS_HOR 16
  47 #define MD_CELLS_VERT 12
  48 #define MD_CELLS (MD_CELLS_HOR * MD_CELLS_VERT)
  49
  50 #define H264_VLC_BUF_SIZE 0x80000
  51 #define H264_MV_BUF_SIZE 0x2000 /* device writes 5396 bytes */
  52 #define QP_VALUE 28
  53 #define MAX_GOP_SIZE 255
  54 #define GOP_SIZE MAX_GOP_SIZE
  55
  56 enum resolution {
  57         D1 = 1,
  58         HD1 = 2, /* half d1 - 360x(240|288) */
  59         CIF = 3,
  60         QCIF = 4,
  61 };
  62
  63 /* ----------------------------------------------------------- */
  64 /* device / file handle status                                 */
  65
  66 struct tw5864_dev; /* forward delclaration */
  67
  68 /* buffer for one video/vbi/ts frame */
  69 struct tw5864_buf {
  70         struct vb2_v4l2_buffer vb;
  71         struct list_head list;
  72
  73         unsigned int size;
  74 };
  75
  76 struct tw5864_dma_buf {
  77         void *addr;
  78         dma_addr_t dma_addr;
  79 };
  80
  81 enum tw5864_vid_std {
  82         STD_NTSC = 0, /* NTSC (M) */
  83         STD_PAL = 1, /* PAL (B, D, G, H, I) */
  84         STD_SECAM = 2, /* SECAM */
  85         STD_NTSC443 = 3, /* NTSC4.43 */
  86         STD_PAL_M = 4, /* PAL (M) */
  87         STD_PAL_CN = 5, /* PAL (CN) */
  88         STD_PAL_60 = 6, /* PAL 60 */
  89         STD_INVALID = 7,
  90         STD_AUTO = 7,
  91 };
  92
  93 struct tw5864_input {
  94         int nr; /* input number */
  95         struct tw5864_dev *root;
  96         struct mutex lock; /* used for vidq and vdev */
  97         spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */
  98         struct video_device vdev;
  99         struct v4l2_ctrl_handler hdl;
 100         struct vb2_queue vidq;
 101         struct list_head active;
 102         enum resolution resolution;
 103         unsigned int width, height;
 104         unsigned int frame_seqno;
 105         unsigned int frame_gop_seqno;
 106         unsigned int h264_idr_pic_id;
 107         int enabled;
 108         enum tw5864_vid_std std;
 109         v4l2_std_id v4l2_std;
 110         int tail_nb_bits;
 111         u8 tail;
 112         u8 *buf_cur_ptr;
 113         int buf_cur_space_left;
 114
 115         u32 reg_interlacing;
 116         u32 reg_vlc;
 117         u32 reg_dsp_codec;
 118         u32 reg_dsp;
 119         u32 reg_emu;
 120         u32 reg_dsp_qp;
 121         u32 reg_dsp_ref_mvp_lambda;
 122         u32 reg_dsp_i4x4_weight;
 123         u32 buf_id;
 124
 125         struct tw5864_buf *vb;
 126
 127         struct v4l2_ctrl *md_threshold_grid_ctrl;
 128         u16 md_threshold_grid_values[12 * 16];
 129         int qp;
 130         int gop;
 131
 132         /*
 133          * In (1/MAX_FPS) units.
 134          * For max FPS (default), set to 1.
 135          * For 1 FPS, set to e.g. 32.
 136          */
 137         int frame_interval;
 138         unsigned long new_frame_deadline;
 139 };
 140
 141 struct tw5864_h264_frame {
 142         struct tw5864_dma_buf vlc;
 143         struct tw5864_dma_buf mv;
 144         int vlc_len;
 145         u32 checksum;
 146         struct tw5864_input *input;
 147         u64 timestamp;
 148         unsigned int seqno;
 149         unsigned int gop_seqno;
 150 };
 151
 152 /* global device status */
 153 struct tw5864_dev {
 154         spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */
 155         struct v4l2_device v4l2_dev;
 156         struct tw5864_input inputs[TW5864_INPUTS];
 157 #define H264_BUF_CNT 4
 158         struct tw5864_h264_frame h264_buf[H264_BUF_CNT];
 159         int h264_buf_r_index;
 160         int h264_buf_w_index;
 161
 162         struct tasklet_struct tasklet;
 163
 164         int encoder_busy;
 165         /* Input number to check next for ready raw picture (in RR fashion) */
 166         int next_input;
 167
 168         /* pci i/o */
 169         char name[64];
 170         struct pci_dev *pci;
 171         void __iomem *mmio;
 172         u32 irqmask;
 173 };
 174
 175 #define tw_readl(reg) readl(dev->mmio + reg)
 176 #define tw_mask_readl(reg, mask) \
 177         (tw_readl(reg) & (mask))
 178 #define tw_mask_shift_readl(reg, mask, shift) \
 179         (tw_mask_readl((reg), ((mask) << (shift))) >> (shift))
 180
 181 #define tw_writel(reg, value) writel((value), dev->mmio + reg)
 182 #define tw_mask_writel(reg, mask, value) \
 183         tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask)))
 184 #define tw_mask_shift_writel(reg, mask, shift, value) \
 185         tw_mask_writel((reg), ((mask) << (shift)), ((value) << (shift)))
 186
 187 #define tw_setl(reg, bit) tw_writel((reg), tw_readl(reg) | (bit))
 188 #define tw_clearl(reg, bit) tw_writel((reg), tw_readl(reg) & ~(bit))
 189
 190 u8 tw5864_indir_readb(struct tw5864_dev *dev, u16 addr);
 191 #define tw_indir_readb(addr) tw5864_indir_readb(dev, addr)
 192 void tw5864_indir_writeb(struct tw5864_dev *dev, u16 addr, u8 data);
 193 #define tw_indir_writeb(addr, data) tw5864_indir_writeb(dev, addr, data)
 194
 195 void tw5864_irqmask_apply(struct tw5864_dev *dev);
 196 int tw5864_video_init(struct tw5864_dev *dev, int *video_nr);
 197 void tw5864_video_fini(struct tw5864_dev *dev);
 198 void tw5864_prepare_frame_headers(struct tw5864_input *input);
 199 void tw5864_h264_put_stream_header(u8 **buf, size_t *space_left, int qp,
 200                                    int width, int height);
 201 void tw5864_h264_put_slice_header(u8 **buf, size_t *space_left,
 202                                   unsigned int idr_pic_id,
 203                                   unsigned int frame_gop_seqno,
 204                                   int *tail_nb_bits, u8 *tail);
 205 void tw5864_request_encoded_frame(struct tw5864_input *input);