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Linux 4.19.133
[linux/fpc-iii.git] / drivers / media / platform / stm32 / stm32-dcmi.c
blob18d0b5641789436536b07ce838890bf968201a94
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STM32 Digital Camera Memory Interface
4 *
5 * Copyright (C) STMicroelectronics SA 2017
6 * Authors: Yannick Fertre <yannick.fertre@st.com>
7 * Hugues Fruchet <hugues.fruchet@st.com>
8 * for STMicroelectronics.
9 *
10 * This driver is based on atmel_isi.c
11 *
12 */
13
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/dmaengine.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_graph.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/reset.h>
29 #include <linux/videodev2.h>
30
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-dev.h>
33 #include <media/v4l2-device.h>
34 #include <media/v4l2-event.h>
35 #include <media/v4l2-fwnode.h>
36 #include <media/v4l2-image-sizes.h>
37 #include <media/v4l2-ioctl.h>
38 #include <media/v4l2-rect.h>
39 #include <media/videobuf2-dma-contig.h>
40
41 #define DRV_NAME "stm32-dcmi"
42
43 /* Registers offset for DCMI */
44 #define DCMI_CR 0x00 /* Control Register */
45 #define DCMI_SR 0x04 /* Status Register */
46 #define DCMI_RIS 0x08 /* Raw Interrupt Status register */
47 #define DCMI_IER 0x0C /* Interrupt Enable Register */
48 #define DCMI_MIS 0x10 /* Masked Interrupt Status register */
49 #define DCMI_ICR 0x14 /* Interrupt Clear Register */
50 #define DCMI_ESCR 0x18 /* Embedded Synchronization Code Register */
51 #define DCMI_ESUR 0x1C /* Embedded Synchronization Unmask Register */
52 #define DCMI_CWSTRT 0x20 /* Crop Window STaRT */
53 #define DCMI_CWSIZE 0x24 /* Crop Window SIZE */
54 #define DCMI_DR 0x28 /* Data Register */
55 #define DCMI_IDR 0x2C /* IDentifier Register */
56
57 /* Bits definition for control register (DCMI_CR) */
58 #define CR_CAPTURE BIT(0)
59 #define CR_CM BIT(1)
60 #define CR_CROP BIT(2)
61 #define CR_JPEG BIT(3)
62 #define CR_ESS BIT(4)
63 #define CR_PCKPOL BIT(5)
64 #define CR_HSPOL BIT(6)
65 #define CR_VSPOL BIT(7)
66 #define CR_FCRC_0 BIT(8)
67 #define CR_FCRC_1 BIT(9)
68 #define CR_EDM_0 BIT(10)
69 #define CR_EDM_1 BIT(11)
70 #define CR_ENABLE BIT(14)
71
72 /* Bits definition for status register (DCMI_SR) */
73 #define SR_HSYNC BIT(0)
74 #define SR_VSYNC BIT(1)
75 #define SR_FNE BIT(2)
76
77 /*
78 * Bits definition for interrupt registers
79 * (DCMI_RIS, DCMI_IER, DCMI_MIS, DCMI_ICR)
80 */
81 #define IT_FRAME BIT(0)
82 #define IT_OVR BIT(1)
83 #define IT_ERR BIT(2)
84 #define IT_VSYNC BIT(3)
85 #define IT_LINE BIT(4)
86
87 enum state {
88 STOPPED = 0,
89 WAIT_FOR_BUFFER,
90 RUNNING,
91 };
92
93 #define MIN_WIDTH 16U
94 #define MAX_WIDTH 2592U
95 #define MIN_HEIGHT 16U
96 #define MAX_HEIGHT 2592U
97
98 #define TIMEOUT_MS 1000
99
100 struct dcmi_graph_entity {
101 struct device_node *node;
102
103 struct v4l2_async_subdev asd;
104 struct v4l2_subdev *subdev;
105 };
106
107 struct dcmi_format {
108 u32 fourcc;
109 u32 mbus_code;
110 u8 bpp;
111 };
112
113 struct dcmi_framesize {
114 u32 width;
115 u32 height;
116 };
117
118 struct dcmi_buf {
119 struct vb2_v4l2_buffer vb;
120 bool prepared;
121 dma_addr_t paddr;
122 size_t size;
123 struct list_head list;
124 };
125
126 struct stm32_dcmi {
127 /* Protects the access of variables shared within the interrupt */
128 spinlock_t irqlock;
129 struct device *dev;
130 void __iomem *regs;
131 struct resource *res;
132 struct reset_control *rstc;
133 int sequence;
134 struct list_head buffers;
135 struct dcmi_buf *active;
136
137 struct v4l2_device v4l2_dev;
138 struct video_device *vdev;
139 struct v4l2_async_notifier notifier;
140 struct dcmi_graph_entity entity;
141 struct v4l2_format fmt;
142 struct v4l2_rect crop;
143 bool do_crop;
144
145 const struct dcmi_format **sd_formats;
146 unsigned int num_of_sd_formats;
147 const struct dcmi_format *sd_format;
148 struct dcmi_framesize *sd_framesizes;
149 unsigned int num_of_sd_framesizes;
150 struct dcmi_framesize sd_framesize;
151 struct v4l2_rect sd_bounds;
152
153 /* Protect this data structure */
154 struct mutex lock;
155 struct vb2_queue queue;
156
157 struct v4l2_fwnode_bus_parallel bus;
158 struct completion complete;
159 struct clk *mclk;
160 enum state state;
161 struct dma_chan *dma_chan;
162 dma_cookie_t dma_cookie;
163 u32 misr;
164 int errors_count;
165 int overrun_count;
166 int buffers_count;
167
168 /* Ensure DMA operations atomicity */
169 struct mutex dma_lock;
170 };
171
172 static inline struct stm32_dcmi *notifier_to_dcmi(struct v4l2_async_notifier *n)
173 {
174 return container_of(n, struct stm32_dcmi, notifier);
175 }
176
177 static inline u32 reg_read(void __iomem *base, u32 reg)
178 {
179 return readl_relaxed(base + reg);
180 }
181
182 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
183 {
184 writel_relaxed(val, base + reg);
185 }
186
187 static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
188 {
189 reg_write(base, reg, reg_read(base, reg) | mask);
190 }
191
192 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
193 {
194 reg_write(base, reg, reg_read(base, reg) & ~mask);
195 }
196
197 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf);
198
199 static void dcmi_buffer_done(struct stm32_dcmi *dcmi,
200 struct dcmi_buf *buf,
201 size_t bytesused,
202 int err)
203 {
204 struct vb2_v4l2_buffer *vbuf;
205
206 if (!buf)
207 return;
208
209 list_del_init(&buf->list);
210
211 vbuf = &buf->vb;
212
213 vbuf->sequence = dcmi->sequence++;
214 vbuf->field = V4L2_FIELD_NONE;
215 vbuf->vb2_buf.timestamp = ktime_get_ns();
216 vb2_set_plane_payload(&vbuf->vb2_buf, 0, bytesused);
217 vb2_buffer_done(&vbuf->vb2_buf,
218 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
219 dev_dbg(dcmi->dev, "buffer[%d] done seq=%d, bytesused=%zu\n",
220 vbuf->vb2_buf.index, vbuf->sequence, bytesused);
221
222 dcmi->buffers_count++;
223 dcmi->active = NULL;
224 }
225
226 static int dcmi_restart_capture(struct stm32_dcmi *dcmi)
227 {
228 struct dcmi_buf *buf;
229
230 spin_lock_irq(&dcmi->irqlock);
231
232 if (dcmi->state != RUNNING) {
233 spin_unlock_irq(&dcmi->irqlock);
234 return -EINVAL;
235 }
236
237 /* Restart a new DMA transfer with next buffer */
238 if (list_empty(&dcmi->buffers)) {
239 dev_dbg(dcmi->dev, "Capture restart is deferred to next buffer queueing\n");
240 dcmi->state = WAIT_FOR_BUFFER;
241 spin_unlock_irq(&dcmi->irqlock);
242 return 0;
243 }
244 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list);
245 dcmi->active = buf;
246
247 spin_unlock_irq(&dcmi->irqlock);
248
249 return dcmi_start_capture(dcmi, buf);
250 }
251
252 static void dcmi_dma_callback(void *param)
253 {
254 struct stm32_dcmi *dcmi = (struct stm32_dcmi *)param;
255 struct dma_tx_state state;
256 enum dma_status status;
257 struct dcmi_buf *buf = dcmi->active;
258
259 spin_lock_irq(&dcmi->irqlock);
260
261 /* Check DMA status */
262 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state);
263
264 switch (status) {
265 case DMA_IN_PROGRESS:
266 dev_dbg(dcmi->dev, "%s: Received DMA_IN_PROGRESS\n", __func__);
267 break;
268 case DMA_PAUSED:
269 dev_err(dcmi->dev, "%s: Received DMA_PAUSED\n", __func__);
270 break;
271 case DMA_ERROR:
272 dev_err(dcmi->dev, "%s: Received DMA_ERROR\n", __func__);
273
274 /* Return buffer to V4L2 in error state */
275 dcmi_buffer_done(dcmi, buf, 0, -EIO);
276 break;
277 case DMA_COMPLETE:
278 dev_dbg(dcmi->dev, "%s: Received DMA_COMPLETE\n", __func__);
279
280 /* Return buffer to V4L2 */
281 dcmi_buffer_done(dcmi, buf, buf->size, 0);
282
283 spin_unlock_irq(&dcmi->irqlock);
284
285 /* Restart capture */
286 if (dcmi_restart_capture(dcmi))
287 dev_err(dcmi->dev, "%s: Cannot restart capture on DMA complete\n",
288 __func__);
289 return;
290 default:
291 dev_err(dcmi->dev, "%s: Received unknown status\n", __func__);
292 break;
293 }
294
295 spin_unlock_irq(&dcmi->irqlock);
296 }
297
298 static int dcmi_start_dma(struct stm32_dcmi *dcmi,
299 struct dcmi_buf *buf)
300 {
301 struct dma_async_tx_descriptor *desc = NULL;
302 struct dma_slave_config config;
303 int ret;
304
305 memset(&config, 0, sizeof(config));
306
307 config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR;
308 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
309 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
310 config.dst_maxburst = 4;
311
312 /* Configure DMA channel */
313 ret = dmaengine_slave_config(dcmi->dma_chan, &config);
314 if (ret < 0) {
315 dev_err(dcmi->dev, "%s: DMA channel config failed (%d)\n",
316 __func__, ret);
317 return ret;
318 }
319
320 /*
321 * Avoid call of dmaengine_terminate_all() between
322 * dmaengine_prep_slave_single() and dmaengine_submit()
323 * by locking the whole DMA submission sequence
324 */
325 mutex_lock(&dcmi->dma_lock);
326
327 /* Prepare a DMA transaction */
328 desc = dmaengine_prep_slave_single(dcmi->dma_chan, buf->paddr,
329 buf->size,
330 DMA_DEV_TO_MEM,
331 DMA_PREP_INTERRUPT);
332 if (!desc) {
333 dev_err(dcmi->dev, "%s: DMA dmaengine_prep_slave_single failed for buffer phy=%pad size=%zu\n",
334 __func__, &buf->paddr, buf->size);
335 mutex_unlock(&dcmi->dma_lock);
336 return -EINVAL;
337 }
338
339 /* Set completion callback routine for notification */
340 desc->callback = dcmi_dma_callback;
341 desc->callback_param = dcmi;
342
343 /* Push current DMA transaction in the pending queue */
344 dcmi->dma_cookie = dmaengine_submit(desc);
345 if (dma_submit_error(dcmi->dma_cookie)) {
346 dev_err(dcmi->dev, "%s: DMA submission failed\n", __func__);
347 mutex_unlock(&dcmi->dma_lock);
348 return -ENXIO;
349 }
350
351 mutex_unlock(&dcmi->dma_lock);
352
353 dma_async_issue_pending(dcmi->dma_chan);
354
355 return 0;
356 }
357
358 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf)
359 {
360 int ret;
361
362 if (!buf)
363 return -EINVAL;
364
365 ret = dcmi_start_dma(dcmi, buf);
366 if (ret) {
367 dcmi->errors_count++;
368 return ret;
369 }
370
371 /* Enable capture */
372 reg_set(dcmi->regs, DCMI_CR, CR_CAPTURE);
373
374 return 0;
375 }
376
377 static void dcmi_set_crop(struct stm32_dcmi *dcmi)
378 {
379 u32 size, start;
380
381 /* Crop resolution */
382 size = ((dcmi->crop.height - 1) << 16) |
383 ((dcmi->crop.width << 1) - 1);
384 reg_write(dcmi->regs, DCMI_CWSIZE, size);
385
386 /* Crop start point */
387 start = ((dcmi->crop.top) << 16) |
388 ((dcmi->crop.left << 1));
389 reg_write(dcmi->regs, DCMI_CWSTRT, start);
390
391 dev_dbg(dcmi->dev, "Cropping to %ux%u@%u:%u\n",
392 dcmi->crop.width, dcmi->crop.height,
393 dcmi->crop.left, dcmi->crop.top);
394
395 /* Enable crop */
396 reg_set(dcmi->regs, DCMI_CR, CR_CROP);
397 }
398
399 static void dcmi_process_jpeg(struct stm32_dcmi *dcmi)
400 {
401 struct dma_tx_state state;
402 enum dma_status status;
403 struct dcmi_buf *buf = dcmi->active;
404
405 if (!buf)
406 return;
407
408 /*
409 * Because of variable JPEG buffer size sent by sensor,
410 * DMA transfer never completes due to transfer size never reached.
411 * In order to ensure that all the JPEG data are transferred
412 * in active buffer memory, DMA is drained.
413 * Then DMA tx status gives the amount of data transferred
414 * to memory, which is then returned to V4L2 through the active
415 * buffer payload.
416 */
417
418 /* Drain DMA */
419 dmaengine_synchronize(dcmi->dma_chan);
420
421 /* Get DMA residue to get JPEG size */
422 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state);
423 if (status != DMA_ERROR && state.residue < buf->size) {
424 /* Return JPEG buffer to V4L2 with received JPEG buffer size */
425 dcmi_buffer_done(dcmi, buf, buf->size - state.residue, 0);
426 } else {
427 dcmi->errors_count++;
428 dev_err(dcmi->dev, "%s: Cannot get JPEG size from DMA\n",
429 __func__);
430 /* Return JPEG buffer to V4L2 in ERROR state */
431 dcmi_buffer_done(dcmi, buf, 0, -EIO);
432 }
433
434 /* Abort DMA operation */
435 dmaengine_terminate_all(dcmi->dma_chan);
436
437 /* Restart capture */
438 if (dcmi_restart_capture(dcmi))
439 dev_err(dcmi->dev, "%s: Cannot restart capture on JPEG received\n",
440 __func__);
441 }
442
443 static irqreturn_t dcmi_irq_thread(int irq, void *arg)
444 {
445 struct stm32_dcmi *dcmi = arg;
446
447 spin_lock_irq(&dcmi->irqlock);
448
449 if ((dcmi->misr & IT_OVR) || (dcmi->misr & IT_ERR)) {
450 dcmi->errors_count++;
451 if (dcmi->misr & IT_OVR)
452 dcmi->overrun_count++;
453 }
454
455 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG &&
456 dcmi->misr & IT_FRAME) {
457 /* JPEG received */
458 spin_unlock_irq(&dcmi->irqlock);
459 dcmi_process_jpeg(dcmi);
460 return IRQ_HANDLED;
461 }
462
463 spin_unlock_irq(&dcmi->irqlock);
464 return IRQ_HANDLED;
465 }
466
467 static irqreturn_t dcmi_irq_callback(int irq, void *arg)
468 {
469 struct stm32_dcmi *dcmi = arg;
470 unsigned long flags;
471
472 spin_lock_irqsave(&dcmi->irqlock, flags);
473
474 dcmi->misr = reg_read(dcmi->regs, DCMI_MIS);
475
476 /* Clear interrupt */
477 reg_set(dcmi->regs, DCMI_ICR, IT_FRAME | IT_OVR | IT_ERR);
478
479 spin_unlock_irqrestore(&dcmi->irqlock, flags);
480
481 return IRQ_WAKE_THREAD;
482 }
483
484 static int dcmi_queue_setup(struct vb2_queue *vq,
485 unsigned int *nbuffers,
486 unsigned int *nplanes,
487 unsigned int sizes[],
488 struct device *alloc_devs[])
489 {
490 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
491 unsigned int size;
492
493 size = dcmi->fmt.fmt.pix.sizeimage;
494
495 /* Make sure the image size is large enough */
496 if (*nplanes)
497 return sizes[0] < size ? -EINVAL : 0;
498
499 *nplanes = 1;
500 sizes[0] = size;
501
502 dev_dbg(dcmi->dev, "Setup queue, count=%d, size=%d\n",
503 *nbuffers, size);
504
505 return 0;
506 }
507
508 static int dcmi_buf_init(struct vb2_buffer *vb)
509 {
510 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
511 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
512
513 INIT_LIST_HEAD(&buf->list);
514
515 return 0;
516 }
517
518 static int dcmi_buf_prepare(struct vb2_buffer *vb)
519 {
520 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue);
521 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
522 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
523 unsigned long size;
524
525 size = dcmi->fmt.fmt.pix.sizeimage;
526
527 if (vb2_plane_size(vb, 0) < size) {
528 dev_err(dcmi->dev, "%s data will not fit into plane (%lu < %lu)\n",
529 __func__, vb2_plane_size(vb, 0), size);
530 return -EINVAL;
531 }
532
533 vb2_set_plane_payload(vb, 0, size);
534
535 if (!buf->prepared) {
536 /* Get memory addresses */
537 buf->paddr =
538 vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
539 buf->size = vb2_plane_size(&buf->vb.vb2_buf, 0);
540 buf->prepared = true;
541
542 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, buf->size);
543
544 dev_dbg(dcmi->dev, "buffer[%d] phy=%pad size=%zu\n",
545 vb->index, &buf->paddr, buf->size);
546 }
547
548 return 0;
549 }
550
551 static void dcmi_buf_queue(struct vb2_buffer *vb)
552 {
553 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue);
554 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
555 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb);
556
557 spin_lock_irq(&dcmi->irqlock);
558
559 /* Enqueue to video buffers list */
560 list_add_tail(&buf->list, &dcmi->buffers);
561
562 if (dcmi->state == WAIT_FOR_BUFFER) {
563 dcmi->state = RUNNING;
564 dcmi->active = buf;
565
566 dev_dbg(dcmi->dev, "Starting capture on buffer[%d] queued\n",
567 buf->vb.vb2_buf.index);
568
569 spin_unlock_irq(&dcmi->irqlock);
570 if (dcmi_start_capture(dcmi, buf))
571 dev_err(dcmi->dev, "%s: Cannot restart capture on overflow or error\n",
572 __func__);
573 return;
574 }
575
576 spin_unlock_irq(&dcmi->irqlock);
577 }
578
579 static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count)
580 {
581 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
582 struct dcmi_buf *buf, *node;
583 u32 val = 0;
584 int ret;
585
586 ret = pm_runtime_get_sync(dcmi->dev);
587 if (ret < 0) {
588 dev_err(dcmi->dev, "%s: Failed to start streaming, cannot get sync (%d)\n",
589 __func__, ret);
590 goto err_release_buffers;
591 }
592
593 /* Enable stream on the sub device */
594 ret = v4l2_subdev_call(dcmi->entity.subdev, video, s_stream, 1);
595 if (ret && ret != -ENOIOCTLCMD) {
596 dev_err(dcmi->dev, "%s: Failed to start streaming, subdev streamon error",
597 __func__);
598 goto err_pm_put;
599 }
600
601 spin_lock_irq(&dcmi->irqlock);
602
603 /* Set bus width */
604 switch (dcmi->bus.bus_width) {
605 case 14:
606 val |= CR_EDM_0 | CR_EDM_1;
607 break;
608 case 12:
609 val |= CR_EDM_1;
610 break;
611 case 10:
612 val |= CR_EDM_0;
613 break;
614 default:
615 /* Set bus width to 8 bits by default */
616 break;
617 }
618
619 /* Set vertical synchronization polarity */
620 if (dcmi->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
621 val |= CR_VSPOL;
622
623 /* Set horizontal synchronization polarity */
624 if (dcmi->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
625 val |= CR_HSPOL;
626
627 /* Set pixel clock polarity */
628 if (dcmi->bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
629 val |= CR_PCKPOL;
630
631 reg_write(dcmi->regs, DCMI_CR, val);
632
633 /* Set crop */
634 if (dcmi->do_crop)
635 dcmi_set_crop(dcmi);
636
637 /* Enable jpeg capture */
638 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG)
639 reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */
640
641 /* Enable dcmi */
642 reg_set(dcmi->regs, DCMI_CR, CR_ENABLE);
643
644 dcmi->sequence = 0;
645 dcmi->errors_count = 0;
646 dcmi->overrun_count = 0;
647 dcmi->buffers_count = 0;
648
649 /*
650 * Start transfer if at least one buffer has been queued,
651 * otherwise transfer is deferred at buffer queueing
652 */
653 if (list_empty(&dcmi->buffers)) {
654 dev_dbg(dcmi->dev, "Start streaming is deferred to next buffer queueing\n");
655 dcmi->state = WAIT_FOR_BUFFER;
656 spin_unlock_irq(&dcmi->irqlock);
657 return 0;
658 }
659
660 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list);
661 dcmi->active = buf;
662
663 dcmi->state = RUNNING;
664
665 dev_dbg(dcmi->dev, "Start streaming, starting capture\n");
666
667 spin_unlock_irq(&dcmi->irqlock);
668 ret = dcmi_start_capture(dcmi, buf);
669 if (ret) {
670 dev_err(dcmi->dev, "%s: Start streaming failed, cannot start capture\n",
671 __func__);
672 goto err_subdev_streamoff;
673 }
674
675 /* Enable interruptions */
676 reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
677
678 return 0;
679
680 err_subdev_streamoff:
681 v4l2_subdev_call(dcmi->entity.subdev, video, s_stream, 0);
682
683 err_pm_put:
684 pm_runtime_put(dcmi->dev);
685
686 err_release_buffers:
687 spin_lock_irq(&dcmi->irqlock);
688 /*
689 * Return all buffers to vb2 in QUEUED state.
690 * This will give ownership back to userspace
691 */
692 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) {
693 list_del_init(&buf->list);
694 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
695 }
696 dcmi->active = NULL;
697 spin_unlock_irq(&dcmi->irqlock);
698
699 return ret;
700 }
701
702 static void dcmi_stop_streaming(struct vb2_queue *vq)
703 {
704 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);
705 struct dcmi_buf *buf, *node;
706 int ret;
707
708 /* Disable stream on the sub device */
709 ret = v4l2_subdev_call(dcmi->entity.subdev, video, s_stream, 0);
710 if (ret && ret != -ENOIOCTLCMD)
711 dev_err(dcmi->dev, "%s: Failed to stop streaming, subdev streamoff error (%d)\n",
712 __func__, ret);
713
714 spin_lock_irq(&dcmi->irqlock);
715
716 /* Disable interruptions */
717 reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);
718
719 /* Disable DCMI */
720 reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE);
721
722 /* Return all queued buffers to vb2 in ERROR state */
723 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) {
724 list_del_init(&buf->list);
725 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
726 }
727
728 dcmi->active = NULL;
729 dcmi->state = STOPPED;
730
731 spin_unlock_irq(&dcmi->irqlock);
732
733 /* Stop all pending DMA operations */
734 mutex_lock(&dcmi->dma_lock);
735 dmaengine_terminate_all(dcmi->dma_chan);
736 mutex_unlock(&dcmi->dma_lock);
737
738 pm_runtime_put(dcmi->dev);
739
740 if (dcmi->errors_count)
741 dev_warn(dcmi->dev, "Some errors found while streaming: errors=%d (overrun=%d), buffers=%d\n",
742 dcmi->errors_count, dcmi->overrun_count,
743 dcmi->buffers_count);
744 dev_dbg(dcmi->dev, "Stop streaming, errors=%d (overrun=%d), buffers=%d\n",
745 dcmi->errors_count, dcmi->overrun_count,
746 dcmi->buffers_count);
747 }
748
749 static const struct vb2_ops dcmi_video_qops = {
750 .queue_setup = dcmi_queue_setup,
751 .buf_init = dcmi_buf_init,
752 .buf_prepare = dcmi_buf_prepare,
753 .buf_queue = dcmi_buf_queue,
754 .start_streaming = dcmi_start_streaming,
755 .stop_streaming = dcmi_stop_streaming,
756 .wait_prepare = vb2_ops_wait_prepare,
757 .wait_finish = vb2_ops_wait_finish,
758 };
759
760 static int dcmi_g_fmt_vid_cap(struct file *file, void *priv,
761 struct v4l2_format *fmt)
762 {
763 struct stm32_dcmi *dcmi = video_drvdata(file);
764
765 *fmt = dcmi->fmt;
766
767 return 0;
768 }
769
770 static const struct dcmi_format *find_format_by_fourcc(struct stm32_dcmi *dcmi,
771 unsigned int fourcc)
772 {
773 unsigned int num_formats = dcmi->num_of_sd_formats;
774 const struct dcmi_format *fmt;
775 unsigned int i;
776
777 for (i = 0; i < num_formats; i++) {
778 fmt = dcmi->sd_formats[i];
779 if (fmt->fourcc == fourcc)
780 return fmt;
781 }
782
783 return NULL;
784 }
785
786 static void __find_outer_frame_size(struct stm32_dcmi *dcmi,
787 struct v4l2_pix_format *pix,
788 struct dcmi_framesize *framesize)
789 {
790 struct dcmi_framesize *match = NULL;
791 unsigned int i;
792 unsigned int min_err = UINT_MAX;
793
794 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
795 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i];
796 int w_err = (fsize->width - pix->width);
797 int h_err = (fsize->height - pix->height);
798 int err = w_err + h_err;
799
800 if (w_err >= 0 && h_err >= 0 && err < min_err) {
801 min_err = err;
802 match = fsize;
803 }
804 }
805 if (!match)
806 match = &dcmi->sd_framesizes[0];
807
808 *framesize = *match;
809 }
810
811 static int dcmi_try_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f,
812 const struct dcmi_format **sd_format,
813 struct dcmi_framesize *sd_framesize)
814 {
815 const struct dcmi_format *sd_fmt;
816 struct dcmi_framesize sd_fsize;
817 struct v4l2_pix_format *pix = &f->fmt.pix;
818 struct v4l2_subdev_pad_config pad_cfg;
819 struct v4l2_subdev_format format = {
820 .which = V4L2_SUBDEV_FORMAT_TRY,
821 };
822 bool do_crop;
823 int ret;
824
825 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat);
826 if (!sd_fmt) {
827 if (!dcmi->num_of_sd_formats)
828 return -ENODATA;
829
830 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1];
831 pix->pixelformat = sd_fmt->fourcc;
832 }
833
834 /* Limit to hardware capabilities */
835 pix->width = clamp(pix->width, MIN_WIDTH, MAX_WIDTH);
836 pix->height = clamp(pix->height, MIN_HEIGHT, MAX_HEIGHT);
837
838 /* No crop if JPEG is requested */
839 do_crop = dcmi->do_crop && (pix->pixelformat != V4L2_PIX_FMT_JPEG);
840
841 if (do_crop && dcmi->num_of_sd_framesizes) {
842 struct dcmi_framesize outer_sd_fsize;
843 /*
844 * If crop is requested and sensor have discrete frame sizes,
845 * select the frame size that is just larger than request
846 */
847 __find_outer_frame_size(dcmi, pix, &outer_sd_fsize);
848 pix->width = outer_sd_fsize.width;
849 pix->height = outer_sd_fsize.height;
850 }
851
852 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code);
853 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, set_fmt,
854 &pad_cfg, &format);
855 if (ret < 0)
856 return ret;
857
858 /* Update pix regarding to what sensor can do */
859 v4l2_fill_pix_format(pix, &format.format);
860
861 /* Save resolution that sensor can actually do */
862 sd_fsize.width = pix->width;
863 sd_fsize.height = pix->height;
864
865 if (do_crop) {
866 struct v4l2_rect c = dcmi->crop;
867 struct v4l2_rect max_rect;
868
869 /*
870 * Adjust crop by making the intersection between
871 * format resolution request and crop request
872 */
873 max_rect.top = 0;
874 max_rect.left = 0;
875 max_rect.width = pix->width;
876 max_rect.height = pix->height;
877 v4l2_rect_map_inside(&c, &max_rect);
878 c.top = clamp_t(s32, c.top, 0, pix->height - c.height);
879 c.left = clamp_t(s32, c.left, 0, pix->width - c.width);
880 dcmi->crop = c;
881
882 /* Adjust format resolution request to crop */
883 pix->width = dcmi->crop.width;
884 pix->height = dcmi->crop.height;
885 }
886
887 pix->field = V4L2_FIELD_NONE;
888 pix->bytesperline = pix->width * sd_fmt->bpp;
889 pix->sizeimage = pix->bytesperline * pix->height;
890
891 if (sd_format)
892 *sd_format = sd_fmt;
893 if (sd_framesize)
894 *sd_framesize = sd_fsize;
895
896 return 0;
897 }
898
899 static int dcmi_set_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f)
900 {
901 struct v4l2_subdev_format format = {
902 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
903 };
904 const struct dcmi_format *sd_format;
905 struct dcmi_framesize sd_framesize;
906 struct v4l2_mbus_framefmt *mf = &format.format;
907 struct v4l2_pix_format *pix = &f->fmt.pix;
908 int ret;
909
910 /*
911 * Try format, fmt.width/height could have been changed
912 * to match sensor capability or crop request
913 * sd_format & sd_framesize will contain what subdev
914 * can do for this request.
915 */
916 ret = dcmi_try_fmt(dcmi, f, &sd_format, &sd_framesize);
917 if (ret)
918 return ret;
919
920 /* Disable crop if JPEG is requested */
921 if (pix->pixelformat == V4L2_PIX_FMT_JPEG)
922 dcmi->do_crop = false;
923
924 /* pix to mbus format */
925 v4l2_fill_mbus_format(mf, pix,
926 sd_format->mbus_code);
927 mf->width = sd_framesize.width;
928 mf->height = sd_framesize.height;
929
930 ret = v4l2_subdev_call(dcmi->entity.subdev, pad,
931 set_fmt, NULL, &format);
932 if (ret < 0)
933 return ret;
934
935 dev_dbg(dcmi->dev, "Sensor format set to 0x%x %ux%u\n",
936 mf->code, mf->width, mf->height);
937 dev_dbg(dcmi->dev, "Buffer format set to %4.4s %ux%u\n",
938 (char *)&pix->pixelformat,
939 pix->width, pix->height);
940
941 dcmi->fmt = *f;
942 dcmi->sd_format = sd_format;
943 dcmi->sd_framesize = sd_framesize;
944
945 return 0;
946 }
947
948 static int dcmi_s_fmt_vid_cap(struct file *file, void *priv,
949 struct v4l2_format *f)
950 {
951 struct stm32_dcmi *dcmi = video_drvdata(file);
952
953 if (vb2_is_streaming(&dcmi->queue))
954 return -EBUSY;
955
956 return dcmi_set_fmt(dcmi, f);
957 }
958
959 static int dcmi_try_fmt_vid_cap(struct file *file, void *priv,
960 struct v4l2_format *f)
961 {
962 struct stm32_dcmi *dcmi = video_drvdata(file);
963
964 return dcmi_try_fmt(dcmi, f, NULL, NULL);
965 }
966
967 static int dcmi_enum_fmt_vid_cap(struct file *file, void *priv,
968 struct v4l2_fmtdesc *f)
969 {
970 struct stm32_dcmi *dcmi = video_drvdata(file);
971
972 if (f->index >= dcmi->num_of_sd_formats)
973 return -EINVAL;
974
975 f->pixelformat = dcmi->sd_formats[f->index]->fourcc;
976 return 0;
977 }
978
979 static int dcmi_get_sensor_format(struct stm32_dcmi *dcmi,
980 struct v4l2_pix_format *pix)
981 {
982 struct v4l2_subdev_format fmt = {
983 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
984 };
985 int ret;
986
987 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, get_fmt, NULL, &fmt);
988 if (ret)
989 return ret;
990
991 v4l2_fill_pix_format(pix, &fmt.format);
992
993 return 0;
994 }
995
996 static int dcmi_set_sensor_format(struct stm32_dcmi *dcmi,
997 struct v4l2_pix_format *pix)
998 {
999 const struct dcmi_format *sd_fmt;
1000 struct v4l2_subdev_format format = {
1001 .which = V4L2_SUBDEV_FORMAT_TRY,
1002 };
1003 struct v4l2_subdev_pad_config pad_cfg;
1004 int ret;
1005
1006 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat);
1007 if (!sd_fmt) {
1008 if (!dcmi->num_of_sd_formats)
1009 return -ENODATA;
1010
1011 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1];
1012 pix->pixelformat = sd_fmt->fourcc;
1013 }
1014
1015 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code);
1016 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, set_fmt,
1017 &pad_cfg, &format);
1018 if (ret < 0)
1019 return ret;
1020
1021 return 0;
1022 }
1023
1024 static int dcmi_get_sensor_bounds(struct stm32_dcmi *dcmi,
1025 struct v4l2_rect *r)
1026 {
1027 struct v4l2_subdev_selection bounds = {
1028 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1029 .target = V4L2_SEL_TGT_CROP_BOUNDS,
1030 };
1031 unsigned int max_width, max_height, max_pixsize;
1032 struct v4l2_pix_format pix;
1033 unsigned int i;
1034 int ret;
1035
1036 /*
1037 * Get sensor bounds first
1038 */
1039 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, get_selection,
1040 NULL, &bounds);
1041 if (!ret)
1042 *r = bounds.r;
1043 if (ret != -ENOIOCTLCMD)
1044 return ret;
1045
1046 /*
1047 * If selection is not implemented,
1048 * fallback by enumerating sensor frame sizes
1049 * and take the largest one
1050 */
1051 max_width = 0;
1052 max_height = 0;
1053 max_pixsize = 0;
1054 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
1055 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i];
1056 unsigned int pixsize = fsize->width * fsize->height;
1057
1058 if (pixsize > max_pixsize) {
1059 max_pixsize = pixsize;
1060 max_width = fsize->width;
1061 max_height = fsize->height;
1062 }
1063 }
1064 if (max_pixsize > 0) {
1065 r->top = 0;
1066 r->left = 0;
1067 r->width = max_width;
1068 r->height = max_height;
1069 return 0;
1070 }
1071
1072 /*
1073 * If frame sizes enumeration is not implemented,
1074 * fallback by getting current sensor frame size
1075 */
1076 ret = dcmi_get_sensor_format(dcmi, &pix);
1077 if (ret)
1078 return ret;
1079
1080 r->top = 0;
1081 r->left = 0;
1082 r->width = pix.width;
1083 r->height = pix.height;
1084
1085 return 0;
1086 }
1087
1088 static int dcmi_g_selection(struct file *file, void *fh,
1089 struct v4l2_selection *s)
1090 {
1091 struct stm32_dcmi *dcmi = video_drvdata(file);
1092
1093 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1094 return -EINVAL;
1095
1096 switch (s->target) {
1097 case V4L2_SEL_TGT_CROP_DEFAULT:
1098 case V4L2_SEL_TGT_CROP_BOUNDS:
1099 s->r = dcmi->sd_bounds;
1100 return 0;
1101 case V4L2_SEL_TGT_CROP:
1102 if (dcmi->do_crop) {
1103 s->r = dcmi->crop;
1104 } else {
1105 s->r.top = 0;
1106 s->r.left = 0;
1107 s->r.width = dcmi->fmt.fmt.pix.width;
1108 s->r.height = dcmi->fmt.fmt.pix.height;
1109 }
1110 break;
1111 default:
1112 return -EINVAL;
1113 }
1114
1115 return 0;
1116 }
1117
1118 static int dcmi_s_selection(struct file *file, void *priv,
1119 struct v4l2_selection *s)
1120 {
1121 struct stm32_dcmi *dcmi = video_drvdata(file);
1122 struct v4l2_rect r = s->r;
1123 struct v4l2_rect max_rect;
1124 struct v4l2_pix_format pix;
1125
1126 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE ||
1127 s->target != V4L2_SEL_TGT_CROP)
1128 return -EINVAL;
1129
1130 /* Reset sensor resolution to max resolution */
1131 pix.pixelformat = dcmi->fmt.fmt.pix.pixelformat;
1132 pix.width = dcmi->sd_bounds.width;
1133 pix.height = dcmi->sd_bounds.height;
1134 dcmi_set_sensor_format(dcmi, &pix);
1135
1136 /*
1137 * Make the intersection between
1138 * sensor resolution
1139 * and crop request
1140 */
1141 max_rect.top = 0;
1142 max_rect.left = 0;
1143 max_rect.width = pix.width;
1144 max_rect.height = pix.height;
1145 v4l2_rect_map_inside(&r, &max_rect);
1146 r.top = clamp_t(s32, r.top, 0, pix.height - r.height);
1147 r.left = clamp_t(s32, r.left, 0, pix.width - r.width);
1148
1149 if (!(r.top == dcmi->sd_bounds.top &&
1150 r.left == dcmi->sd_bounds.left &&
1151 r.width == dcmi->sd_bounds.width &&
1152 r.height == dcmi->sd_bounds.height)) {
1153 /* Crop if request is different than sensor resolution */
1154 dcmi->do_crop = true;
1155 dcmi->crop = r;
1156 dev_dbg(dcmi->dev, "s_selection: crop %ux%u@(%u,%u) from %ux%u\n",
1157 r.width, r.height, r.left, r.top,
1158 pix.width, pix.height);
1159 } else {
1160 /* Disable crop */
1161 dcmi->do_crop = false;
1162 dev_dbg(dcmi->dev, "s_selection: crop is disabled\n");
1163 }
1164
1165 s->r = r;
1166 return 0;
1167 }
1168
1169 static int dcmi_querycap(struct file *file, void *priv,
1170 struct v4l2_capability *cap)
1171 {
1172 strlcpy(cap->driver, DRV_NAME, sizeof(cap->driver));
1173 strlcpy(cap->card, "STM32 Camera Memory Interface",
1174 sizeof(cap->card));
1175 strlcpy(cap->bus_info, "platform:dcmi", sizeof(cap->bus_info));
1176 return 0;
1177 }
1178
1179 static int dcmi_enum_input(struct file *file, void *priv,
1180 struct v4l2_input *i)
1181 {
1182 if (i->index != 0)
1183 return -EINVAL;
1184
1185 i->type = V4L2_INPUT_TYPE_CAMERA;
1186 strlcpy(i->name, "Camera", sizeof(i->name));
1187 return 0;
1188 }
1189
1190 static int dcmi_g_input(struct file *file, void *priv, unsigned int *i)
1191 {
1192 *i = 0;
1193 return 0;
1194 }
1195
1196 static int dcmi_s_input(struct file *file, void *priv, unsigned int i)
1197 {
1198 if (i > 0)
1199 return -EINVAL;
1200 return 0;
1201 }
1202
1203 static int dcmi_enum_framesizes(struct file *file, void *fh,
1204 struct v4l2_frmsizeenum *fsize)
1205 {
1206 struct stm32_dcmi *dcmi = video_drvdata(file);
1207 const struct dcmi_format *sd_fmt;
1208 struct v4l2_subdev_frame_size_enum fse = {
1209 .index = fsize->index,
1210 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1211 };
1212 int ret;
1213
1214 sd_fmt = find_format_by_fourcc(dcmi, fsize->pixel_format);
1215 if (!sd_fmt)
1216 return -EINVAL;
1217
1218 fse.code = sd_fmt->mbus_code;
1219
1220 ret = v4l2_subdev_call(dcmi->entity.subdev, pad, enum_frame_size,
1221 NULL, &fse);
1222 if (ret)
1223 return ret;
1224
1225 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1226 fsize->discrete.width = fse.max_width;
1227 fsize->discrete.height = fse.max_height;
1228
1229 return 0;
1230 }
1231
1232 static int dcmi_g_parm(struct file *file, void *priv,
1233 struct v4l2_streamparm *p)
1234 {
1235 struct stm32_dcmi *dcmi = video_drvdata(file);
1236
1237 return v4l2_g_parm_cap(video_devdata(file), dcmi->entity.subdev, p);
1238 }
1239
1240 static int dcmi_s_parm(struct file *file, void *priv,
1241 struct v4l2_streamparm *p)
1242 {
1243 struct stm32_dcmi *dcmi = video_drvdata(file);
1244
1245 return v4l2_s_parm_cap(video_devdata(file), dcmi->entity.subdev, p);
1246 }
1247
1248 static int dcmi_enum_frameintervals(struct file *file, void *fh,
1249 struct v4l2_frmivalenum *fival)
1250 {
1251 struct stm32_dcmi *dcmi = video_drvdata(file);
1252 const struct dcmi_format *sd_fmt;
1253 struct v4l2_subdev_frame_interval_enum fie = {
1254 .index = fival->index,
1255 .width = fival->width,
1256 .height = fival->height,
1257 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1258 };
1259 int ret;
1260
1261 sd_fmt = find_format_by_fourcc(dcmi, fival->pixel_format);
1262 if (!sd_fmt)
1263 return -EINVAL;
1264
1265 fie.code = sd_fmt->mbus_code;
1266
1267 ret = v4l2_subdev_call(dcmi->entity.subdev, pad,
1268 enum_frame_interval, NULL, &fie);
1269 if (ret)
1270 return ret;
1271
1272 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1273 fival->discrete = fie.interval;
1274
1275 return 0;
1276 }
1277
1278 static const struct of_device_id stm32_dcmi_of_match[] = {
1279 { .compatible = "st,stm32-dcmi"},
1280 { /* end node */ },
1281 };
1282 MODULE_DEVICE_TABLE(of, stm32_dcmi_of_match);
1283
1284 static int dcmi_open(struct file *file)
1285 {
1286 struct stm32_dcmi *dcmi = video_drvdata(file);
1287 struct v4l2_subdev *sd = dcmi->entity.subdev;
1288 int ret;
1289
1290 if (mutex_lock_interruptible(&dcmi->lock))
1291 return -ERESTARTSYS;
1292
1293 ret = v4l2_fh_open(file);
1294 if (ret < 0)
1295 goto unlock;
1296
1297 if (!v4l2_fh_is_singular_file(file))
1298 goto fh_rel;
1299
1300 ret = v4l2_subdev_call(sd, core, s_power, 1);
1301 if (ret < 0 && ret != -ENOIOCTLCMD)
1302 goto fh_rel;
1303
1304 ret = dcmi_set_fmt(dcmi, &dcmi->fmt);
1305 if (ret)
1306 v4l2_subdev_call(sd, core, s_power, 0);
1307 fh_rel:
1308 if (ret)
1309 v4l2_fh_release(file);
1310 unlock:
1311 mutex_unlock(&dcmi->lock);
1312 return ret;
1313 }
1314
1315 static int dcmi_release(struct file *file)
1316 {
1317 struct stm32_dcmi *dcmi = video_drvdata(file);
1318 struct v4l2_subdev *sd = dcmi->entity.subdev;
1319 bool fh_singular;
1320 int ret;
1321
1322 mutex_lock(&dcmi->lock);
1323
1324 fh_singular = v4l2_fh_is_singular_file(file);
1325
1326 ret = _vb2_fop_release(file, NULL);
1327
1328 if (fh_singular)
1329 v4l2_subdev_call(sd, core, s_power, 0);
1330
1331 mutex_unlock(&dcmi->lock);
1332
1333 return ret;
1334 }
1335
1336 static const struct v4l2_ioctl_ops dcmi_ioctl_ops = {
1337 .vidioc_querycap = dcmi_querycap,
1338
1339 .vidioc_try_fmt_vid_cap = dcmi_try_fmt_vid_cap,
1340 .vidioc_g_fmt_vid_cap = dcmi_g_fmt_vid_cap,
1341 .vidioc_s_fmt_vid_cap = dcmi_s_fmt_vid_cap,
1342 .vidioc_enum_fmt_vid_cap = dcmi_enum_fmt_vid_cap,
1343 .vidioc_g_selection = dcmi_g_selection,
1344 .vidioc_s_selection = dcmi_s_selection,
1345
1346 .vidioc_enum_input = dcmi_enum_input,
1347 .vidioc_g_input = dcmi_g_input,
1348 .vidioc_s_input = dcmi_s_input,
1349
1350 .vidioc_g_parm = dcmi_g_parm,
1351 .vidioc_s_parm = dcmi_s_parm,
1352
1353 .vidioc_enum_framesizes = dcmi_enum_framesizes,
1354 .vidioc_enum_frameintervals = dcmi_enum_frameintervals,
1355
1356 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1357 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1358 .vidioc_querybuf = vb2_ioctl_querybuf,
1359 .vidioc_qbuf = vb2_ioctl_qbuf,
1360 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1361 .vidioc_expbuf = vb2_ioctl_expbuf,
1362 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1363 .vidioc_streamon = vb2_ioctl_streamon,
1364 .vidioc_streamoff = vb2_ioctl_streamoff,
1365
1366 .vidioc_log_status = v4l2_ctrl_log_status,
1367 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1368 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1369 };
1370
1371 static const struct v4l2_file_operations dcmi_fops = {
1372 .owner = THIS_MODULE,
1373 .unlocked_ioctl = video_ioctl2,
1374 .open = dcmi_open,
1375 .release = dcmi_release,
1376 .poll = vb2_fop_poll,
1377 .mmap = vb2_fop_mmap,
1378 #ifndef CONFIG_MMU
1379 .get_unmapped_area = vb2_fop_get_unmapped_area,
1380 #endif
1381 .read = vb2_fop_read,
1382 };
1383
1384 static int dcmi_set_default_fmt(struct stm32_dcmi *dcmi)
1385 {
1386 struct v4l2_format f = {
1387 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1388 .fmt.pix = {
1389 .width = CIF_WIDTH,
1390 .height = CIF_HEIGHT,
1391 .field = V4L2_FIELD_NONE,
1392 .pixelformat = dcmi->sd_formats[0]->fourcc,
1393 },
1394 };
1395 int ret;
1396
1397 ret = dcmi_try_fmt(dcmi, &f, NULL, NULL);
1398 if (ret)
1399 return ret;
1400 dcmi->sd_format = dcmi->sd_formats[0];
1401 dcmi->fmt = f;
1402 return 0;
1403 }
1404
1405 static const struct dcmi_format dcmi_formats[] = {
1406 {
1407 .fourcc = V4L2_PIX_FMT_RGB565,
1408 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
1409 .bpp = 2,
1410 }, {
1411 .fourcc = V4L2_PIX_FMT_YUYV,
1412 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
1413 .bpp = 2,
1414 }, {
1415 .fourcc = V4L2_PIX_FMT_UYVY,
1416 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
1417 .bpp = 2,
1418 }, {
1419 .fourcc = V4L2_PIX_FMT_JPEG,
1420 .mbus_code = MEDIA_BUS_FMT_JPEG_1X8,
1421 .bpp = 1,
1422 },
1423 };
1424
1425 static int dcmi_formats_init(struct stm32_dcmi *dcmi)
1426 {
1427 const struct dcmi_format *sd_fmts[ARRAY_SIZE(dcmi_formats)];
1428 unsigned int num_fmts = 0, i, j;
1429 struct v4l2_subdev *subdev = dcmi->entity.subdev;
1430 struct v4l2_subdev_mbus_code_enum mbus_code = {
1431 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1432 };
1433
1434 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code,
1435 NULL, &mbus_code)) {
1436 for (i = 0; i < ARRAY_SIZE(dcmi_formats); i++) {
1437 if (dcmi_formats[i].mbus_code != mbus_code.code)
1438 continue;
1439
1440 /* Code supported, have we got this fourcc yet? */
1441 for (j = 0; j < num_fmts; j++)
1442 if (sd_fmts[j]->fourcc ==
1443 dcmi_formats[i].fourcc)
1444 /* Already available */
1445 break;
1446 if (j == num_fmts)
1447 /* New */
1448 sd_fmts[num_fmts++] = dcmi_formats + i;
1449 }
1450 mbus_code.index++;
1451 }
1452
1453 if (!num_fmts)
1454 return -ENXIO;
1455
1456 dcmi->num_of_sd_formats = num_fmts;
1457 dcmi->sd_formats = devm_kcalloc(dcmi->dev,
1458 num_fmts, sizeof(struct dcmi_format *),
1459 GFP_KERNEL);
1460 if (!dcmi->sd_formats) {
1461 dev_err(dcmi->dev, "Could not allocate memory\n");
1462 return -ENOMEM;
1463 }
1464
1465 memcpy(dcmi->sd_formats, sd_fmts,
1466 num_fmts * sizeof(struct dcmi_format *));
1467 dcmi->sd_format = dcmi->sd_formats[0];
1468
1469 return 0;
1470 }
1471
1472 static int dcmi_framesizes_init(struct stm32_dcmi *dcmi)
1473 {
1474 unsigned int num_fsize = 0;
1475 struct v4l2_subdev *subdev = dcmi->entity.subdev;
1476 struct v4l2_subdev_frame_size_enum fse = {
1477 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1478 .code = dcmi->sd_format->mbus_code,
1479 };
1480 unsigned int ret;
1481 unsigned int i;
1482
1483 /* Allocate discrete framesizes array */
1484 while (!v4l2_subdev_call(subdev, pad, enum_frame_size,
1485 NULL, &fse))
1486 fse.index++;
1487
1488 num_fsize = fse.index;
1489 if (!num_fsize)
1490 return 0;
1491
1492 dcmi->num_of_sd_framesizes = num_fsize;
1493 dcmi->sd_framesizes = devm_kcalloc(dcmi->dev, num_fsize,
1494 sizeof(struct dcmi_framesize),
1495 GFP_KERNEL);
1496 if (!dcmi->sd_framesizes) {
1497 dev_err(dcmi->dev, "Could not allocate memory\n");
1498 return -ENOMEM;
1499 }
1500
1501 /* Fill array with sensor supported framesizes */
1502 dev_dbg(dcmi->dev, "Sensor supports %u frame sizes:\n", num_fsize);
1503 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) {
1504 fse.index = i;
1505 ret = v4l2_subdev_call(subdev, pad, enum_frame_size,
1506 NULL, &fse);
1507 if (ret)
1508 return ret;
1509 dcmi->sd_framesizes[fse.index].width = fse.max_width;
1510 dcmi->sd_framesizes[fse.index].height = fse.max_height;
1511 dev_dbg(dcmi->dev, "%ux%u\n", fse.max_width, fse.max_height);
1512 }
1513
1514 return 0;
1515 }
1516
1517 static int dcmi_graph_notify_complete(struct v4l2_async_notifier *notifier)
1518 {
1519 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1520 int ret;
1521
1522 dcmi->vdev->ctrl_handler = dcmi->entity.subdev->ctrl_handler;
1523 ret = dcmi_formats_init(dcmi);
1524 if (ret) {
1525 dev_err(dcmi->dev, "No supported mediabus format found\n");
1526 return ret;
1527 }
1528
1529 ret = dcmi_framesizes_init(dcmi);
1530 if (ret) {
1531 dev_err(dcmi->dev, "Could not initialize framesizes\n");
1532 return ret;
1533 }
1534
1535 ret = dcmi_get_sensor_bounds(dcmi, &dcmi->sd_bounds);
1536 if (ret) {
1537 dev_err(dcmi->dev, "Could not get sensor bounds\n");
1538 return ret;
1539 }
1540
1541 ret = dcmi_set_default_fmt(dcmi);
1542 if (ret) {
1543 dev_err(dcmi->dev, "Could not set default format\n");
1544 return ret;
1545 }
1546
1547 ret = video_register_device(dcmi->vdev, VFL_TYPE_GRABBER, -1);
1548 if (ret) {
1549 dev_err(dcmi->dev, "Failed to register video device\n");
1550 return ret;
1551 }
1552
1553 dev_dbg(dcmi->dev, "Device registered as %s\n",
1554 video_device_node_name(dcmi->vdev));
1555 return 0;
1556 }
1557
1558 static void dcmi_graph_notify_unbind(struct v4l2_async_notifier *notifier,
1559 struct v4l2_subdev *sd,
1560 struct v4l2_async_subdev *asd)
1561 {
1562 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1563
1564 dev_dbg(dcmi->dev, "Removing %s\n", video_device_node_name(dcmi->vdev));
1565
1566 /* Checks internaly if vdev has been init or not */
1567 video_unregister_device(dcmi->vdev);
1568 }
1569
1570 static int dcmi_graph_notify_bound(struct v4l2_async_notifier *notifier,
1571 struct v4l2_subdev *subdev,
1572 struct v4l2_async_subdev *asd)
1573 {
1574 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier);
1575
1576 dev_dbg(dcmi->dev, "Subdev %s bound\n", subdev->name);
1577
1578 dcmi->entity.subdev = subdev;
1579
1580 return 0;
1581 }
1582
1583 static const struct v4l2_async_notifier_operations dcmi_graph_notify_ops = {
1584 .bound = dcmi_graph_notify_bound,
1585 .unbind = dcmi_graph_notify_unbind,
1586 .complete = dcmi_graph_notify_complete,
1587 };
1588
1589 static int dcmi_graph_parse(struct stm32_dcmi *dcmi, struct device_node *node)
1590 {
1591 struct device_node *ep = NULL;
1592 struct device_node *remote;
1593
1594 ep = of_graph_get_next_endpoint(node, ep);
1595 if (!ep)
1596 return -EINVAL;
1597
1598 remote = of_graph_get_remote_port_parent(ep);
1599 of_node_put(ep);
1600 if (!remote)
1601 return -EINVAL;
1602
1603 /* Remote node to connect */
1604 dcmi->entity.node = remote;
1605 dcmi->entity.asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
1606 dcmi->entity.asd.match.fwnode = of_fwnode_handle(remote);
1607 return 0;
1608 }
1609
1610 static int dcmi_graph_init(struct stm32_dcmi *dcmi)
1611 {
1612 struct v4l2_async_subdev **subdevs = NULL;
1613 int ret;
1614
1615 /* Parse the graph to extract a list of subdevice DT nodes. */
1616 ret = dcmi_graph_parse(dcmi, dcmi->dev->of_node);
1617 if (ret < 0) {
1618 dev_err(dcmi->dev, "Graph parsing failed\n");
1619 return ret;
1620 }
1621
1622 /* Register the subdevices notifier. */
1623 subdevs = devm_kzalloc(dcmi->dev, sizeof(*subdevs), GFP_KERNEL);
1624 if (!subdevs) {
1625 of_node_put(dcmi->entity.node);
1626 return -ENOMEM;
1627 }
1628
1629 subdevs[0] = &dcmi->entity.asd;
1630
1631 dcmi->notifier.subdevs = subdevs;
1632 dcmi->notifier.num_subdevs = 1;
1633 dcmi->notifier.ops = &dcmi_graph_notify_ops;
1634
1635 ret = v4l2_async_notifier_register(&dcmi->v4l2_dev, &dcmi->notifier);
1636 if (ret < 0) {
1637 dev_err(dcmi->dev, "Notifier registration failed\n");
1638 of_node_put(dcmi->entity.node);
1639 return ret;
1640 }
1641
1642 return 0;
1643 }
1644
1645 static int dcmi_probe(struct platform_device *pdev)
1646 {
1647 struct device_node *np = pdev->dev.of_node;
1648 const struct of_device_id *match = NULL;
1649 struct v4l2_fwnode_endpoint ep;
1650 struct stm32_dcmi *dcmi;
1651 struct vb2_queue *q;
1652 struct dma_chan *chan;
1653 struct clk *mclk;
1654 int irq;
1655 int ret = 0;
1656
1657 match = of_match_device(of_match_ptr(stm32_dcmi_of_match), &pdev->dev);
1658 if (!match) {
1659 dev_err(&pdev->dev, "Could not find a match in devicetree\n");
1660 return -ENODEV;
1661 }
1662
1663 dcmi = devm_kzalloc(&pdev->dev, sizeof(struct stm32_dcmi), GFP_KERNEL);
1664 if (!dcmi)
1665 return -ENOMEM;
1666
1667 dcmi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1668 if (IS_ERR(dcmi->rstc)) {
1669 dev_err(&pdev->dev, "Could not get reset control\n");
1670 return PTR_ERR(dcmi->rstc);
1671 }
1672
1673 /* Get bus characteristics from devicetree */
1674 np = of_graph_get_next_endpoint(np, NULL);
1675 if (!np) {
1676 dev_err(&pdev->dev, "Could not find the endpoint\n");
1677 of_node_put(np);
1678 return -ENODEV;
1679 }
1680
1681 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep);
1682 of_node_put(np);
1683 if (ret) {
1684 dev_err(&pdev->dev, "Could not parse the endpoint\n");
1685 return ret;
1686 }
1687
1688 if (ep.bus_type == V4L2_MBUS_CSI2) {
1689 dev_err(&pdev->dev, "CSI bus not supported\n");
1690 return -ENODEV;
1691 }
1692 dcmi->bus.flags = ep.bus.parallel.flags;
1693 dcmi->bus.bus_width = ep.bus.parallel.bus_width;
1694 dcmi->bus.data_shift = ep.bus.parallel.data_shift;
1695
1696 irq = platform_get_irq(pdev, 0);
1697 if (irq <= 0) {
1698 if (irq != -EPROBE_DEFER)
1699 dev_err(&pdev->dev, "Could not get irq\n");
1700 return irq ? irq : -ENXIO;
1701 }
1702
1703 dcmi->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1704 if (!dcmi->res) {
1705 dev_err(&pdev->dev, "Could not get resource\n");
1706 return -ENODEV;
1707 }
1708
1709 dcmi->regs = devm_ioremap_resource(&pdev->dev, dcmi->res);
1710 if (IS_ERR(dcmi->regs)) {
1711 dev_err(&pdev->dev, "Could not map registers\n");
1712 return PTR_ERR(dcmi->regs);
1713 }
1714
1715 ret = devm_request_threaded_irq(&pdev->dev, irq, dcmi_irq_callback,
1716 dcmi_irq_thread, IRQF_ONESHOT,
1717 dev_name(&pdev->dev), dcmi);
1718 if (ret) {
1719 dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
1720 return ret;
1721 }
1722
1723 mclk = devm_clk_get(&pdev->dev, "mclk");
1724 if (IS_ERR(mclk)) {
1725 if (PTR_ERR(mclk) != -EPROBE_DEFER)
1726 dev_err(&pdev->dev, "Unable to get mclk\n");
1727 return PTR_ERR(mclk);
1728 }
1729
1730 chan = dma_request_slave_channel(&pdev->dev, "tx");
1731 if (!chan) {
1732 dev_info(&pdev->dev, "Unable to request DMA channel, defer probing\n");
1733 return -EPROBE_DEFER;
1734 }
1735
1736 spin_lock_init(&dcmi->irqlock);
1737 mutex_init(&dcmi->lock);
1738 mutex_init(&dcmi->dma_lock);
1739 init_completion(&dcmi->complete);
1740 INIT_LIST_HEAD(&dcmi->buffers);
1741
1742 dcmi->dev = &pdev->dev;
1743 dcmi->mclk = mclk;
1744 dcmi->state = STOPPED;
1745 dcmi->dma_chan = chan;
1746
1747 q = &dcmi->queue;
1748
1749 /* Initialize the top-level structure */
1750 ret = v4l2_device_register(&pdev->dev, &dcmi->v4l2_dev);
1751 if (ret)
1752 goto err_dma_release;
1753
1754 dcmi->vdev = video_device_alloc();
1755 if (!dcmi->vdev) {
1756 ret = -ENOMEM;
1757 goto err_device_unregister;
1758 }
1759
1760 /* Video node */
1761 dcmi->vdev->fops = &dcmi_fops;
1762 dcmi->vdev->v4l2_dev = &dcmi->v4l2_dev;
1763 dcmi->vdev->queue = &dcmi->queue;
1764 strlcpy(dcmi->vdev->name, KBUILD_MODNAME, sizeof(dcmi->vdev->name));
1765 dcmi->vdev->release = video_device_release;
1766 dcmi->vdev->ioctl_ops = &dcmi_ioctl_ops;
1767 dcmi->vdev->lock = &dcmi->lock;
1768 dcmi->vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
1769 V4L2_CAP_READWRITE;
1770 video_set_drvdata(dcmi->vdev, dcmi);
1771
1772 /* Buffer queue */
1773 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1774 q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1775 q->lock = &dcmi->lock;
1776 q->drv_priv = dcmi;
1777 q->buf_struct_size = sizeof(struct dcmi_buf);
1778 q->ops = &dcmi_video_qops;
1779 q->mem_ops = &vb2_dma_contig_memops;
1780 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1781 q->min_buffers_needed = 2;
1782 q->dev = &pdev->dev;
1783
1784 ret = vb2_queue_init(q);
1785 if (ret < 0) {
1786 dev_err(&pdev->dev, "Failed to initialize vb2 queue\n");
1787 goto err_device_release;
1788 }
1789
1790 ret = dcmi_graph_init(dcmi);
1791 if (ret < 0)
1792 goto err_device_release;
1793
1794 /* Reset device */
1795 ret = reset_control_assert(dcmi->rstc);
1796 if (ret) {
1797 dev_err(&pdev->dev, "Failed to assert the reset line\n");
1798 goto err_device_release;
1799 }
1800
1801 usleep_range(3000, 5000);
1802
1803 ret = reset_control_deassert(dcmi->rstc);
1804 if (ret) {
1805 dev_err(&pdev->dev, "Failed to deassert the reset line\n");
1806 goto err_device_release;
1807 }
1808
1809 dev_info(&pdev->dev, "Probe done\n");
1810
1811 platform_set_drvdata(pdev, dcmi);
1812
1813 pm_runtime_enable(&pdev->dev);
1814
1815 return 0;
1816
1817 err_device_release:
1818 video_device_release(dcmi->vdev);
1819 err_device_unregister:
1820 v4l2_device_unregister(&dcmi->v4l2_dev);
1821 err_dma_release:
1822 dma_release_channel(dcmi->dma_chan);
1823
1824 return ret;
1825 }
1826
1827 static int dcmi_remove(struct platform_device *pdev)
1828 {
1829 struct stm32_dcmi *dcmi = platform_get_drvdata(pdev);
1830
1831 pm_runtime_disable(&pdev->dev);
1832
1833 v4l2_async_notifier_unregister(&dcmi->notifier);
1834 v4l2_device_unregister(&dcmi->v4l2_dev);
1835
1836 dma_release_channel(dcmi->dma_chan);
1837
1838 return 0;
1839 }
1840
1841 static __maybe_unused int dcmi_runtime_suspend(struct device *dev)
1842 {
1843 struct stm32_dcmi *dcmi = dev_get_drvdata(dev);
1844
1845 clk_disable_unprepare(dcmi->mclk);
1846
1847 return 0;
1848 }
1849
1850 static __maybe_unused int dcmi_runtime_resume(struct device *dev)
1851 {
1852 struct stm32_dcmi *dcmi = dev_get_drvdata(dev);
1853 int ret;
1854
1855 ret = clk_prepare_enable(dcmi->mclk);
1856 if (ret)
1857 dev_err(dev, "%s: Failed to prepare_enable clock\n", __func__);
1858
1859 return ret;
1860 }
1861
1862 static __maybe_unused int dcmi_suspend(struct device *dev)
1863 {
1864 /* disable clock */
1865 pm_runtime_force_suspend(dev);
1866
1867 /* change pinctrl state */
1868 pinctrl_pm_select_sleep_state(dev);
1869
1870 return 0;
1871 }
1872
1873 static __maybe_unused int dcmi_resume(struct device *dev)
1874 {
1875 /* restore pinctl default state */
1876 pinctrl_pm_select_default_state(dev);
1877
1878 /* clock enable */
1879 pm_runtime_force_resume(dev);
1880
1881 return 0;
1882 }
1883
1884 static const struct dev_pm_ops dcmi_pm_ops = {
1885 SET_SYSTEM_SLEEP_PM_OPS(dcmi_suspend, dcmi_resume)
1886 SET_RUNTIME_PM_OPS(dcmi_runtime_suspend,
1887 dcmi_runtime_resume, NULL)
1888 };
1889
1890 static struct platform_driver stm32_dcmi_driver = {
1891 .probe = dcmi_probe,
1892 .remove = dcmi_remove,
1893 .driver = {
1894 .name = DRV_NAME,
1895 .of_match_table = of_match_ptr(stm32_dcmi_of_match),
1896 .pm = &dcmi_pm_ops,
1897 },
1898 };
1899
1900 module_platform_driver(stm32_dcmi_driver);
1901
1902 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1903 MODULE_AUTHOR("Hugues Fruchet <hugues.fruchet@st.com>");
1904 MODULE_DESCRIPTION("STMicroelectronics STM32 Digital Camera Memory Interface driver");
1905 MODULE_LICENSE("GPL");
1906 MODULE_SUPPORTED_DEVICE("video");
Linux with added FPC-III support