drivers/media/platform/vsp1/vsp1_pipe.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * vsp1_pipe.c  --  R-Car VSP1 Pipeline
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/list.h>
  12 #include <linux/sched.h>
  13 #include <linux/wait.h>
  14
  15 #include <media/media-entity.h>
  16 #include <media/v4l2-subdev.h>
  17
  18 #include "vsp1.h"
  19 #include "vsp1_brx.h"
  20 #include "vsp1_dl.h"
  21 #include "vsp1_entity.h"
  22 #include "vsp1_hgo.h"
  23 #include "vsp1_hgt.h"
  24 #include "vsp1_pipe.h"
  25 #include "vsp1_rwpf.h"
  26 #include "vsp1_uds.h"
  27
  28 /* -----------------------------------------------------------------------------
  29  * Helper Functions
  30  */
  31
  32 static const struct vsp1_format_info vsp1_video_formats[] = {
  33         { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
  34           VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  35           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  36           1, { 8, 0, 0 }, false, false, 1, 1, false },
  37         { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  38           VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  39           VI6_RPF_DSWAP_P_WDS,
  40           1, { 16, 0, 0 }, false, false, 1, 1, true },
  41         { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  42           VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  43           VI6_RPF_DSWAP_P_WDS,
  44           1, { 16, 0, 0 }, false, false, 1, 1, false },
  45         { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  46           VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  47           VI6_RPF_DSWAP_P_WDS,
  48           1, { 16, 0, 0 }, false, false, 1, 1, true },
  49         { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  50           VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  51           VI6_RPF_DSWAP_P_WDS,
  52           1, { 16, 0, 0 }, false, false, 1, 1, false },
  53         { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
  54           VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  55           VI6_RPF_DSWAP_P_WDS,
  56           1, { 16, 0, 0 }, false, false, 1, 1, false },
  57         { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
  58           VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  59           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  60           1, { 24, 0, 0 }, false, false, 1, 1, false },
  61         { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
  62           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  63           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  64           1, { 24, 0, 0 }, false, false, 1, 1, false },
  65         { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  66           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  67           1, { 32, 0, 0 }, false, false, 1, 1, true },
  68         { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  69           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  70           1, { 32, 0, 0 }, false, false, 1, 1, false },
  71         { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  72           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  73           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  74           1, { 32, 0, 0 }, false, false, 1, 1, true },
  75         { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  76           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  77           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  78           1, { 32, 0, 0 }, false, false, 1, 1, false },
  79         { V4L2_PIX_FMT_HSV24, MEDIA_BUS_FMT_AHSV8888_1X32,
  80           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  81           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  82           1, { 24, 0, 0 }, false, false, 1, 1, false },
  83         { V4L2_PIX_FMT_HSV32, MEDIA_BUS_FMT_AHSV8888_1X32,
  84           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  85           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  86           1, { 32, 0, 0 }, false, false, 1, 1, false },
  87         { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
  88           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  89           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  90           1, { 16, 0, 0 }, false, false, 2, 1, false },
  91         { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
  92           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  93           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  94           1, { 16, 0, 0 }, false, true, 2, 1, false },
  95         { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
  96           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  97           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  98           1, { 16, 0, 0 }, true, false, 2, 1, false },
  99         { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
 100           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 101           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 102           1, { 16, 0, 0 }, true, true, 2, 1, false },
 103         { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
 104           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 105           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 106           2, { 8, 16, 0 }, false, false, 2, 2, false },
 107         { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
 108           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 109           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 110           2, { 8, 16, 0 }, false, true, 2, 2, false },
 111         { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
 112           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 113           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 114           2, { 8, 16, 0 }, false, false, 2, 1, false },
 115         { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
 116           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 117           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 118           2, { 8, 16, 0 }, false, true, 2, 1, false },
 119         { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
 120           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 121           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 122           3, { 8, 8, 8 }, false, false, 2, 2, false },
 123         { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
 124           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 125           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 126           3, { 8, 8, 8 }, false, true, 2, 2, false },
 127         { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
 128           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 129           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 130           3, { 8, 8, 8 }, false, false, 2, 1, false },
 131         { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
 132           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 133           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 134           3, { 8, 8, 8 }, false, true, 2, 1, false },
 135         { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
 136           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 137           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 138           3, { 8, 8, 8 }, false, false, 1, 1, false },
 139         { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
 140           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 141           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 142           3, { 8, 8, 8 }, false, true, 1, 1, false },
 143 };
 144
 145 /**
 146  * vsp1_get_format_info - Retrieve format information for a 4CC
 147  * @vsp1: the VSP1 device
 148  * @fourcc: the format 4CC
 149  *
 150  * Return a pointer to the format information structure corresponding to the
 151  * given V4L2 format 4CC, or NULL if no corresponding format can be found.
 152  */
 153 const struct vsp1_format_info *vsp1_get_format_info(struct vsp1_device *vsp1,
 154                                                     u32 fourcc)
 155 {
 156         unsigned int i;
 157
 158         /* Special case, the VYUY and HSV formats are supported on Gen2 only. */
 159         if (vsp1->info->gen != 2) {
 160                 switch (fourcc) {
 161                 case V4L2_PIX_FMT_VYUY:
 162                 case V4L2_PIX_FMT_HSV24:
 163                 case V4L2_PIX_FMT_HSV32:
 164                         return NULL;
 165                 }
 166         }
 167
 168         for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
 169                 const struct vsp1_format_info *info = &vsp1_video_formats[i];
 170
 171                 if (info->fourcc == fourcc)
 172                         return info;
 173         }
 174
 175         return NULL;
 176 }
 177
 178 /* -----------------------------------------------------------------------------
 179  * Pipeline Management
 180  */
 181
 182 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
 183 {
 184         struct vsp1_entity *entity;
 185         unsigned int i;
 186
 187         if (pipe->brx) {
 188                 struct vsp1_brx *brx = to_brx(&pipe->brx->subdev);
 189
 190                 for (i = 0; i < ARRAY_SIZE(brx->inputs); ++i)
 191                         brx->inputs[i].rpf = NULL;
 192         }
 193
 194         for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i)
 195                 pipe->inputs[i] = NULL;
 196
 197         pipe->output = NULL;
 198
 199         list_for_each_entry(entity, &pipe->entities, list_pipe)
 200                 entity->pipe = NULL;
 201
 202         INIT_LIST_HEAD(&pipe->entities);
 203         pipe->state = VSP1_PIPELINE_STOPPED;
 204         pipe->buffers_ready = 0;
 205         pipe->num_inputs = 0;
 206         pipe->brx = NULL;
 207         pipe->hgo = NULL;
 208         pipe->hgt = NULL;
 209         pipe->lif = NULL;
 210         pipe->uds = NULL;
 211 }
 212
 213 void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
 214 {
 215         mutex_init(&pipe->lock);
 216         spin_lock_init(&pipe->irqlock);
 217         init_waitqueue_head(&pipe->wq);
 218         kref_init(&pipe->kref);
 219
 220         INIT_LIST_HEAD(&pipe->entities);
 221         pipe->state = VSP1_PIPELINE_STOPPED;
 222 }
 223
 224 /* Must be called with the pipe irqlock held. */
 225 void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
 226 {
 227         struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 228
 229         if (pipe->state == VSP1_PIPELINE_STOPPED) {
 230                 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
 231                            VI6_CMD_STRCMD);
 232                 pipe->state = VSP1_PIPELINE_RUNNING;
 233         }
 234
 235         pipe->buffers_ready = 0;
 236 }
 237
 238 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
 239 {
 240         unsigned long flags;
 241         bool stopped;
 242
 243         spin_lock_irqsave(&pipe->irqlock, flags);
 244         stopped = pipe->state == VSP1_PIPELINE_STOPPED;
 245         spin_unlock_irqrestore(&pipe->irqlock, flags);
 246
 247         return stopped;
 248 }
 249
 250 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
 251 {
 252         struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 253         struct vsp1_entity *entity;
 254         unsigned long flags;
 255         int ret;
 256
 257         if (pipe->lif) {
 258                 /*
 259                  * When using display lists in continuous frame mode the only
 260                  * way to stop the pipeline is to reset the hardware.
 261                  */
 262                 ret = vsp1_reset_wpf(vsp1, pipe->output->entity.index);
 263                 if (ret == 0) {
 264                         spin_lock_irqsave(&pipe->irqlock, flags);
 265                         pipe->state = VSP1_PIPELINE_STOPPED;
 266                         spin_unlock_irqrestore(&pipe->irqlock, flags);
 267                 }
 268         } else {
 269                 /* Otherwise just request a stop and wait. */
 270                 spin_lock_irqsave(&pipe->irqlock, flags);
 271                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 272                         pipe->state = VSP1_PIPELINE_STOPPING;
 273                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 274
 275                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 276                                          msecs_to_jiffies(500));
 277                 ret = ret == 0 ? -ETIMEDOUT : 0;
 278         }
 279
 280         list_for_each_entry(entity, &pipe->entities, list_pipe) {
 281                 if (entity->route && entity->route->reg)
 282                         vsp1_write(vsp1, entity->route->reg,
 283                                    VI6_DPR_NODE_UNUSED);
 284         }
 285
 286         if (pipe->hgo)
 287                 vsp1_write(vsp1, VI6_DPR_HGO_SMPPT,
 288                            (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
 289                            (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
 290
 291         if (pipe->hgt)
 292                 vsp1_write(vsp1, VI6_DPR_HGT_SMPPT,
 293                            (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
 294                            (VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
 295
 296         v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);
 297
 298         return ret;
 299 }
 300
 301 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
 302 {
 303         unsigned int mask;
 304
 305         mask = ((1 << pipe->num_inputs) - 1) << 1;
 306         if (!pipe->lif)
 307                 mask |= 1 << 0;
 308
 309         return pipe->buffers_ready == mask;
 310 }
 311
 312 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
 313 {
 314         unsigned int flags;
 315
 316         if (pipe == NULL)
 317                 return;
 318
 319         /*
 320          * If the DL commit raced with the frame end interrupt, the commit ends
 321          * up being postponed by one frame. The returned flags tell whether the
 322          * active frame was finished or postponed.
 323          */
 324         flags = vsp1_dlm_irq_frame_end(pipe->output->dlm);
 325
 326         if (pipe->hgo)
 327                 vsp1_hgo_frame_end(pipe->hgo);
 328
 329         if (pipe->hgt)
 330                 vsp1_hgt_frame_end(pipe->hgt);
 331
 332         /*
 333          * Regardless of frame completion we still need to notify the pipe
 334          * frame_end to account for vblank events.
 335          */
 336         if (pipe->frame_end)
 337                 pipe->frame_end(pipe, flags);
 338
 339         pipe->sequence++;
 340 }
 341
 342 /*
 343  * Propagate the alpha value through the pipeline.
 344  *
 345  * As the UDS has restricted scaling capabilities when the alpha component needs
 346  * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
 347  * value. The UDS then outputs a fixed alpha value which needs to be programmed
 348  * from the input RPF alpha.
 349  */
 350 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
 351                                    struct vsp1_dl_body *dlb, unsigned int alpha)
 352 {
 353         if (!pipe->uds)
 354                 return;
 355
 356         /*
 357          * The BRU and BRS background color has a fixed alpha value set to 255,
 358          * the output alpha value is thus always equal to 255.
 359          */
 360         if (pipe->uds_input->type == VSP1_ENTITY_BRU ||
 361             pipe->uds_input->type == VSP1_ENTITY_BRS)
 362                 alpha = 255;
 363
 364         vsp1_uds_set_alpha(pipe->uds, dlb, alpha);
 365 }
 366
 367 /*
 368  * Propagate the partition calculations through the pipeline
 369  *
 370  * Work backwards through the pipe, allowing each entity to update the partition
 371  * parameters based on its configuration, and the entity connected to its
 372  * source. Each entity must produce the partition required for the previous
 373  * entity in the pipeline.
 374  */
 375 void vsp1_pipeline_propagate_partition(struct vsp1_pipeline *pipe,
 376                                        struct vsp1_partition *partition,
 377                                        unsigned int index,
 378                                        struct vsp1_partition_window *window)
 379 {
 380         struct vsp1_entity *entity;
 381
 382         list_for_each_entry_reverse(entity, &pipe->entities, list_pipe) {
 383                 if (entity->ops->partition)
 384                         entity->ops->partition(entity, pipe, partition, index,
 385                                                window);
 386         }
 387 }
 388